Unified Coverage Report :: Module :: usbdev_reg_top

Module : usbdev_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.94	99.59	98.10			98.08	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	98.94	99.59	98.10			98.08	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.94	99.59	98.10			98.08	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.93	98.21	96.59	100.00		97.74	87.10

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.25	96.75	68.07	93.93		87.50	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_avoutbuffer	100.00	100.00	100.00			100.00
u_avoutbuffer0_qe	100.00	100.00				100.00
u_avsetupbuffer	100.00	100.00	100.00			100.00
u_avsetupbuffer0_qe	100.00	100.00				100.00
u_chk	100.00	100.00		100.00			100.00
u_configin_0_buffer_0	100.00	100.00	100.00			100.00
u_configin_0_pend_0	97.22	100.00	91.67			100.00
u_configin_0_rdy_0	100.00	100.00	100.00			100.00
u_configin_0_sending_0	97.22	100.00	91.67			100.00
u_configin_0_size_0	100.00	100.00	100.00			100.00
u_configin_10_buffer_10	100.00	100.00	100.00			100.00
u_configin_10_pend_10	100.00	100.00	100.00			100.00
u_configin_10_rdy_10	100.00	100.00	100.00			100.00
u_configin_10_sending_10	97.22	100.00	91.67			100.00
u_configin_10_size_10	100.00	100.00	100.00			100.00
u_configin_11_buffer_11	100.00	100.00	100.00			100.00
u_configin_11_pend_11	97.22	100.00	91.67			100.00
u_configin_11_rdy_11	100.00	100.00	100.00			100.00
u_configin_11_sending_11	97.22	100.00	91.67			100.00
u_configin_11_size_11	100.00	100.00	100.00			100.00
u_configin_1_buffer_1	100.00	100.00	100.00			100.00
u_configin_1_pend_1	97.22	100.00	91.67			100.00
u_configin_1_rdy_1	100.00	100.00	100.00			100.00
u_configin_1_sending_1	97.22	100.00	91.67			100.00
u_configin_1_size_1	100.00	100.00	100.00			100.00
u_configin_2_buffer_2	100.00	100.00	100.00			100.00
u_configin_2_pend_2	97.22	100.00	91.67			100.00
u_configin_2_rdy_2	100.00	100.00	100.00			100.00
u_configin_2_sending_2	97.22	100.00	91.67			100.00
u_configin_2_size_2	100.00	100.00	100.00			100.00
u_configin_3_buffer_3	100.00	100.00	100.00			100.00
u_configin_3_pend_3	97.22	100.00	91.67			100.00
u_configin_3_rdy_3	100.00	100.00	100.00			100.00
u_configin_3_sending_3	97.22	100.00	91.67			100.00
u_configin_3_size_3	100.00	100.00	100.00			100.00
u_configin_4_buffer_4	100.00	100.00	100.00			100.00
u_configin_4_pend_4	97.22	100.00	91.67			100.00
u_configin_4_rdy_4	100.00	100.00	100.00			100.00
u_configin_4_sending_4	97.22	100.00	91.67			100.00
u_configin_4_size_4	100.00	100.00	100.00			100.00
u_configin_5_buffer_5	100.00	100.00	100.00			100.00
u_configin_5_pend_5	97.22	100.00	91.67			100.00
u_configin_5_rdy_5	100.00	100.00	100.00			100.00
u_configin_5_sending_5	97.22	100.00	91.67			100.00
u_configin_5_size_5	100.00	100.00	100.00			100.00
u_configin_6_buffer_6	100.00	100.00	100.00			100.00
u_configin_6_pend_6	97.22	100.00	91.67			100.00
u_configin_6_rdy_6	100.00	100.00	100.00			100.00
u_configin_6_sending_6	97.22	100.00	91.67			100.00
u_configin_6_size_6	100.00	100.00	100.00			100.00
u_configin_7_buffer_7	100.00	100.00	100.00			100.00
u_configin_7_pend_7	97.22	100.00	91.67			100.00
u_configin_7_rdy_7	100.00	100.00	100.00			100.00
u_configin_7_sending_7	97.22	100.00	91.67			100.00
u_configin_7_size_7	100.00	100.00	100.00			100.00
u_configin_8_buffer_8	100.00	100.00	100.00			100.00
u_configin_8_pend_8	97.22	100.00	91.67			100.00
u_configin_8_rdy_8	100.00	100.00	100.00			100.00
u_configin_8_sending_8	97.22	100.00	91.67			100.00
u_configin_8_size_8	100.00	100.00	100.00			100.00
u_configin_9_buffer_9	100.00	100.00	100.00			100.00
u_configin_9_pend_9	97.22	100.00	91.67			100.00
u_configin_9_rdy_9	100.00	100.00	100.00			100.00
u_configin_9_sending_9	97.22	100.00	91.67			100.00
u_configin_9_size_9	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_0	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_1	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_10	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_11	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_2	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_3	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_4	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_5	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_6	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_7	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_8	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_9	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_0	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_1	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_10	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_11	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_2	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_3	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_4	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_5	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_6	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_7	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_8	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_9	100.00	100.00	100.00			100.00
u_fifo_ctrl0_qe	100.00	100.00				100.00
u_fifo_ctrl_avout_rst	100.00	100.00	100.00			100.00
u_fifo_ctrl_avsetup_rst	100.00	100.00	100.00			100.00
u_fifo_ctrl_rx_rst	100.00	100.00	100.00			100.00
u_in_data_toggle_mask	60.00	60.00
u_in_data_toggle_status	100.00	100.00
u_in_iso_iso_0	100.00	100.00	100.00			100.00
u_in_iso_iso_1	100.00	100.00	100.00			100.00
u_in_iso_iso_10	100.00	100.00	100.00			100.00
u_in_iso_iso_11	100.00	100.00	100.00			100.00
u_in_iso_iso_2	100.00	100.00	100.00			100.00
u_in_iso_iso_3	100.00	100.00	100.00			100.00
u_in_iso_iso_4	100.00	100.00	100.00			100.00
u_in_iso_iso_5	100.00	100.00	100.00			100.00
u_in_iso_iso_6	100.00	100.00	100.00			100.00
u_in_iso_iso_7	100.00	100.00	100.00			100.00
u_in_iso_iso_8	100.00	100.00	100.00			100.00
u_in_iso_iso_9	100.00	100.00	100.00			100.00
u_in_sent_sent_0	100.00	100.00	100.00			100.00
u_in_sent_sent_1	100.00	100.00	100.00			100.00
u_in_sent_sent_10	100.00	100.00	100.00			100.00
u_in_sent_sent_11	100.00	100.00	100.00			100.00
u_in_sent_sent_2	100.00	100.00	100.00			100.00
u_in_sent_sent_3	100.00	100.00	100.00			100.00
u_in_sent_sent_4	100.00	100.00	100.00			100.00
u_in_sent_sent_5	100.00	100.00	100.00			100.00
u_in_sent_sent_6	100.00	100.00	100.00			100.00
u_in_sent_sent_7	100.00	100.00	100.00			100.00
u_in_sent_sent_8	100.00	100.00	100.00			100.00
u_in_sent_sent_9	100.00	100.00	100.00			100.00
u_in_stall_endpoint_0	100.00	100.00	100.00			100.00
u_in_stall_endpoint_1	100.00	100.00	100.00			100.00
u_in_stall_endpoint_10	100.00	100.00	100.00			100.00
u_in_stall_endpoint_11	100.00	100.00	100.00			100.00
u_in_stall_endpoint_2	100.00	100.00	100.00			100.00
u_in_stall_endpoint_3	100.00	100.00	100.00			100.00
u_in_stall_endpoint_4	100.00	100.00	100.00			100.00
u_in_stall_endpoint_5	100.00	100.00	100.00			100.00
u_in_stall_endpoint_6	100.00	100.00	100.00			100.00
u_in_stall_endpoint_7	100.00	100.00	100.00			100.00
u_in_stall_endpoint_8	100.00	100.00	100.00			100.00
u_in_stall_endpoint_9	100.00	100.00	100.00			100.00
u_intr_enable_av_out_empty	100.00	100.00	100.00			100.00
u_intr_enable_av_overflow	100.00	100.00	100.00			100.00
u_intr_enable_av_setup_empty	100.00	100.00	100.00			100.00
u_intr_enable_disconnected	100.00	100.00	100.00			100.00
u_intr_enable_frame	100.00	100.00	100.00			100.00
u_intr_enable_host_lost	100.00	100.00	100.00			100.00
u_intr_enable_link_in_err	100.00	100.00	100.00			100.00
u_intr_enable_link_out_err	100.00	100.00	100.00			100.00
u_intr_enable_link_reset	100.00	100.00	100.00			100.00
u_intr_enable_link_resume	100.00	100.00	100.00			100.00
u_intr_enable_link_suspend	100.00	100.00	100.00			100.00
u_intr_enable_pkt_received	100.00	100.00	100.00			100.00
u_intr_enable_pkt_sent	100.00	100.00	100.00			100.00
u_intr_enable_powered	100.00	100.00	100.00			100.00
u_intr_enable_rx_bitstuff_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_crc_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_full	100.00	100.00	100.00			100.00
u_intr_enable_rx_pid_err	100.00	100.00	100.00			100.00
u_intr_state_av_out_empty	62.59	77.78	50.00			60.00
u_intr_state_av_overflow	100.00	100.00	100.00			100.00
u_intr_state_av_setup_empty	62.59	77.78	50.00			60.00
u_intr_state_disconnected	100.00	100.00	100.00			100.00
u_intr_state_frame	100.00	100.00	100.00			100.00
u_intr_state_host_lost	100.00	100.00	100.00			100.00
u_intr_state_link_in_err	100.00	100.00	100.00			100.00
u_intr_state_link_out_err	100.00	100.00	100.00			100.00
u_intr_state_link_reset	100.00	100.00	100.00			100.00
u_intr_state_link_resume	100.00	100.00	100.00			100.00
u_intr_state_link_suspend	100.00	100.00	100.00			100.00
u_intr_state_pkt_received	62.59	77.78	50.00			60.00
u_intr_state_pkt_sent	62.59	77.78	50.00			60.00
u_intr_state_powered	100.00	100.00	100.00			100.00
u_intr_state_rx_bitstuff_err	100.00	100.00	100.00			100.00
u_intr_state_rx_crc_err	100.00	100.00	100.00			100.00
u_intr_state_rx_full	62.59	77.78	50.00			60.00
u_intr_state_rx_pid_err	100.00	100.00	100.00			100.00
u_intr_test_av_out_empty	100.00	100.00
u_intr_test_av_overflow	100.00	100.00
u_intr_test_av_setup_empty	100.00	100.00
u_intr_test_disconnected	100.00	100.00
u_intr_test_frame	100.00	100.00
u_intr_test_host_lost	100.00	100.00
u_intr_test_link_in_err	100.00	100.00
u_intr_test_link_out_err	100.00	100.00
u_intr_test_link_reset	100.00	100.00
u_intr_test_link_resume	100.00	100.00
u_intr_test_link_suspend	100.00	100.00
u_intr_test_pkt_received	100.00	100.00
u_intr_test_pkt_sent	100.00	100.00
u_intr_test_powered	100.00	100.00
u_intr_test_rx_bitstuff_err	100.00	100.00
u_intr_test_rx_crc_err	100.00	100.00
u_intr_test_rx_full	100.00	100.00
u_intr_test_rx_pid_err	100.00	100.00
u_out_data_toggle_mask	60.00	60.00
u_out_data_toggle_status	100.00	100.00
u_out_iso_iso_0	100.00	100.00	100.00			100.00
u_out_iso_iso_1	100.00	100.00	100.00			100.00
u_out_iso_iso_10	100.00	100.00	100.00			100.00
u_out_iso_iso_11	100.00	100.00	100.00			100.00
u_out_iso_iso_2	100.00	100.00	100.00			100.00
u_out_iso_iso_3	100.00	100.00	100.00			100.00
u_out_iso_iso_4	100.00	100.00	100.00			100.00
u_out_iso_iso_5	100.00	100.00	100.00			100.00
u_out_iso_iso_6	100.00	100.00	100.00			100.00
u_out_iso_iso_7	100.00	100.00	100.00			100.00
u_out_iso_iso_8	100.00	100.00	100.00			100.00
u_out_iso_iso_9	100.00	100.00	100.00			100.00
u_out_stall_endpoint_0	100.00	100.00	100.00			100.00
u_out_stall_endpoint_1	100.00	100.00	100.00			100.00
u_out_stall_endpoint_10	100.00	100.00	100.00			100.00
u_out_stall_endpoint_11	100.00	100.00	100.00			100.00
u_out_stall_endpoint_2	100.00	100.00	100.00			100.00
u_out_stall_endpoint_3	100.00	100.00	100.00			100.00
u_out_stall_endpoint_4	100.00	100.00	100.00			100.00
u_out_stall_endpoint_5	100.00	100.00	100.00			100.00
u_out_stall_endpoint_6	100.00	100.00	100.00			100.00
u_out_stall_endpoint_7	100.00	100.00	100.00			100.00
u_out_stall_endpoint_8	100.00	100.00	100.00			100.00
u_out_stall_endpoint_9	100.00	100.00	100.00			100.00
u_phy_config_eop_single_bit	100.00	100.00	100.00			100.00
u_phy_config_pinflip	100.00	100.00	100.00			100.00
u_phy_config_tx_osc_test_mode	100.00	100.00	100.00			100.00
u_phy_config_tx_use_d_se0	100.00	100.00	100.00			100.00
u_phy_config_usb_ref_disable	100.00	100.00	100.00			100.00
u_phy_config_use_diff_rcvr	100.00	100.00	100.00			100.00
u_phy_pins_drive_d_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dn_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dn_pullup_en_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dp_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dp_pullup_en_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_en	100.00	100.00	100.00			100.00
u_phy_pins_drive_oe_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_rx_enable_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_se0_o	100.00	100.00	100.00			100.00
u_phy_pins_sense_pwr_sense	100.00	100.00
u_phy_pins_sense_rx_d_i	100.00	100.00
u_phy_pins_sense_rx_dn_i	100.00	100.00
u_phy_pins_sense_rx_dp_i	100.00	100.00
u_phy_pins_sense_tx_d_o	100.00	100.00
u_phy_pins_sense_tx_dn_o	100.00	100.00
u_phy_pins_sense_tx_dp_o	100.00	100.00
u_phy_pins_sense_tx_oe_o	100.00	100.00
u_phy_pins_sense_tx_se0_o	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_rxenable_out_out_0	100.00	100.00	100.00			100.00
u_rxenable_out_out_1	100.00	100.00	100.00			100.00
u_rxenable_out_out_10	100.00	100.00	100.00			100.00
u_rxenable_out_out_11	100.00	100.00	100.00			100.00
u_rxenable_out_out_2	100.00	100.00	100.00			100.00
u_rxenable_out_out_3	100.00	100.00	100.00			100.00
u_rxenable_out_out_4	100.00	100.00	100.00			100.00
u_rxenable_out_out_5	100.00	100.00	100.00			100.00
u_rxenable_out_out_6	100.00	100.00	100.00			100.00
u_rxenable_out_out_7	100.00	100.00	100.00			100.00
u_rxenable_out_out_8	100.00	100.00	100.00			100.00
u_rxenable_out_out_9	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_0	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_1	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_10	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_11	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_2	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_3	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_4	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_5	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_6	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_7	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_8	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_9	100.00	100.00	100.00			100.00
u_rxfifo_buffer	100.00	100.00
u_rxfifo_ep	100.00	100.00
u_rxfifo_setup	100.00	100.00
u_rxfifo_size	100.00	100.00
u_set_nak_out_enable_0	100.00	100.00	100.00			100.00
u_set_nak_out_enable_1	100.00	100.00	100.00			100.00
u_set_nak_out_enable_10	100.00	100.00	100.00			100.00
u_set_nak_out_enable_11	100.00	100.00	100.00			100.00
u_set_nak_out_enable_2	100.00	100.00	100.00			100.00
u_set_nak_out_enable_3	100.00	100.00	100.00			100.00
u_set_nak_out_enable_4	100.00	100.00	100.00			100.00
u_set_nak_out_enable_5	100.00	100.00	100.00			100.00
u_set_nak_out_enable_6	100.00	100.00	100.00			100.00
u_set_nak_out_enable_7	100.00	100.00	100.00			100.00
u_set_nak_out_enable_8	100.00	100.00	100.00			100.00
u_set_nak_out_enable_9	100.00	100.00	100.00			100.00
u_socket	98.24	98.75	98.21			96.00	100.00
u_usbctrl0_qe	100.00	100.00				100.00
u_usbctrl_device_address	96.30	100.00	88.89			100.00
u_usbctrl_enable	100.00	100.00	100.00			100.00
u_usbctrl_resume_link_active	100.00	100.00	100.00			100.00
u_usbstat_av_out_depth	100.00	100.00
u_usbstat_av_out_full	100.00	100.00
u_usbstat_av_setup_depth	100.00	100.00
u_usbstat_av_setup_full	100.00	100.00
u_usbstat_frame	100.00	100.00
u_usbstat_host_lost	100.00	100.00
u_usbstat_link_state	100.00	100.00
u_usbstat_rx_depth	100.00	100.00
u_usbstat_rx_empty	100.00	100.00
u_usbstat_sense	100.00	100.00
u_wake_control_cdc	98.13	96.08	96.43			100.00	100.00
u_wake_control_suspend_req	100.00	100.00
u_wake_control_wake_ack	100.00	100.00
u_wake_events_bus_reset	58.89	66.67	50.00			60.00
u_wake_events_cdc	45.74	76.56	25.00			61.40	20.00
u_wake_events_disconnected	58.89	66.67	50.00			60.00
u_wake_events_module_active	58.89	66.67	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev_reg_top

	Line No.	Total	Covered	Percent
TOTAL		736	733	99.59
ALWAYS	75	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
ALWAYS	132	3	2	66.67
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
ALWAYS	745	1	0	0.00
CONT_ASSIGN	772	1	1	100.00
ALWAYS	786	8	8	100.00
CONT_ASSIGN	1801	1	1	100.00
CONT_ASSIGN	1816	1	1	100.00
CONT_ASSIGN	1832	1	1	100.00
CONT_ASSIGN	1848	1	1	100.00
CONT_ASSIGN	1864	1	1	100.00
CONT_ASSIGN	1880	1	1	100.00
CONT_ASSIGN	1896	1	1	100.00
CONT_ASSIGN	1912	1	1	100.00
CONT_ASSIGN	1928	1	1	100.00
CONT_ASSIGN	1944	1	1	100.00
CONT_ASSIGN	1960	1	1	100.00
CONT_ASSIGN	1976	1	1	100.00
CONT_ASSIGN	1992	1	1	100.00
CONT_ASSIGN	2008	1	1	100.00
CONT_ASSIGN	2024	1	1	100.00
CONT_ASSIGN	2040	1	1	100.00
CONT_ASSIGN	2056	1	1	100.00
CONT_ASSIGN	2072	1	1	100.00
CONT_ASSIGN	2088	1	1	100.00
CONT_ASSIGN	2094	1	1	100.00
CONT_ASSIGN	2108	1	1	100.00
CONT_ASSIGN	2176	1	1	100.00
CONT_ASSIGN	3049	1	1	100.00
CONT_ASSIGN	3089	1	1	100.00
CONT_ASSIGN	7429	1	1	100.00
CONT_ASSIGN	7444	1	1	100.00
CONT_ASSIGN	7460	1	1	100.00
CONT_ASSIGN	7466	1	1	100.00
CONT_ASSIGN	7481	1	1	100.00
CONT_ASSIGN	7497	1	1	100.00
CONT_ASSIGN	8049	1	1	100.00
CONT_ASSIGN	8064	1	1	100.00
CONT_ASSIGN	8080	1	1	100.00
CONT_ASSIGN	8085	1	0	0.00
CONT_ASSIGN	8206	1	1	100.00
CONT_ASSIGN	8234	1	1	100.00
CONT_ASSIGN	8262	1	1	100.00
ALWAYS	8268	40	40	100.00
CONT_ASSIGN	8310	1	1	100.00
ALWAYS	8314	1	1	100.00
CONT_ASSIGN	8357	1	1	100.00
CONT_ASSIGN	8359	1	1	100.00
CONT_ASSIGN	8361	1	1	100.00
CONT_ASSIGN	8363	1	1	100.00
CONT_ASSIGN	8365	1	1	100.00
CONT_ASSIGN	8367	1	1	100.00
CONT_ASSIGN	8369	1	1	100.00
CONT_ASSIGN	8371	1	1	100.00
CONT_ASSIGN	8373	1	1	100.00
CONT_ASSIGN	8375	1	1	100.00
CONT_ASSIGN	8377	1	1	100.00
CONT_ASSIGN	8379	1	1	100.00
CONT_ASSIGN	8381	1	1	100.00
CONT_ASSIGN	8383	1	1	100.00
CONT_ASSIGN	8384	1	1	100.00
CONT_ASSIGN	8386	1	1	100.00
CONT_ASSIGN	8388	1	1	100.00
CONT_ASSIGN	8390	1	1	100.00
CONT_ASSIGN	8392	1	1	100.00
CONT_ASSIGN	8394	1	1	100.00
CONT_ASSIGN	8396	1	1	100.00
CONT_ASSIGN	8398	1	1	100.00
CONT_ASSIGN	8400	1	1	100.00
CONT_ASSIGN	8402	1	1	100.00
CONT_ASSIGN	8404	1	1	100.00
CONT_ASSIGN	8406	1	1	100.00
CONT_ASSIGN	8408	1	1	100.00
CONT_ASSIGN	8410	1	1	100.00
CONT_ASSIGN	8412	1	1	100.00
CONT_ASSIGN	8414	1	1	100.00
CONT_ASSIGN	8416	1	1	100.00
CONT_ASSIGN	8418	1	1	100.00
CONT_ASSIGN	8420	1	1	100.00
CONT_ASSIGN	8421	1	1	100.00
CONT_ASSIGN	8423	1	1	100.00
CONT_ASSIGN	8425	1	1	100.00
CONT_ASSIGN	8427	1	1	100.00
CONT_ASSIGN	8429	1	1	100.00
CONT_ASSIGN	8431	1	1	100.00
CONT_ASSIGN	8433	1	1	100.00
CONT_ASSIGN	8435	1	1	100.00
CONT_ASSIGN	8437	1	1	100.00
CONT_ASSIGN	8439	1	1	100.00
CONT_ASSIGN	8441	1	1	100.00
CONT_ASSIGN	8443	1	1	100.00
CONT_ASSIGN	8445	1	1	100.00
CONT_ASSIGN	8447	1	1	100.00
CONT_ASSIGN	8449	1	1	100.00
CONT_ASSIGN	8451	1	1	100.00
CONT_ASSIGN	8453	1	1	100.00
CONT_ASSIGN	8455	1	1	100.00
CONT_ASSIGN	8457	1	1	100.00
CONT_ASSIGN	8458	1	1	100.00
CONT_ASSIGN	8460	1	1	100.00
CONT_ASSIGN	8461	1	1	100.00
CONT_ASSIGN	8463	1	1	100.00
CONT_ASSIGN	8465	1	1	100.00
CONT_ASSIGN	8467	1	1	100.00
CONT_ASSIGN	8468	1	1	100.00
CONT_ASSIGN	8470	1	1	100.00
CONT_ASSIGN	8472	1	1	100.00
CONT_ASSIGN	8474	1	1	100.00
CONT_ASSIGN	8476	1	1	100.00
CONT_ASSIGN	8478	1	1	100.00
CONT_ASSIGN	8480	1	1	100.00
CONT_ASSIGN	8482	1	1	100.00
CONT_ASSIGN	8484	1	1	100.00
CONT_ASSIGN	8486	1	1	100.00
CONT_ASSIGN	8488	1	1	100.00
CONT_ASSIGN	8490	1	1	100.00
CONT_ASSIGN	8492	1	1	100.00
CONT_ASSIGN	8493	1	1	100.00
CONT_ASSIGN	8495	1	1	100.00
CONT_ASSIGN	8497	1	1	100.00
CONT_ASSIGN	8499	1	1	100.00
CONT_ASSIGN	8501	1	1	100.00
CONT_ASSIGN	8503	1	1	100.00
CONT_ASSIGN	8505	1	1	100.00
CONT_ASSIGN	8507	1	1	100.00
CONT_ASSIGN	8509	1	1	100.00
CONT_ASSIGN	8511	1	1	100.00
CONT_ASSIGN	8513	1	1	100.00
CONT_ASSIGN	8515	1	1	100.00
CONT_ASSIGN	8517	1	1	100.00
CONT_ASSIGN	8518	1	1	100.00
CONT_ASSIGN	8519	1	1	100.00
CONT_ASSIGN	8521	1	1	100.00
CONT_ASSIGN	8522	1	1	100.00
CONT_ASSIGN	8524	1	1	100.00
CONT_ASSIGN	8525	1	1	100.00
CONT_ASSIGN	8526	1	1	100.00
CONT_ASSIGN	8528	1	1	100.00
CONT_ASSIGN	8530	1	1	100.00
CONT_ASSIGN	8532	1	1	100.00
CONT_ASSIGN	8534	1	1	100.00
CONT_ASSIGN	8536	1	1	100.00
CONT_ASSIGN	8538	1	1	100.00
CONT_ASSIGN	8540	1	1	100.00
CONT_ASSIGN	8542	1	1	100.00
CONT_ASSIGN	8544	1	1	100.00
CONT_ASSIGN	8546	1	1	100.00
CONT_ASSIGN	8548	1	1	100.00
CONT_ASSIGN	8550	1	1	100.00
CONT_ASSIGN	8551	1	1	100.00
CONT_ASSIGN	8553	1	1	100.00
CONT_ASSIGN	8555	1	1	100.00
CONT_ASSIGN	8557	1	1	100.00
CONT_ASSIGN	8559	1	1	100.00
CONT_ASSIGN	8561	1	1	100.00
CONT_ASSIGN	8563	1	1	100.00
CONT_ASSIGN	8565	1	1	100.00
CONT_ASSIGN	8567	1	1	100.00
CONT_ASSIGN	8569	1	1	100.00
CONT_ASSIGN	8571	1	1	100.00
CONT_ASSIGN	8573	1	1	100.00
CONT_ASSIGN	8575	1	1	100.00
CONT_ASSIGN	8576	1	1	100.00
CONT_ASSIGN	8578	1	1	100.00
CONT_ASSIGN	8580	1	1	100.00
CONT_ASSIGN	8582	1	1	100.00
CONT_ASSIGN	8584	1	1	100.00
CONT_ASSIGN	8586	1	1	100.00
CONT_ASSIGN	8588	1	1	100.00
CONT_ASSIGN	8590	1	1	100.00
CONT_ASSIGN	8592	1	1	100.00
CONT_ASSIGN	8594	1	1	100.00
CONT_ASSIGN	8596	1	1	100.00
CONT_ASSIGN	8598	1	1	100.00
CONT_ASSIGN	8600	1	1	100.00
CONT_ASSIGN	8601	1	1	100.00
CONT_ASSIGN	8603	1	1	100.00
CONT_ASSIGN	8605	1	1	100.00
CONT_ASSIGN	8607	1	1	100.00
CONT_ASSIGN	8609	1	1	100.00
CONT_ASSIGN	8611	1	1	100.00
CONT_ASSIGN	8613	1	1	100.00
CONT_ASSIGN	8615	1	1	100.00
CONT_ASSIGN	8617	1	1	100.00
CONT_ASSIGN	8619	1	1	100.00
CONT_ASSIGN	8621	1	1	100.00
CONT_ASSIGN	8623	1	1	100.00
CONT_ASSIGN	8625	1	1	100.00
CONT_ASSIGN	8626	1	1	100.00
CONT_ASSIGN	8628	1	1	100.00
CONT_ASSIGN	8630	1	1	100.00
CONT_ASSIGN	8632	1	1	100.00
CONT_ASSIGN	8634	1	1	100.00
CONT_ASSIGN	8636	1	1	100.00
CONT_ASSIGN	8638	1	1	100.00
CONT_ASSIGN	8640	1	1	100.00
CONT_ASSIGN	8642	1	1	100.00
CONT_ASSIGN	8644	1	1	100.00
CONT_ASSIGN	8646	1	1	100.00
CONT_ASSIGN	8648	1	1	100.00
CONT_ASSIGN	8650	1	1	100.00
CONT_ASSIGN	8651	1	1	100.00
CONT_ASSIGN	8653	1	1	100.00
CONT_ASSIGN	8655	1	1	100.00
CONT_ASSIGN	8657	1	1	100.00
CONT_ASSIGN	8659	1	1	100.00
CONT_ASSIGN	8661	1	1	100.00
CONT_ASSIGN	8663	1	1	100.00
CONT_ASSIGN	8665	1	1	100.00
CONT_ASSIGN	8667	1	1	100.00
CONT_ASSIGN	8669	1	1	100.00
CONT_ASSIGN	8671	1	1	100.00
CONT_ASSIGN	8673	1	1	100.00
CONT_ASSIGN	8675	1	1	100.00
CONT_ASSIGN	8676	1	1	100.00
CONT_ASSIGN	8678	1	1	100.00
CONT_ASSIGN	8680	1	1	100.00
CONT_ASSIGN	8682	1	1	100.00
CONT_ASSIGN	8684	1	1	100.00
CONT_ASSIGN	8686	1	1	100.00
CONT_ASSIGN	8687	1	1	100.00
CONT_ASSIGN	8689	1	1	100.00
CONT_ASSIGN	8691	1	1	100.00
CONT_ASSIGN	8693	1	1	100.00
CONT_ASSIGN	8695	1	1	100.00
CONT_ASSIGN	8697	1	1	100.00
CONT_ASSIGN	8698	1	1	100.00
CONT_ASSIGN	8700	1	1	100.00
CONT_ASSIGN	8702	1	1	100.00
CONT_ASSIGN	8704	1	1	100.00
CONT_ASSIGN	8706	1	1	100.00
CONT_ASSIGN	8708	1	1	100.00
CONT_ASSIGN	8709	1	1	100.00
CONT_ASSIGN	8711	1	1	100.00
CONT_ASSIGN	8713	1	1	100.00
CONT_ASSIGN	8715	1	1	100.00
CONT_ASSIGN	8717	1	1	100.00
CONT_ASSIGN	8719	1	1	100.00
CONT_ASSIGN	8720	1	1	100.00
CONT_ASSIGN	8722	1	1	100.00
CONT_ASSIGN	8724	1	1	100.00
CONT_ASSIGN	8726	1	1	100.00
CONT_ASSIGN	8728	1	1	100.00
CONT_ASSIGN	8730	1	1	100.00
CONT_ASSIGN	8731	1	1	100.00
CONT_ASSIGN	8733	1	1	100.00
CONT_ASSIGN	8735	1	1	100.00
CONT_ASSIGN	8737	1	1	100.00
CONT_ASSIGN	8739	1	1	100.00
CONT_ASSIGN	8741	1	1	100.00
CONT_ASSIGN	8742	1	1	100.00
CONT_ASSIGN	8744	1	1	100.00
CONT_ASSIGN	8746	1	1	100.00
CONT_ASSIGN	8748	1	1	100.00
CONT_ASSIGN	8750	1	1	100.00
CONT_ASSIGN	8752	1	1	100.00
CONT_ASSIGN	8753	1	1	100.00
CONT_ASSIGN	8755	1	1	100.00
CONT_ASSIGN	8757	1	1	100.00
CONT_ASSIGN	8759	1	1	100.00
CONT_ASSIGN	8761	1	1	100.00
CONT_ASSIGN	8763	1	1	100.00
CONT_ASSIGN	8764	1	1	100.00
CONT_ASSIGN	8766	1	1	100.00
CONT_ASSIGN	8768	1	1	100.00
CONT_ASSIGN	8770	1	1	100.00
CONT_ASSIGN	8772	1	1	100.00
CONT_ASSIGN	8774	1	1	100.00
CONT_ASSIGN	8775	1	1	100.00
CONT_ASSIGN	8777	1	1	100.00
CONT_ASSIGN	8779	1	1	100.00
CONT_ASSIGN	8781	1	1	100.00
CONT_ASSIGN	8783	1	1	100.00
CONT_ASSIGN	8785	1	1	100.00
CONT_ASSIGN	8786	1	1	100.00
CONT_ASSIGN	8788	1	1	100.00
CONT_ASSIGN	8790	1	1	100.00
CONT_ASSIGN	8792	1	1	100.00
CONT_ASSIGN	8794	1	1	100.00
CONT_ASSIGN	8796	1	1	100.00
CONT_ASSIGN	8797	1	1	100.00
CONT_ASSIGN	8799	1	1	100.00
CONT_ASSIGN	8801	1	1	100.00
CONT_ASSIGN	8803	1	1	100.00
CONT_ASSIGN	8805	1	1	100.00
CONT_ASSIGN	8807	1	1	100.00
CONT_ASSIGN	8808	1	1	100.00
CONT_ASSIGN	8810	1	1	100.00
CONT_ASSIGN	8812	1	1	100.00
CONT_ASSIGN	8814	1	1	100.00
CONT_ASSIGN	8816	1	1	100.00
CONT_ASSIGN	8818	1	1	100.00
CONT_ASSIGN	8820	1	1	100.00
CONT_ASSIGN	8822	1	1	100.00
CONT_ASSIGN	8824	1	1	100.00
CONT_ASSIGN	8826	1	1	100.00
CONT_ASSIGN	8828	1	1	100.00
CONT_ASSIGN	8830	1	1	100.00
CONT_ASSIGN	8832	1	1	100.00
CONT_ASSIGN	8833	1	1	100.00
CONT_ASSIGN	8835	1	1	100.00
CONT_ASSIGN	8837	1	1	100.00
CONT_ASSIGN	8839	1	1	100.00
CONT_ASSIGN	8841	1	1	100.00
CONT_ASSIGN	8843	1	1	100.00
CONT_ASSIGN	8845	1	1	100.00
CONT_ASSIGN	8847	1	1	100.00
CONT_ASSIGN	8849	1	1	100.00
CONT_ASSIGN	8851	1	1	100.00
CONT_ASSIGN	8853	1	1	100.00
CONT_ASSIGN	8855	1	1	100.00
CONT_ASSIGN	8857	1	1	100.00
CONT_ASSIGN	8858	1	1	100.00
CONT_ASSIGN	8859	1	1	100.00
CONT_ASSIGN	8861	1	1	100.00
CONT_ASSIGN	8863	1	1	100.00
CONT_ASSIGN	8864	1	1	100.00
CONT_ASSIGN	8865	1	1	100.00
CONT_ASSIGN	8867	1	1	100.00
CONT_ASSIGN	8869	1	1	100.00
CONT_ASSIGN	8870	1	1	100.00
CONT_ASSIGN	8871	1	1	100.00
CONT_ASSIGN	8873	1	1	100.00
CONT_ASSIGN	8875	1	1	100.00
CONT_ASSIGN	8877	1	1	100.00
CONT_ASSIGN	8879	1	1	100.00
CONT_ASSIGN	8881	1	1	100.00
CONT_ASSIGN	8883	1	1	100.00
CONT_ASSIGN	8885	1	1	100.00
CONT_ASSIGN	8887	1	1	100.00
CONT_ASSIGN	8889	1	1	100.00
CONT_ASSIGN	8890	1	1	100.00
CONT_ASSIGN	8892	1	1	100.00
CONT_ASSIGN	8894	1	1	100.00
CONT_ASSIGN	8896	1	1	100.00
CONT_ASSIGN	8898	1	1	100.00
CONT_ASSIGN	8900	1	1	100.00
CONT_ASSIGN	8902	1	1	100.00
CONT_ASSIGN	8903	1	1	100.00
CONT_ASSIGN	8906	1	1	100.00
CONT_ASSIGN	8908	1	1	100.00
CONT_ASSIGN	8910	1	1	100.00
CONT_ASSIGN	8912	1	1	100.00
ALWAYS	8916	40	40	100.00
ALWAYS	8960	289	289	100.00
CONT_ASSIGN	9376	1	1	100.00
ALWAYS	9378	4	4	100.00
CONT_ASSIGN	9399	1	1	100.00
CONT_ASSIGN	9400	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	1	1
76	1	1
77	1	1
78	1	1
			MISSING_ELSE
84	1	1
102	1	1
103	1	1
105	1	1
106	1	1
132	1	1
138	1	1
139	0	1
			MISSING_ELSE
169	1	1
170	1	1
745	0	1
772	1	1
786	1	1
787	1	1
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
793	1	1
1801	1	1
1816	1	1
1832	1	1
1848	1	1
1864	1	1
1880	1	1
1896	1	1
1912	1	1
1928	1	1
1944	1	1
1960	1	1
1976	1	1
1992	1	1
2008	1	1
2024	1	1
2040	1	1
2056	1	1
2072	1	1
2088	1	1
2094	1	1
2108	1	1
2176	1	1
3049	1	1
3089	1	1
7429	1	1
7444	1	1
7460	1	1
7466	1	1
7481	1	1
7497	1	1
8049	1	1
8064	1	1
8080	1	1
8085	0	1
8206	1	1
8234	1	1
8262	1	1
8268	1	1
8269	1	1
8270	1	1
8271	1	1
8272	1	1
8273	1	1
8274	1	1
8275	1	1
8276	1	1
8277	1	1
8278	1	1
8279	1	1
8280	1	1
8281	1	1
8282	1	1
8283	1	1
8284	1	1
8285	1	1
8286	1	1
8287	1	1
8288	1	1
8289	1	1
8290	1	1
8291	1	1
8292	1	1
8293	1	1
8294	1	1
8295	1	1
8296	1	1
8297	1	1
8298	1	1
8299	1	1
8300	1	1
8301	1	1
8302	1	1
8303	1	1
8304	1	1
8305	1	1
8306	1	1
8307	1	1
8310	1	1
8314	1	1
8357	1	1
8359	1	1
8361	1	1
8363	1	1
8365	1	1
8367	1	1
8369	1	1
8371	1	1
8373	1	1
8375	1	1
8377	1	1
8379	1	1
8381	1	1
8383	1	1
8384	1	1
8386	1	1
8388	1	1
8390	1	1
8392	1	1
8394	1	1
8396	1	1
8398	1	1
8400	1	1
8402	1	1
8404	1	1
8406	1	1
8408	1	1
8410	1	1
8412	1	1
8414	1	1
8416	1	1
8418	1	1
8420	1	1
8421	1	1
8423	1	1
8425	1	1
8427	1	1
8429	1	1
8431	1	1
8433	1	1
8435	1	1
8437	1	1
8439	1	1
8441	1	1
8443	1	1
8445	1	1
8447	1	1
8449	1	1
8451	1	1
8453	1	1
8455	1	1
8457	1	1
8458	1	1
8460	1	1
8461	1	1
8463	1	1
8465	1	1
8467	1	1
8468	1	1
8470	1	1
8472	1	1
8474	1	1
8476	1	1
8478	1	1
8480	1	1
8482	1	1
8484	1	1
8486	1	1
8488	1	1
8490	1	1
8492	1	1
8493	1	1
8495	1	1
8497	1	1
8499	1	1
8501	1	1
8503	1	1
8505	1	1
8507	1	1
8509	1	1
8511	1	1
8513	1	1
8515	1	1
8517	1	1
8518	1	1
8519	1	1
8521	1	1
8522	1	1
8524	1	1
8525	1	1
8526	1	1
8528	1	1
8530	1	1
8532	1	1
8534	1	1
8536	1	1
8538	1	1
8540	1	1
8542	1	1
8544	1	1
8546	1	1
8548	1	1
8550	1	1
8551	1	1
8553	1	1
8555	1	1
8557	1	1
8559	1	1
8561	1	1
8563	1	1
8565	1	1
8567	1	1
8569	1	1
8571	1	1
8573	1	1
8575	1	1
8576	1	1
8578	1	1
8580	1	1
8582	1	1
8584	1	1
8586	1	1
8588	1	1
8590	1	1
8592	1	1
8594	1	1
8596	1	1
8598	1	1
8600	1	1
8601	1	1
8603	1	1
8605	1	1
8607	1	1
8609	1	1
8611	1	1
8613	1	1
8615	1	1
8617	1	1
8619	1	1
8621	1	1
8623	1	1
8625	1	1
8626	1	1
8628	1	1
8630	1	1
8632	1	1
8634	1	1
8636	1	1
8638	1	1
8640	1	1
8642	1	1
8644	1	1
8646	1	1
8648	1	1
8650	1	1
8651	1	1
8653	1	1
8655	1	1
8657	1	1
8659	1	1
8661	1	1
8663	1	1
8665	1	1
8667	1	1
8669	1	1
8671	1	1
8673	1	1
8675	1	1
8676	1	1
8678	1	1
8680	1	1
8682	1	1
8684	1	1
8686	1	1
8687	1	1
8689	1	1
8691	1	1
8693	1	1
8695	1	1
8697	1	1
8698	1	1
8700	1	1
8702	1	1
8704	1	1
8706	1	1
8708	1	1
8709	1	1
8711	1	1
8713	1	1
8715	1	1
8717	1	1
8719	1	1
8720	1	1
8722	1	1
8724	1	1
8726	1	1
8728	1	1
8730	1	1
8731	1	1
8733	1	1
8735	1	1
8737	1	1
8739	1	1
8741	1	1
8742	1	1
8744	1	1
8746	1	1
8748	1	1
8750	1	1
8752	1	1
8753	1	1
8755	1	1
8757	1	1
8759	1	1
8761	1	1
8763	1	1
8764	1	1
8766	1	1
8768	1	1
8770	1	1
8772	1	1
8774	1	1
8775	1	1
8777	1	1
8779	1	1
8781	1	1
8783	1	1
8785	1	1
8786	1	1
8788	1	1
8790	1	1
8792	1	1
8794	1	1
8796	1	1
8797	1	1
8799	1	1
8801	1	1
8803	1	1
8805	1	1
8807	1	1
8808	1	1
8810	1	1
8812	1	1
8814	1	1
8816	1	1
8818	1	1
8820	1	1
8822	1	1
8824	1	1
8826	1	1
8828	1	1
8830	1	1
8832	1	1
8833	1	1
8835	1	1
8837	1	1
8839	1	1
8841	1	1
8843	1	1
8845	1	1
8847	1	1
8849	1	1
8851	1	1
8853	1	1
8855	1	1
8857	1	1
8858	1	1
8859	1	1
8861	1	1
8863	1	1
8864	1	1
8865	1	1
8867	1	1
8869	1	1
8870	1	1
8871	1	1
8873	1	1
8875	1	1
8877	1	1
8879	1	1
8881	1	1
8883	1	1
8885	1	1
8887	1	1
8889	1	1
8890	1	1
8892	1	1
8894	1	1
8896	1	1
8898	1	1
8900	1	1
8902	1	1
8903	1	1
8906	1	1
8908	1	1
8910	1	1
8912	1	1
8916	1	1
8917	1	1
8918	1	1
8919	1	1
8920	1	1
8921	1	1
8922	1	1
8923	1	1
8924	1	1
8925	1	1
8926	1	1
8927	1	1
8928	1	1
8929	1	1
8930	1	1
8931	1	1
8932	1	1
8933	1	1
8934	1	1
8935	1	1
8936	1	1
8937	1	1
8938	1	1
8939	1	1
8940	1	1
8941	1	1
8942	1	1
8943	1	1
8944	1	1
8945	1	1
8946	1	1
8947	1	1
8948	1	1
8949	1	1
8950	1	1
8951	1	1
8952	1	1
8953	1	1
8954	1	1
8955	1	1
8960	1	1
8961	1	1
8963	1	1
8964	1	1
8965	1	1
8966	1	1
8967	1	1
8968	1	1
8969	1	1
8970	1	1
8971	1	1
8972	1	1
8973	1	1
8974	1	1
8975	1	1
8976	1	1
8977	1	1
8978	1	1
8979	1	1
8980	1	1
8984	1	1
8985	1	1
8986	1	1
8987	1	1
8988	1	1
8989	1	1
8990	1	1
8991	1	1
8992	1	1
8993	1	1
8994	1	1
8995	1	1
8996	1	1
8997	1	1
8998	1	1
8999	1	1
9000	1	1
9001	1	1
9005	1	1
9006	1	1
9007	1	1
9008	1	1
9009	1	1
9010	1	1
9011	1	1
9012	1	1
9013	1	1
9014	1	1
9015	1	1
9016	1	1
9017	1	1
9018	1	1
9019	1	1
9020	1	1
9021	1	1
9022	1	1
9026	1	1
9030	1	1
9031	1	1
9032	1	1
9036	1	1
9037	1	1
9038	1	1
9039	1	1
9040	1	1
9041	1	1
9042	1	1
9043	1	1
9044	1	1
9045	1	1
9046	1	1
9047	1	1
9051	1	1
9052	1	1
9053	1	1
9054	1	1
9055	1	1
9056	1	1
9057	1	1
9058	1	1
9059	1	1
9060	1	1
9061	1	1
9062	1	1
9066	1	1
9067	1	1
9068	1	1
9069	1	1
9070	1	1
9071	1	1
9072	1	1
9073	1	1
9074	1	1
9075	1	1
9079	1	1
9083	1	1
9087	1	1
9088	1	1
9089	1	1
9090	1	1
9094	1	1
9095	1	1
9096	1	1
9097	1	1
9098	1	1
9099	1	1
9100	1	1
9101	1	1
9102	1	1
9103	1	1
9104	1	1
9105	1	1
9109	1	1
9110	1	1
9111	1	1
9112	1	1
9113	1	1
9114	1	1
9115	1	1
9116	1	1
9117	1	1
9118	1	1
9119	1	1
9120	1	1
9124	1	1
9125	1	1
9126	1	1
9127	1	1
9128	1	1
9129	1	1
9130	1	1
9131	1	1
9132	1	1
9133	1	1
9134	1	1
9135	1	1
9139	1	1
9140	1	1
9141	1	1
9142	1	1
9143	1	1
9144	1	1
9145	1	1
9146	1	1
9147	1	1
9148	1	1
9149	1	1
9150	1	1
9154	1	1
9155	1	1
9156	1	1
9157	1	1
9158	1	1
9159	1	1
9160	1	1
9161	1	1
9162	1	1
9163	1	1
9164	1	1
9165	1	1
9169	1	1
9170	1	1
9171	1	1
9172	1	1
9173	1	1
9174	1	1
9175	1	1
9176	1	1
9177	1	1
9178	1	1
9179	1	1
9180	1	1
9184	1	1
9185	1	1
9186	1	1
9187	1	1
9188	1	1
9192	1	1
9193	1	1
9194	1	1
9195	1	1
9196	1	1
9200	1	1
9201	1	1
9202	1	1
9203	1	1
9204	1	1
9208	1	1
9209	1	1
9210	1	1
9211	1	1
9212	1	1
9216	1	1
9217	1	1
9218	1	1
9219	1	1
9220	1	1
9224	1	1
9225	1	1
9226	1	1
9227	1	1
9228	1	1
9232	1	1
9233	1	1
9234	1	1
9235	1	1
9236	1	1
9240	1	1
9241	1	1
9242	1	1
9243	1	1
9244	1	1
9248	1	1
9249	1	1
9250	1	1
9251	1	1
9252	1	1
9256	1	1
9257	1	1
9258	1	1
9259	1	1
9260	1	1
9264	1	1
9265	1	1
9266	1	1
9267	1	1
9268	1	1
9272	1	1
9273	1	1
9274	1	1
9275	1	1
9276	1	1
9280	1	1
9281	1	1
9282	1	1
9283	1	1
9284	1	1
9285	1	1
9286	1	1
9287	1	1
9288	1	1
9289	1	1
9290	1	1
9291	1	1
9295	1	1
9296	1	1
9297	1	1
9298	1	1
9299	1	1
9300	1	1
9301	1	1
9302	1	1
9303	1	1
9304	1	1
9305	1	1
9306	1	1
9310	1	1
9311	1	1
9315	1	1
9316	1	1
9320	1	1
9321	1	1
9322	1	1
9323	1	1
9324	1	1
9325	1	1
9326	1	1
9327	1	1
9328	1	1
9332	1	1
9333	1	1
9334	1	1
9335	1	1
9336	1	1
9337	1	1
9338	1	1
9339	1	1
9340	1	1
9344	1	1
9345	1	1
9346	1	1
9347	1	1
9348	1	1
9349	1	1
9353	1	1
9356	1	1
9359	1	1
9360	1	1
9361	1	1
9376	1	1
9378	1	1
9379	1	1
9381	1	1
9384	1	1
9399	1	1
9400	1	1

---

Cond Coverage for Module : usbdev_reg_top

	Total	Covered	Percent
Conditions	421	413	98.10
Logical	421	413	98.10
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T46,T47,T48
1	1	Covered	T1,T2,T3

 LINE       77
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T49,T50,T51
1	0	Not Covered

 LINE       84
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T49,T50,T51
0	1	0	Not Covered
1	0	0	Covered	T49,T50,T51

 LINE       132
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 1'b0 : 1'b1)
             ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T6

 LINE       170
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T46,T47,T48
1	0	0	Covered	T46,T47,T48

 LINE       8269
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_STATE_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       8270
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_ENABLE_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       8271
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_TEST_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T13,T203

 LINE       8272
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T204,T205,T206

 LINE       8273
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_USBCTRL_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       8274
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_EP_OUT_ENABLE_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       8275
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_EP_IN_ENABLE_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       8276
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_USBSTAT_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T10,T45

 LINE       8277
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_AVOUTBUFFER_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       8278
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_AVSETUPBUFFER_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T10

 LINE       8279
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXFIFO_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       8280
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXENABLE_SETUP_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T11

 LINE       8281
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXENABLE_OUT_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       8282
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_SET_NAK_OUT_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T13,T17

 LINE       8283
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_SENT_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       8284
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_STALL_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T20,T21

 LINE       8285
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_STALL_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T23

 LINE       8286
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_0_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T6,T109

 LINE       8287
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_1_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T77,T157

 LINE       8288
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_2_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T23,T119

 LINE       8289
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_3_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T9,T14

 LINE       8290
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_4_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T116,T117

 LINE       8291
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_5_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T119,T37

 LINE       8292
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_6_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T172,T122,T123

 LINE       8293
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_7_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T8,T28

 LINE       8294
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_8_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T125,T126,T127

 LINE       8295
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_9_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T24,T41

 LINE       8296
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_10_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T29

 LINE       8297
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_11_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T132,T133

 LINE       8298
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_ISO_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T207,T113,T208

 LINE       8299
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_ISO_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T38,T207

 LINE       8300
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_DATA_TOGGLE_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T33,T207

 LINE       8301
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_DATA_TOGGLE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T118,T131

 LINE       8302
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_PINS_SENSE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T25,T26

 LINE       8303
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_PINS_DRIVE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T26,T27

 LINE       8304
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_CONFIG_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T203,T207,T206

 LINE       8305
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_WAKE_CONTROL_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T159,T209

 LINE       8306
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_WAKE_EVENTS_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T203,T210

 LINE       8307
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_FIFO_CTRL_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T10,T45

 LINE       8310
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       8310
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       8314
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1 & (~reg_be))))) | (addr_hit[37] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T46,T47,T48

 LINE       8314
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0111 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0111 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0111 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b0111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b0111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b0111 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b1 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b0011 & (~reg_be))))) | 
     39  (addr_hit[38] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
39 (addr_hit[38] & ((|(4'...	Covered	T6,T203,T211
38 (addr_hit[37] & ((|(4'...	Covered	T6,T210,T206
37 (addr_hit[36] & ((|(4'...	Covered	T6,T159,T209
36 (addr_hit[35] & ((|(4'...	Covered	T203,T207,T206
35 (addr_hit[34] & ((|(4'...	Covered	T139,T206,T86
34 (addr_hit[33] & ((|(4'...	Covered	T6,T25,T26
33 (addr_hit[32] & ((|(4'...	Covered	T6,T118,T131
32 (addr_hit[31] & ((|(4'...	Covered	T6,T33,T207
31 (addr_hit[30] & ((|(4'...	Covered	T6,T207,T206
30 (addr_hit[29] & ((|(4'...	Covered	T207,T113,T208
29 (addr_hit[28] & ((|(4'...	Covered	T207,T105,T212
28 (addr_hit[27] & ((|(4'...	Covered	T6,T203,T213
27 (addr_hit[26] & ((|(4'...	Covered	T6,T41,T203
26 (addr_hit[25] & ((|(4'...	Covered	T207,T115,T206
25 (addr_hit[24] & ((|(4'...	Covered	T142,T207,T214
24 (addr_hit[23] & ((|(4'...	Covered	T203,T211,T206
23 (addr_hit[22] & ((|(4'...	Covered	T6,T37,T207
22 (addr_hit[21] & ((|(4'...	Covered	T6,T215,T203
21 (addr_hit[20] & ((|(4'...	Covered	T6,T37,T51
20 (addr_hit[19] & ((|(4'...	Covered	T119,T216,T217
19 (addr_hit[18] & ((|(4'...	Covered	T6,T64,T207
18 (addr_hit[17] & ((|(4'...	Covered	T6,T203,T218
17 (addr_hit[16] & ((|(4'...	Covered	T6,T142,T219
16 (addr_hit[15] & ((|(4'...	Covered	T6,T208,T216
15 (addr_hit[14] & ((|(4'...	Covered	T1,T3,T6
14 (addr_hit[13] & ((|(4'...	Covered	T6,T203,T206
13 (addr_hit[12] & ((|(4'...	Covered	T17,T18,T103
12 (addr_hit[11] & ((|(4'...	Covered	T13,T207,T206
11 (addr_hit[10] & ((|(4'...	Covered	T3,T5,T7
10 (addr_hit[9] & ((|(4'b...	Covered	T6,T220,T208
9 (addr_hit[8] & ((|(4'b...	Covered	T208,T206,T212
8 (addr_hit[7] & ((|(4'b...	Covered	T6,T10,T45
7 (addr_hit[6] & ((|(4'b...	Covered	T6,T116,T142
6 (addr_hit[5] & ((|(4'b...	Covered	T6,T203,T207
5 (addr_hit[4] & ((|(4'b...	Covered	T6,T208,T206
4 (addr_hit[3] & ((|(4'b...	Covered	T205,T221,T46
3 (addr_hit[2] & ((|(4'b...	Covered	T6,T203,T207
2 (addr_hit[1] & ((|(4'b...	Covered	T6,T203,T207
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T3,T5

 LINE       8314
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       8314
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T6,T203,T207

 LINE       8314
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T52,T57
1	1	Covered	T6,T203,T207

 LINE       8314
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T204,T206,T216
1	1	Covered	T205,T221,T46

 LINE       8314
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T208,T206

 LINE       8314
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
1	1	Covered	T6,T203,T207

 LINE       8314
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T116,T142

 LINE       8314
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T10,T45
1	1	Covered	T6,T10,T45

 LINE       8314
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
1	1	Covered	T208,T206,T212

 LINE       8314
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T3,T6,T10
1	1	Covered	T6,T220,T208

 LINE       8314
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T28
1	1	Covered	T3,T5,T7

 LINE       8314
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T3,T6,T11
1	1	Covered	T13,T207,T206

 LINE       8314
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
1	1	Covered	T17,T18,T103

 LINE       8314
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T13,T17,T18
1	1	Covered	T6,T203,T206

 LINE       8314
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       8314
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T20,T21,T22
1	1	Covered	T6,T208,T216

 LINE       8314
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T2,T23,T24
1	1	Covered	T6,T142,T219

 LINE       8314
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T109,T110
1	1	Covered	T6,T203,T218

 LINE       8314
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T157,T158
1	1	Covered	T6,T64,T207

 LINE       8314
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T23,T161
1	1	Covered	T119,T216,T217

 LINE       8314
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T14,T163
1	1	Covered	T6,T37,T51

 LINE       8314
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T116,T117,T118
1	1	Covered	T6,T215,T203

 LINE       8314
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T119,T120,T121
1	1	Covered	T6,T37,T207

 LINE       8314
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T172,T122,T123
1	1	Covered	T203,T211,T206

 LINE       8314
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T8,T28
1	1	Covered	T142,T207,T214

 LINE       8314
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T125,T126,T127
1	1	Covered	T207,T115,T206

 LINE       8314
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T178,T128
1	1	Covered	T6,T41,T203

 LINE       8314
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T29,T131
1	1	Covered	T6,T203,T213

 LINE       8314
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T132,T133
1	1	Covered	T207,T105,T212

 LINE       8314
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T216,T212,T222
1	1	Covered	T207,T113,T208

 LINE       8314
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T38,T223,T52
1	1	Covered	T6,T207,T206

 LINE       8314
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T52,T57
1	1	Covered	T6,T33,T207

 LINE       8314
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T52,T57
1	1	Covered	T6,T118,T131

 LINE       8314
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T57,T58
1	1	Covered	T6,T25,T26

 LINE       8314
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T25,T26,T27
1	1	Covered	T139,T206,T86

 LINE       8314
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T206,T216,T224
1	1	Covered	T203,T207,T206

 LINE       8314
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T6,T221,T222
1	1	Covered	T6,T159,T209

 LINE       8314
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T203,T207,T46
1	1	Covered	T6,T210,T206

 LINE       8314
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T6,T10,T45
1	1	Covered	T6,T203,T211

 LINE       8357
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T47,T48,T184
1	1	1	Covered	T1,T2,T3

 LINE       8384
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T6
1	1	0	Covered	T47,T48,T184
1	1	1	Covered	T1,T3,T8

 LINE       8421
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T13,T203
1	1	0	Covered	T47,T48,T184
1	1	1	Covered	T52,T59,T60

 LINE       8458
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T204,T205,T206
1	1	0	Covered	T47,T48,T184
1	1	1	Covered	T52,T57,T58

 LINE       8461
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T46,T47,T48
1	1	1	Covered	T1,T2,T3

 LINE       8468
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T47,T184,T185
1	1	1	Covered	T1,T3,T5

 LINE       8493
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T46,T47,T48
1	1	1	Covered	T1,T2,T3

 LINE       8518
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T10,T45
1	1	0	Not Covered
1	1	1	Covered	T6,T10,T45

 LINE       8519
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T46,T47,T184
1	1	1	Covered	T1,T3,T5

 LINE       8522
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T6,T10
1	1	0	Covered	T47,T48,T184
1	1	1	Covered	T3,T6,T10

 LINE       8525
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       8526
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T6,T11
1	1	0	Covered	T47,T48,T185
1	1	1	Covered	T3,T11,T12

 LINE       8551
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T225,T226,T227
1	1	1	Covered	T1,T3,T5

 LINE       8576
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T13,T17
1	1	0	Covered	T47,T48,T74
1	1	1	Covered	T13,T17,T18

 LINE       8601
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T6
1	1	0	Covered	T46,T47,T48
1	1	1	Covered	T1,T3,T8

 LINE       8626
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T20,T21
1	1	0	Covered	T46,T47,T55
1	1	1	Covered	T20,T21,T22

 LINE       8651
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T23
1	1	0	Covered	T46,T47,T48
1	1	1	Covered	T2,T23,T24

 LINE       8676
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T109
1	1	0	Covered	T47,T48,T184
1	1	1	Covered	T2,T109,T110

 LINE       8687
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T77,T157
1	1	0	Covered	T48,T184,T185
1	1	1	Covered	T77,T157,T158

 LINE       8698
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T13,T23
1	1	0	Covered	T47,T225,T227
1	1	1	Covered	T1,T23,T161

 LINE       8709
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T9,T14
1	1	0	Covered	T47,T48,T184
1	1	1	Covered	T9,T14,T163

 LINE       8720
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T116,T117
1	1	0	Covered	T47,T48,T184
1	1	1	Covered	T116,T117,T118

 LINE       8731
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T119,T37
1	1	0	Covered	T46,T47,T48
1	1	1	Covered	T119,T120,T121

 LINE       8742
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T172,T122,T123
1	1	0	Covered	T46,T47,T185
1	1	1	Covered	T172,T122,T123

 LINE       8753
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T8,T28
1	1	0	Covered	T46,T47,T48
1	1	1	Covered	T8,T28,T30

 LINE       8764
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T125,T126,T84
1	1	0	Covered	T46,T47,T48
1	1	1	Covered	T125,T126,T127

 LINE       8775
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T24,T41
1	1	0	Covered	T46,T47,T48
1	1	1	Covered	T24,T178,T128

 LINE       8786
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T6,T29
1	1	0	Covered	T47,T184,T186
1	1	1	Covered	T3,T29,T131

 LINE       8797
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T15,T132,T133
1	1	0	Covered	T46,T48,T184
1	1	1	Covered	T15,T132,T133

 LINE       8808
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T207,T113,T208
1	1	0	Covered	T47,T48,T184
1	1	1	Covered	T52,T57,T58

 LINE       8833
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T228,T38
1	1	0	Covered	T47,T48,T184
1	1	1	Covered	T52,T57,T58

 LINE       8858
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T33,T207
1	1	0	Not Covered
1	1	1	Covered	T52,T57,T58

 LINE       8859
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T33,T207
1	1	0	Covered	T48,T184,T185
1	1	1	Covered	T52,T53,T229

 LINE       8864
 EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T118,T230
1	1	0	Not Covered
1	1	1	Covered	T52,T57,T58

 LINE       8865
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T118,T230
1	1	0	Covered	T47,T48,T184
1	1	1	Covered	T52,T53,T229

 LINE       8870
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T25,T26
1	1	0	Not Covered
1	1	1	Covered	T25,T26,T27

 LINE       8871
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T25,T26,T27
1	1	0	Covered	T47,T48,T184
1	1	1	Covered	T25,T26,T27

 LINE       8890
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T203,T231,T207
1	1	0	Covered	T184,T185,T187
1	1	1	Covered	T52,T57,T58

 LINE       8903
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T159,T209
1	1	0	Covered	T46,T47,T48
1	1	1	Covered	T52,T57,T58

 LINE       8906
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T10,T45
1	1	0	Covered	T46,T47,T187
1	1	1	Covered	T6,T10,T45

 LINE       9376
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T57,T58

---

Branch Coverage for Module : usbdev_reg_top

	Line No.	Total	Covered	Percent
Branches		52	51	98.08
TERNARY	8310	2	2	100.00
IF	75	3	3	100.00
TERNARY	132	2	2	100.00
IF	138	2	1	50.00
CASE	8961	40	40	100.00
CASE	9379	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	8310	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	77	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T49,T50,T51
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	132	((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	if (intg_err)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	8961	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	9379	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	238672165	90816	0	0
reAfterRv	238672165	90816	0	0
rePulse	238672165	36046	0	0
wePulse	238672165	54770	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	238672165	90816	0	0
T1	402056	20	0	0
T2	401124	7	0	0
T3	406749	21	0	0
T4	402006	9	0	0
T5	401786	8	0	0
T6	10382	1305	0	0
T7	403669	8	0	0
T8	405671	20	0	0
T9	403801	20	0	0
T10	3078	1018	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	238672165	90816	0	0
T1	402056	20	0	0
T2	401124	7	0	0
T3	406749	21	0	0
T4	402006	9	0	0
T5	401786	8	0	0
T6	10382	1305	0	0
T7	403669	8	0	0
T8	405671	20	0	0
T9	403801	20	0	0
T10	3078	1018	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	238672165	36046	0	0
T1	402056	8	0	0
T2	401124	2	0	0
T3	406749	8	0	0
T4	402006	3	0	0
T5	401786	3	0	0
T6	10382	257	0	0
T7	403669	3	0	0
T8	405671	8	0	0
T9	403801	8	0	0
T10	3078	215	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	238672165	54770	0	0
T1	402056	12	0	0
T2	401124	5	0	0
T3	406749	13	0	0
T4	402006	6	0	0
T5	401786	5	0	0
T6	10382	1048	0	0
T7	403669	5	0	0
T8	405671	12	0	0
T9	403801	12	0	0
T10	3078	803	0	0