Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2258	1		T1	4		T2	4		T3	2
all_values[1]	2258	1		T1	4		T2	4		T3	2
all_values[2]	2258	1		T1	4		T2	4		T3	2
all_values[3]	2258	1		T1	4		T2	4		T3	2
all_values[4]	2258	1		T1	4		T2	4		T3	2
all_values[5]	2258	1		T1	4		T2	4		T3	2
all_values[6]	2258	1		T1	4		T2	4		T3	2
all_values[7]	2258	1		T1	4		T2	4		T3	2
all_values[8]	2258	1		T1	4		T2	4		T3	2
all_values[9]	2258	1		T1	4		T2	4		T3	2
all_values[10]	2258	1		T1	4		T2	4		T3	2
all_values[11]	2258	1		T1	4		T2	4		T3	2
all_values[12]	2258	1		T1	4		T2	4		T3	2
all_values[13]	2258	1		T1	4		T2	4		T3	2
all_values[14]	2258	1		T1	4		T2	4		T3	2
all_values[15]	2258	1		T1	4		T2	4		T3	2
all_values[16]	2258	1		T1	4		T2	4		T3	2
all_values[17]	2258	1		T1	4		T2	4		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	38529	1		T1	70		T2	72		T3	36
auto[1]	2115	1		T1	2		T5	2		T9	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	38064	1		T1	72		T2	72		T3	36
auto[1]	2580	1		T60	83		T61	72		T62	131

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1844	1		T1	2		T2	4		T3	2
all_values[0]	auto[0]	auto[1]	69	1		T60	4		T61	5		T62	4
all_values[0]	auto[1]	auto[0]	265	1		T1	2		T5	2		T11	3
all_values[0]	auto[1]	auto[1]	80	1		T60	1		T62	4		T64	1
all_values[1]	auto[0]	auto[0]	1823	1		T1	4		T2	4		T3	2
all_values[1]	auto[0]	auto[1]	58	1		T61	3		T62	1		T63	1
all_values[1]	auto[1]	auto[0]	291	1		T9	3		T19	3		T20	3
all_values[1]	auto[1]	auto[1]	86	1		T60	5		T62	6		T63	3
all_values[2]	auto[0]	auto[0]	2104	1		T1	4		T2	4		T3	2
all_values[2]	auto[0]	auto[1]	59	1		T61	1		T62	1		T63	4
all_values[2]	auto[1]	auto[0]	16	1		T64	3		T238	1		T239	2
all_values[2]	auto[1]	auto[1]	79	1		T60	5		T61	3		T62	6
all_values[3]	auto[0]	auto[0]	2097	1		T1	4		T2	4		T3	2
all_values[3]	auto[0]	auto[1]	84	1		T61	1		T62	7		T63	3
all_values[3]	auto[1]	auto[0]	19	1		T63	1		T240	1		T239	1
all_values[3]	auto[1]	auto[1]	58	1		T60	5		T61	4		T62	1
all_values[4]	auto[0]	auto[0]	2105	1		T1	4		T2	4		T3	2
all_values[4]	auto[0]	auto[1]	69	1		T61	3		T62	5		T63	3
all_values[4]	auto[1]	auto[0]	16	1		T60	1		T61	1		T238	4
all_values[4]	auto[1]	auto[1]	68	1		T60	3		T62	3		T63	2
all_values[5]	auto[0]	auto[0]	2097	1		T1	4		T2	4		T3	2
all_values[5]	auto[0]	auto[1]	69	1		T60	5		T61	4		T62	3
all_values[5]	auto[1]	auto[0]	10	1		T241	2		T242	1		T243	1
all_values[5]	auto[1]	auto[1]	82	1		T61	1		T62	5		T63	5
all_values[6]	auto[0]	auto[0]	2101	1		T1	4		T2	4		T3	2
all_values[6]	auto[0]	auto[1]	77	1		T60	4		T61	3		T62	3
all_values[6]	auto[1]	auto[0]	11	1		T61	1		T64	1		T238	1
all_values[6]	auto[1]	auto[1]	69	1		T60	1		T61	1		T62	5
all_values[7]	auto[0]	auto[0]	2102	1		T1	4		T2	4		T3	2
all_values[7]	auto[0]	auto[1]	71	1		T60	4		T61	3		T62	4
all_values[7]	auto[1]	auto[0]	19	1		T61	1		T63	1		T64	2
all_values[7]	auto[1]	auto[1]	66	1		T61	1		T62	3		T63	3
all_values[8]	auto[0]	auto[0]	2100	1		T1	4		T2	4		T3	2
all_values[8]	auto[0]	auto[1]	56	1		T60	1		T62	3		T63	5
all_values[8]	auto[1]	auto[0]	15	1		T61	1		T65	1		T66	1
all_values[8]	auto[1]	auto[1]	87	1		T60	4		T61	3		T62	5
all_values[9]	auto[0]	auto[0]	2100	1		T1	4		T2	4		T3	2
all_values[9]	auto[0]	auto[1]	78	1		T60	1		T61	1		T62	4
all_values[9]	auto[1]	auto[0]	18	1		T62	1		T64	1		T238	1
all_values[9]	auto[1]	auto[1]	62	1		T60	4		T61	4		T62	3
all_values[10]	auto[0]	auto[0]	2102	1		T1	4		T2	4		T3	2
all_values[10]	auto[0]	auto[1]	75	1		T62	6		T63	5		T66	5
all_values[10]	auto[1]	auto[0]	11	1		T65	1		T241	4		T244	1
all_values[10]	auto[1]	auto[1]	70	1		T60	3		T61	4		T62	2
all_values[11]	auto[0]	auto[0]	2094	1		T1	4		T2	4		T3	2
all_values[11]	auto[0]	auto[1]	76	1		T61	1		T62	4		T64	5
all_values[11]	auto[1]	auto[0]	14	1		T62	2		T63	4		T239	3
all_values[11]	auto[1]	auto[1]	74	1		T60	5		T61	3		T62	2
all_values[12]	auto[0]	auto[0]	2103	1		T1	4		T2	4		T3	2
all_values[12]	auto[0]	auto[1]	60	1		T60	4		T62	3		T63	1
all_values[12]	auto[1]	auto[0]	24	1		T61	4		T62	1		T66	1
all_values[12]	auto[1]	auto[1]	71	1		T60	1		T63	4		T64	1
all_values[13]	auto[0]	auto[0]	2097	1		T1	4		T2	4		T3	2
all_values[13]	auto[0]	auto[1]	63	1		T60	3		T62	2		T63	4
all_values[13]	auto[1]	auto[0]	10	1		T61	2		T62	1		T63	1
all_values[13]	auto[1]	auto[1]	88	1		T60	1		T61	3		T62	4
all_values[14]	auto[0]	auto[0]	2109	1		T1	4		T2	4		T3	2
all_values[14]	auto[0]	auto[1]	68	1		T60	1		T61	4		T62	4
all_values[14]	auto[1]	auto[0]	10	1		T240	2		T241	1		T242	1
all_values[14]	auto[1]	auto[1]	71	1		T60	3		T61	1		T62	4
all_values[15]	auto[0]	auto[0]	2093	1		T1	4		T2	4		T3	2
all_values[15]	auto[0]	auto[1]	77	1		T60	1		T61	4		T62	4
all_values[15]	auto[1]	auto[0]	7	1		T240	3		T245	1		T244	1
all_values[15]	auto[1]	auto[1]	81	1		T60	4		T61	1		T62	4
all_values[16]	auto[0]	auto[0]	2102	1		T1	4		T2	4		T3	2
all_values[16]	auto[0]	auto[1]	79	1		T60	4		T61	5		T62	6
all_values[16]	auto[1]	auto[0]	26	1		T63	1		T66	5		T240	2
all_values[16]	auto[1]	auto[1]	51	1		T60	1		T62	2		T63	1
all_values[17]	auto[0]	auto[0]	2099	1		T1	4		T2	4		T3	2
all_values[17]	auto[0]	auto[1]	69	1		T60	1		T61	4		T62	4
all_values[17]	auto[1]	auto[0]	10	1		T64	1		T66	1		T240	1
all_values[17]	auto[1]	auto[1]	80	1		T60	4		T61	1		T62	4