Design Module List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.26 94.88 82.91 97.17 46.88 85.00 98.75


Total modules in report: 53
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_sync_reqack 30.56 72.22 0.00 50.00 0.00
prim_reg_cdc_arb 37.90 49.67 62.79 39.13 0.00
prim_reg_cdc_arb 19.57 39.13 0.00
prim_reg_cdc_arb ( parameter DataWidth=11,ResetVal=0,DstWrReq=1 ) 45.79 66.00 25.58
prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 ) 66.67 33.33 100.00
usbdev_linkstate 65.92 75.00 62.32 33.33 58.93 100.00
usb_fs_nb_out_pe 78.85 87.30 75.81 50.00 81.13 100.00
usb_fs_nb_in_pe 80.84 87.61 81.18 58.33 77.08 100.00
prim_generic_clock_mux2 83.33 100.00 100.00 50.00
usb_fs_nb_pe 83.33 100.00 50.00 100.00
usb_fs_tx 85.86 95.11 84.48 58.82 90.91 100.00
tlul_adapter_sram 87.38 95.38 70.80 83.33 100.00
prim_intr_hw 88.26 95.00 68.06 90.00 100.00
prim_intr_hw 100.00 100.00
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" ) 86.11 100.00 58.33 100.00
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" ) 82.59 90.00 77.78 80.00
usbdev 89.25 96.75 68.07 93.93 87.50 100.00
prim_fifo_sync 90.01 100.00 70.33 89.72 100.00
prim_fifo_sync 100.00 100.00
prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 ) 100.00 100.00
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) 73.08 73.08
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) 100.00 100.00
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PTRV_W=3,gen_normal_fifo.PTR_WIDTH=4 ) 80.77 100.00 61.54
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PTRV_W=3,gen_normal_fifo.PTR_WIDTH=4 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) 90.00 90.00
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) 89.38 100.00 76.47 91.67
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 ) 69.23 69.23
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 ) 85.42 100.00 70.83
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PTRV_W=3,gen_normal_fifo.PTR_WIDTH=4 ) 87.50 87.50
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PTRV_W=3,gen_normal_fifo.PTR_WIDTH=4 ) 85.42 100.00 70.83
prim_reg_cdc 92.86 100.00 71.43 100.00 100.00
usb_fs_rx 93.25 98.92 87.56 93.26
prim_subreg_arb 94.44 83.33 100.00 100.00
prim_subreg_arb 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=7,SwAccess=0,Mubi=0 + DW=5,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 ) 50.00 50.00
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) 100.00 100.00 100.00
prim_subreg_arb ( parameter DW=5,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=7,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_generic_ram_1p 95.24 85.71 100.00 100.00
tlul_assert 95.24 100.00 85.71 100.00
usbdev_usbif 95.61 97.06 94.20 91.18 100.00
tlul_rsp_intg_gen 95.83 91.67 100.00
tlul_rsp_intg_gen 100.00 100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) 83.33 83.33
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) 100.00 100.00
prim_fifo_sync_cnt 96.48 92.96 100.00
prim_fifo_sync_cnt 100.00 100.00
prim_fifo_sync_cnt ( parameter Depth=1,Width=2,Secure=0 ) 88.89 88.89
prim_fifo_sync_cnt ( parameter Depth=4,Width=3,Secure=0 ) 95.00 95.00
prim_fifo_sync_cnt ( parameter Depth=8,Width=4,Secure=0 ) 95.00 95.00
tlul_socket_1n 97.67 98.21 97.73 94.74 100.00
tlul_adapter_reg 98.47 100.00 93.88 100.00 100.00
usbdev_reg_top 98.94 99.59 98.10 98.08 100.00
tlul_data_integ_dec 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_alert_sender 100.00 100.00
usb_fs_tx_mux 100.00 100.00 100.00 100.00
tlul_fifo_sync 100.00 100.00 100.00
prim_edge_detector 100.00 100.00 100.00
prim_onehot_check 100.00 100.00
prim_subreg 100.00 100.00 100.00 100.00
prim_subreg 100.00 100.00 100.00
prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=5,SwAccess=0,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=7,SwAccess=0,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_filter 100.00 100.00 100.00 100.00
prim_secded_inv_39_32_dec 100.00 100.00
prim_generic_buf 100.00 100.00
prim_pulse_sync 100.00 100.00 100.00 100.00 100.00
prim_subreg_ext 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
tlul_sram_byte 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_secded_inv_64_57_dec 100.00 100.00
prim_ram_1p_adv 100.00 100.00 100.00 100.00 100.00
usbdev_iomux 100.00 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
usbdev_csr_assert_fpv 100.00 100.00
tlul_data_integ_enc
prim_reg_we_check
prim_clock_mux2
prim_buf
prim_flop
prim_flop_2sync
tb
prim_ram_1p
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%