Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2258	1		T1	4		T2	4		T3	2
all_pins[1]	2258	1		T1	4		T2	4		T3	2
all_pins[2]	2258	1		T1	4		T2	4		T3	2
all_pins[3]	2258	1		T1	4		T2	4		T3	2
all_pins[4]	2258	1		T1	4		T2	4		T3	2
all_pins[5]	2258	1		T1	4		T2	4		T3	2
all_pins[6]	2258	1		T1	4		T2	4		T3	2
all_pins[7]	2258	1		T1	4		T2	4		T3	2
all_pins[8]	2258	1		T1	4		T2	4		T3	2
all_pins[9]	2258	1		T1	4		T2	4		T3	2
all_pins[10]	2258	1		T1	4		T2	4		T3	2
all_pins[11]	2258	1		T1	4		T2	4		T3	2
all_pins[12]	2258	1		T1	4		T2	4		T3	2
all_pins[13]	2258	1		T1	4		T2	4		T3	2
all_pins[14]	2258	1		T1	4		T2	4		T3	2
all_pins[15]	2258	1		T1	4		T2	4		T3	2
all_pins[16]	2258	1		T1	4		T2	4		T3	2
all_pins[17]	2258	1		T1	4		T2	4		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	39921	1		T1	72		T2	72		T3	36
values[0x1]	723	1		T9	1		T19	1		T20	1
transitions[0x0=>0x1]	563	1		T9	1		T19	1		T20	1
transitions[0x1=>0x0]	573	1		T9	1		T19	1		T20	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2230	1		T1	4		T2	4		T3	2
all_pins[0]	values[0x1]	28	1		T62	2		T64	1		T238	1
all_pins[0]	transitions[0x0=>0x1]	20	1		T62	1		T64	1		T65	1
all_pins[0]	transitions[0x1=>0x0]	120	1		T9	1		T19	1		T20	1
all_pins[1]	values[0x0]	2130	1		T1	4		T2	4		T3	2
all_pins[1]	values[0x1]	128	1		T9	1		T19	1		T20	1
all_pins[1]	transitions[0x0=>0x1]	116	1		T9	1		T19	1		T20	1
all_pins[1]	transitions[0x1=>0x0]	29	1		T61	2		T62	1		T63	1
all_pins[2]	values[0x0]	2217	1		T1	4		T2	4		T3	2
all_pins[2]	values[0x1]	41	1		T60	2		T61	2		T62	4
all_pins[2]	transitions[0x0=>0x1]	31	1		T62	4		T63	1		T65	2
all_pins[2]	transitions[0x1=>0x0]	24	1		T60	2		T62	1		T64	3
all_pins[3]	values[0x0]	2224	1		T1	4		T2	4		T3	2
all_pins[3]	values[0x1]	34	1		T60	4		T61	2		T62	1
all_pins[3]	transitions[0x0=>0x1]	28	1		T60	2		T61	2		T62	1
all_pins[3]	transitions[0x1=>0x0]	31	1		T62	2		T63	2		T241	2
all_pins[4]	values[0x0]	2221	1		T1	4		T2	4		T3	2
all_pins[4]	values[0x1]	37	1		T60	2		T62	2		T63	2
all_pins[4]	transitions[0x0=>0x1]	23	1		T60	2		T62	1		T63	1
all_pins[4]	transitions[0x1=>0x0]	33	1		T62	1		T63	2		T238	3
all_pins[5]	values[0x0]	2211	1		T1	4		T2	4		T3	2
all_pins[5]	values[0x1]	47	1		T62	2		T63	3		T238	3
all_pins[5]	transitions[0x0=>0x1]	33	1		T62	1		T63	1		T238	1
all_pins[5]	transitions[0x1=>0x0]	22	1		T60	1		T61	1		T62	1
all_pins[6]	values[0x0]	2222	1		T1	4		T2	4		T3	2
all_pins[6]	values[0x1]	36	1		T60	1		T61	1		T62	2
all_pins[6]	transitions[0x0=>0x1]	31	1		T60	1		T62	1		T63	2
all_pins[6]	transitions[0x1=>0x0]	27	1		T62	2		T64	1		T65	1
all_pins[7]	values[0x0]	2226	1		T1	4		T2	4		T3	2
all_pins[7]	values[0x1]	32	1		T61	1		T62	3		T64	1
all_pins[7]	transitions[0x0=>0x1]	27	1		T61	1		T62	2		T64	1
all_pins[7]	transitions[0x1=>0x0]	27	1		T60	1		T61	1		T64	1
all_pins[8]	values[0x0]	2226	1		T1	4		T2	4		T3	2
all_pins[8]	values[0x1]	32	1		T60	1		T61	1		T62	1
all_pins[8]	transitions[0x0=>0x1]	26	1		T60	1		T64	1		T238	2
all_pins[8]	transitions[0x1=>0x0]	29	1		T61	2		T62	2		T63	2
all_pins[9]	values[0x0]	2223	1		T1	4		T2	4		T3	2
all_pins[9]	values[0x1]	35	1		T61	3		T62	3		T63	2
all_pins[9]	transitions[0x0=>0x1]	27	1		T61	3		T62	1		T63	2
all_pins[9]	transitions[0x1=>0x0]	26	1		T64	4		T238	2		T240	1
all_pins[10]	values[0x0]	2224	1		T1	4		T2	4		T3	2
all_pins[10]	values[0x1]	34	1		T62	2		T64	4		T238	2
all_pins[10]	transitions[0x0=>0x1]	28	1		T62	1		T64	4		T238	2
all_pins[10]	transitions[0x1=>0x0]	19	1		T60	1		T62	1		T65	1
all_pins[11]	values[0x0]	2233	1		T1	4		T2	4		T3	2
all_pins[11]	values[0x1]	25	1		T60	1		T62	2		T65	1
all_pins[11]	transitions[0x0=>0x1]	18	1		T60	1		T62	2		T65	1
all_pins[11]	transitions[0x1=>0x0]	25	1		T60	1		T63	3		T240	2
all_pins[12]	values[0x0]	2226	1		T1	4		T2	4		T3	2
all_pins[12]	values[0x1]	32	1		T60	1		T63	3		T240	2
all_pins[12]	transitions[0x0=>0x1]	23	1		T63	3		T240	1		T243	1
all_pins[12]	transitions[0x1=>0x0]	28	1		T61	2		T62	3		T238	4
all_pins[13]	values[0x0]	2221	1		T1	4		T2	4		T3	2
all_pins[13]	values[0x1]	37	1		T60	1		T61	2		T62	3
all_pins[13]	transitions[0x0=>0x1]	29	1		T60	1		T61	2		T62	3
all_pins[13]	transitions[0x1=>0x0]	31	1		T62	1		T63	3		T66	2
all_pins[14]	values[0x0]	2219	1		T1	4		T2	4		T3	2
all_pins[14]	values[0x1]	39	1		T62	1		T63	3		T238	2
all_pins[14]	transitions[0x0=>0x1]	28	1		T63	3		T238	1		T240	1
all_pins[14]	transitions[0x1=>0x0]	25	1		T60	3		T61	1		T62	2
all_pins[15]	values[0x0]	2222	1		T1	4		T2	4		T3	2
all_pins[15]	values[0x1]	36	1		T60	3		T61	1		T62	3
all_pins[15]	transitions[0x0=>0x1]	29	1		T60	3		T61	1		T62	3
all_pins[15]	transitions[0x1=>0x0]	23	1		T60	1		T63	1		T65	3
all_pins[16]	values[0x0]	2228	1		T1	4		T2	4		T3	2
all_pins[16]	values[0x1]	30	1		T60	1		T63	1		T65	3
all_pins[16]	transitions[0x0=>0x1]	24	1		T63	1		T65	3		T240	2
all_pins[16]	transitions[0x1=>0x0]	34	1		T62	3		T63	1		T238	2
all_pins[17]	values[0x0]	2218	1		T1	4		T2	4		T3	2
all_pins[17]	values[0x1]	40	1		T60	1		T62	3		T63	1
all_pins[17]	transitions[0x0=>0x1]	22	1		T62	2		T238	1		T241	1
all_pins[17]	transitions[0x1=>0x0]	20	1		T62	2		T64	1		T238	1