Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	145	1		T60	4		T61	4		T62	7
all_values[1]	145	1		T60	4		T61	4		T62	7
all_values[2]	145	1		T60	4		T61	4		T62	7
all_values[3]	145	1		T60	4		T61	4		T62	7
all_values[4]	145	1		T60	4		T61	4		T62	7
all_values[5]	145	1		T60	4		T61	4		T62	7
all_values[6]	145	1		T60	4		T61	4		T62	7
all_values[7]	145	1		T60	4		T61	4		T62	7
all_values[8]	145	1		T60	4		T61	4		T62	7
all_values[9]	145	1		T60	4		T61	4		T62	7
all_values[10]	145	1		T60	4		T61	4		T62	7
all_values[11]	145	1		T60	4		T61	4		T62	7
all_values[12]	145	1		T60	4		T61	4		T62	7
all_values[13]	145	1		T60	4		T61	4		T62	7
all_values[14]	145	1		T60	4		T61	4		T62	7
all_values[15]	145	1		T60	4		T61	4		T62	7
all_values[16]	145	1		T60	4		T61	4		T62	7
all_values[17]	145	1		T60	4		T61	4		T62	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1379	1		T60	40		T61	48		T62	66
auto[1]	1231	1		T60	32		T61	24		T62	60

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	493	1		T60	7		T61	17		T62	13
auto[1]	2117	1		T60	65		T61	55		T62	113

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1546	1		T60	37		T61	45		T62	72
auto[1]	1064	1		T60	35		T61	27		T62	54

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	13	1		T63	1		T238	1		T65	1
all_values[0]	auto[0]	auto[0]	auto[1]	25	1		T60	1		T61	2		T62	1
all_values[0]	auto[0]	auto[1]	auto[0]	9	1		T63	1		T241	3		T244	1
all_values[0]	auto[0]	auto[1]	auto[1]	33	1		T60	1		T62	1		T64	1
all_values[0]	auto[1]	auto[0]	auto[1]	38	1		T60	2		T61	2		T62	3
all_values[0]	auto[1]	auto[1]	auto[1]	27	1		T62	2		T64	1		T238	1
all_values[1]	auto[0]	auto[0]	auto[0]	16	1		T61	1		T63	1		T64	4
all_values[1]	auto[0]	auto[0]	auto[1]	25	1		T61	1		T62	1		T238	2
all_values[1]	auto[0]	auto[1]	auto[0]	10	1		T61	1		T62	1		T66	3
all_values[1]	auto[0]	auto[1]	auto[1]	33	1		T60	1		T62	2		T63	1
all_values[1]	auto[1]	auto[0]	auto[1]	30	1		T60	1		T63	1		T240	2
all_values[1]	auto[1]	auto[1]	auto[1]	31	1		T60	2		T61	1		T62	3
all_values[2]	auto[0]	auto[0]	auto[0]	20	1		T61	1		T62	1		T64	3
all_values[2]	auto[0]	auto[0]	auto[1]	25	1		T62	1		T63	2		T238	1
all_values[2]	auto[0]	auto[1]	auto[0]	11	1		T64	1		T238	1		T239	2
all_values[2]	auto[0]	auto[1]	auto[1]	32	1		T60	2		T61	1		T62	2
all_values[2]	auto[1]	auto[0]	auto[1]	22	1		T60	1		T61	2		T63	1
all_values[2]	auto[1]	auto[1]	auto[1]	35	1		T60	1		T62	3		T63	1
all_values[3]	auto[0]	auto[0]	auto[0]	12	1		T63	1		T64	1		T238	1
all_values[3]	auto[0]	auto[0]	auto[1]	31	1		T62	2		T63	1		T238	2
all_values[3]	auto[0]	auto[1]	auto[0]	16	1		T63	1		T240	1		T239	1
all_values[3]	auto[0]	auto[1]	auto[1]	29	1		T60	2		T61	2		T62	1
all_values[3]	auto[1]	auto[0]	auto[1]	30	1		T60	1		T61	1		T62	4
all_values[3]	auto[1]	auto[1]	auto[1]	27	1		T60	1		T61	1		T64	2
all_values[4]	auto[0]	auto[0]	auto[0]	24	1		T60	2		T61	2		T238	2
all_values[4]	auto[0]	auto[0]	auto[1]	31	1		T61	1		T62	3		T63	2
all_values[4]	auto[0]	auto[1]	auto[0]	10	1		T238	2		T245	1		T244	3
all_values[4]	auto[0]	auto[1]	auto[1]	26	1		T60	1		T62	1		T63	1
all_values[4]	auto[1]	auto[0]	auto[1]	31	1		T61	1		T62	1		T64	2
all_values[4]	auto[1]	auto[1]	auto[1]	23	1		T60	1		T62	2		T63	1
all_values[5]	auto[0]	auto[0]	auto[0]	13	1		T64	1		T243	2		T246	1
all_values[5]	auto[0]	auto[0]	auto[1]	31	1		T60	2		T61	3		T62	2
all_values[5]	auto[0]	auto[1]	auto[0]	7	1		T241	2		T242	1		T244	1
all_values[5]	auto[0]	auto[1]	auto[1]	30	1		T62	4		T63	2		T238	2
all_values[5]	auto[1]	auto[0]	auto[1]	28	1		T60	2		T61	1		T238	1
all_values[5]	auto[1]	auto[1]	auto[1]	36	1		T62	1		T63	2		T64	2
all_values[6]	auto[0]	auto[0]	auto[0]	16	1		T61	1		T64	2		T238	1
all_values[6]	auto[0]	auto[0]	auto[1]	32	1		T60	2		T61	1		T62	3
all_values[6]	auto[0]	auto[1]	auto[0]	9	1		T64	2		T242	1		T245	1
all_values[6]	auto[0]	auto[1]	auto[1]	31	1		T62	2		T63	2		T238	1
all_values[6]	auto[1]	auto[0]	auto[1]	34	1		T60	1		T62	1		T63	1
all_values[6]	auto[1]	auto[1]	auto[1]	23	1		T60	1		T61	2		T62	1
all_values[7]	auto[0]	auto[0]	auto[0]	20	1		T60	1		T61	1		T62	1
all_values[7]	auto[0]	auto[0]	auto[1]	24	1		T60	1		T61	1		T62	2
all_values[7]	auto[0]	auto[1]	auto[0]	13	1		T63	1		T64	1		T239	1
all_values[7]	auto[0]	auto[1]	auto[1]	25	1		T63	2		T64	1		T240	3
all_values[7]	auto[1]	auto[0]	auto[1]	30	1		T60	2		T62	1		T63	1
all_values[7]	auto[1]	auto[1]	auto[1]	33	1		T61	2		T62	3		T64	1
all_values[8]	auto[0]	auto[0]	auto[0]	19	1		T61	2		T65	1		T240	3
all_values[8]	auto[0]	auto[0]	auto[1]	18	1		T62	1		T63	1		T240	1
all_values[8]	auto[0]	auto[1]	auto[0]	9	1		T66	1		T240	2		T242	2
all_values[8]	auto[0]	auto[1]	auto[1]	40	1		T60	2		T61	1		T62	3
all_values[8]	auto[1]	auto[0]	auto[1]	32	1		T60	1		T61	1		T62	2
all_values[8]	auto[1]	auto[1]	auto[1]	27	1		T60	1		T62	1		T238	1
all_values[9]	auto[0]	auto[0]	auto[0]	18	1		T63	1		T64	1		T238	4
all_values[9]	auto[0]	auto[0]	auto[1]	34	1		T61	1		T62	2		T64	1
all_values[9]	auto[0]	auto[1]	auto[0]	12	1		T62	1		T241	4		T245	1
all_values[9]	auto[0]	auto[1]	auto[1]	24	1		T60	1		T61	1		T62	1
all_values[9]	auto[1]	auto[0]	auto[1]	35	1		T60	2		T61	2		T62	2
all_values[9]	auto[1]	auto[1]	auto[1]	22	1		T60	1		T62	1		T63	1
all_values[10]	auto[0]	auto[0]	auto[0]	19	1		T60	2		T61	1		T65	4
all_values[10]	auto[0]	auto[0]	auto[1]	33	1		T62	4		T63	2		T66	2
all_values[10]	auto[0]	auto[1]	auto[0]	7	1		T241	2		T244	1		T246	1
all_values[10]	auto[0]	auto[1]	auto[1]	31	1		T60	1		T61	2		T64	2
all_values[10]	auto[1]	auto[0]	auto[1]	27	1		T62	2		T63	2		T64	1
all_values[10]	auto[1]	auto[1]	auto[1]	28	1		T60	1		T61	1		T62	1
all_values[11]	auto[0]	auto[0]	auto[0]	13	1		T61	1		T63	1		T238	2
all_values[11]	auto[0]	auto[0]	auto[1]	32	1		T61	1		T62	1		T64	3
all_values[11]	auto[0]	auto[1]	auto[0]	8	1		T62	2		T63	3		T239	1
all_values[11]	auto[0]	auto[1]	auto[1]	30	1		T60	2		T61	1		T65	1
all_values[11]	auto[1]	auto[0]	auto[1]	32	1		T60	1		T61	1		T62	1
all_values[11]	auto[1]	auto[1]	auto[1]	30	1		T60	1		T62	3		T242	1
all_values[12]	auto[0]	auto[0]	auto[0]	23	1		T61	3		T62	4		T238	1
all_values[12]	auto[0]	auto[0]	auto[1]	24	1		T60	2		T62	1		T64	3
all_values[12]	auto[0]	auto[1]	auto[0]	16	1		T61	1		T62	1		T241	4
all_values[12]	auto[0]	auto[1]	auto[1]	28	1		T63	2		T238	2		T66	1
all_values[12]	auto[1]	auto[0]	auto[1]	29	1		T60	1		T62	1		T63	1
all_values[12]	auto[1]	auto[1]	auto[1]	25	1		T60	1		T63	1		T66	1
all_values[13]	auto[0]	auto[0]	auto[0]	14	1		T60	1		T61	1		T62	1
all_values[13]	auto[0]	auto[0]	auto[1]	25	1		T60	2		T62	1		T63	1
all_values[13]	auto[0]	auto[1]	auto[0]	7	1		T61	1		T62	1		T63	1
all_values[13]	auto[0]	auto[1]	auto[1]	39	1		T61	1		T62	1		T64	2
all_values[13]	auto[1]	auto[0]	auto[1]	33	1		T62	2		T63	2		T64	1
all_values[13]	auto[1]	auto[1]	auto[1]	27	1		T60	1		T61	1		T62	1
all_values[14]	auto[0]	auto[0]	auto[0]	22	1		T60	1		T64	4		T66	2
all_values[14]	auto[0]	auto[0]	auto[1]	31	1		T61	1		T62	2		T238	2
all_values[14]	auto[0]	auto[1]	auto[0]	9	1		T240	2		T241	1		T242	2
all_values[14]	auto[0]	auto[1]	auto[1]	29	1		T60	1		T61	1		T62	3
all_values[14]	auto[1]	auto[0]	auto[1]	27	1		T60	1		T61	1		T62	1
all_values[14]	auto[1]	auto[1]	auto[1]	27	1		T60	1		T61	1		T62	1
all_values[15]	auto[0]	auto[0]	auto[0]	8	1		T66	1		T245	2		T246	2
all_values[15]	auto[0]	auto[0]	auto[1]	35	1		T61	1		T62	2		T64	1
all_values[15]	auto[0]	auto[1]	auto[0]	6	1		T240	3		T245	2		T244	1
all_values[15]	auto[0]	auto[1]	auto[1]	29	1		T60	1		T62	1		T63	2
all_values[15]	auto[1]	auto[0]	auto[1]	37	1		T60	1		T61	3		T62	1
all_values[15]	auto[1]	auto[1]	auto[1]	30	1		T60	2		T62	3		T64	1
all_values[16]	auto[0]	auto[0]	auto[0]	19	1		T65	1		T240	2		T243	4
all_values[16]	auto[0]	auto[0]	auto[1]	35	1		T60	3		T61	2		T62	3
all_values[16]	auto[0]	auto[1]	auto[0]	21	1		T63	1		T66	4		T240	3
all_values[16]	auto[0]	auto[1]	auto[1]	19	1		T62	2		T65	2		T240	1
all_values[16]	auto[1]	auto[0]	auto[1]	28	1		T60	1		T61	2		T62	2
all_values[16]	auto[1]	auto[1]	auto[1]	23	1		T63	1		T240	1		T241	1
all_values[17]	auto[0]	auto[0]	auto[0]	17	1		T64	1		T240	3		T239	2
all_values[17]	auto[0]	auto[0]	auto[1]	24	1		T61	1		T62	2		T63	2
all_values[17]	auto[0]	auto[1]	auto[0]	7	1		T66	1		T240	1		T244	1
all_values[17]	auto[0]	auto[1]	auto[1]	30	1		T60	2		T61	2		T62	1
all_values[17]	auto[1]	auto[0]	auto[1]	35	1		T60	2		T61	1		T62	1
all_values[17]	auto[1]	auto[1]	auto[1]	32	1		T62	3		T63	1		T238	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal