Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.52 96.31 88.57 97.17 46.88 94.11 97.36 92.25


Total test records in report: 794
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T761 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.482868621 Mar 17 02:00:02 PM PDT 24 Mar 17 02:00:06 PM PDT 24 85089657 ps
T762 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.406970213 Mar 17 01:59:40 PM PDT 24 Mar 17 01:59:42 PM PDT 24 188960523 ps
T243 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2349568988 Mar 17 02:01:21 PM PDT 24 Mar 17 02:01:22 PM PDT 24 21624344 ps
T196 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2024075612 Mar 17 01:59:18 PM PDT 24 Mar 17 01:59:19 PM PDT 24 26559345 ps
T245 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2884577899 Mar 17 02:01:00 PM PDT 24 Mar 17 02:01:01 PM PDT 24 25402898 ps
T59 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2795423140 Mar 17 01:59:43 PM PDT 24 Mar 17 01:59:44 PM PDT 24 25740592 ps
T244 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1108561959 Mar 17 02:00:07 PM PDT 24 Mar 17 02:00:08 PM PDT 24 26518865 ps
T763 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3458068128 Mar 17 02:00:21 PM PDT 24 Mar 17 02:00:24 PM PDT 24 207770167 ps
T246 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2868523864 Mar 17 02:01:06 PM PDT 24 Mar 17 02:01:07 PM PDT 24 31673826 ps
T236 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2548623136 Mar 17 01:59:36 PM PDT 24 Mar 17 01:59:38 PM PDT 24 81629940 ps
T764 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.763073596 Mar 17 02:00:36 PM PDT 24 Mar 17 02:00:39 PM PDT 24 82745175 ps
T237 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.857009184 Mar 17 02:00:30 PM PDT 24 Mar 17 02:00:32 PM PDT 24 78684080 ps
T161 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.787236111 Mar 17 02:00:02 PM PDT 24 Mar 17 02:00:04 PM PDT 24 63592689 ps
T765 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1994799090 Mar 17 02:00:48 PM PDT 24 Mar 17 02:00:50 PM PDT 24 122725834 ps
T766 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1176768699 Mar 17 02:00:57 PM PDT 24 Mar 17 02:00:58 PM PDT 24 101839343 ps
T767 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2005523832 Mar 17 02:01:13 PM PDT 24 Mar 17 02:01:14 PM PDT 24 23980357 ps
T768 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3752980549 Mar 17 02:00:00 PM PDT 24 Mar 17 02:00:05 PM PDT 24 401152883 ps
T769 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3275401941 Mar 17 02:01:07 PM PDT 24 Mar 17 02:01:07 PM PDT 24 21511135 ps
T770 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2727269374 Mar 17 01:58:56 PM PDT 24 Mar 17 01:58:56 PM PDT 24 32521588 ps
T771 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.908074459 Mar 17 02:00:23 PM PDT 24 Mar 17 02:00:24 PM PDT 24 34217074 ps
T772 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.4264061957 Mar 17 01:59:19 PM PDT 24 Mar 17 01:59:22 PM PDT 24 216441052 ps
T773 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.318081167 Mar 17 02:00:41 PM PDT 24 Mar 17 02:00:42 PM PDT 24 22816070 ps
T774 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.4199158377 Mar 17 02:01:20 PM PDT 24 Mar 17 02:01:21 PM PDT 24 20209171 ps
T775 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1809484245 Mar 17 02:00:07 PM PDT 24 Mar 17 02:00:09 PM PDT 24 154964458 ps
T776 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1943541427 Mar 17 01:59:30 PM PDT 24 Mar 17 01:59:33 PM PDT 24 173850473 ps
T777 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2600351514 Mar 17 02:00:16 PM PDT 24 Mar 17 02:00:19 PM PDT 24 259151842 ps
T778 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2701755759 Mar 17 01:58:56 PM PDT 24 Mar 17 01:58:59 PM PDT 24 61000351 ps
T779 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1711164151 Mar 17 02:00:17 PM PDT 24 Mar 17 02:00:17 PM PDT 24 22585897 ps
T780 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.619437825 Mar 17 01:59:37 PM PDT 24 Mar 17 01:59:38 PM PDT 24 24263220 ps
T781 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2993819575 Mar 17 02:00:23 PM PDT 24 Mar 17 02:00:24 PM PDT 24 21200328 ps
T782 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3612977305 Mar 17 02:00:37 PM PDT 24 Mar 17 02:00:39 PM PDT 24 127762795 ps
T783 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.219797042 Mar 17 02:00:22 PM PDT 24 Mar 17 02:00:24 PM PDT 24 96108044 ps
T784 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2320462542 Mar 17 02:00:41 PM PDT 24 Mar 17 02:00:43 PM PDT 24 55506990 ps
T785 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2161933384 Mar 17 02:00:47 PM PDT 24 Mar 17 02:00:48 PM PDT 24 24695819 ps
T52 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1727868327 Mar 17 01:59:56 PM PDT 24 Mar 17 01:59:57 PM PDT 24 55294611 ps
T786 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1926908059 Mar 17 02:01:21 PM PDT 24 Mar 17 02:01:22 PM PDT 24 20968313 ps
T787 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2249794844 Mar 17 02:00:22 PM PDT 24 Mar 17 02:00:24 PM PDT 24 47384441 ps
T788 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4163690305 Mar 17 02:01:13 PM PDT 24 Mar 17 02:01:14 PM PDT 24 25324377 ps
T789 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2540794187 Mar 17 02:00:57 PM PDT 24 Mar 17 02:00:58 PM PDT 24 66854262 ps
T790 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1009644010 Mar 17 02:00:53 PM PDT 24 Mar 17 02:00:56 PM PDT 24 150707341 ps
T791 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1796198144 Mar 17 01:59:56 PM PDT 24 Mar 17 02:00:00 PM PDT 24 470845358 ps
T792 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.652287654 Mar 17 02:00:53 PM PDT 24 Mar 17 02:00:55 PM PDT 24 141650304 ps
T793 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3918975252 Mar 17 02:01:13 PM PDT 24 Mar 17 02:01:14 PM PDT 24 24895817 ps
T794 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.501227336 Mar 17 01:59:25 PM PDT 24 Mar 17 01:59:26 PM PDT 24 39814009 ps

Test location /workspace/coverage/default/43.usbdev_smoke.1367482727
Short name T5
Test name
Test status
Simulation time 8470897087 ps
CPU time 8.78 seconds
Started Mar 17 01:42:58 PM PDT 24
Finished Mar 17 01:43:07 PM PDT 24
Peak memory 203668 kb
Host smart-bfcd77e1-d5cb-416b-a871-4f9782695aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13674
82727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1367482727
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2506917324
Short name T62
Test name
Test status
Simulation time 26969382 ps
CPU time 0.66 seconds
Started Mar 17 02:01:06 PM PDT 24
Finished Mar 17 02:01:06 PM PDT 24
Peak memory 202024 kb
Host smart-faa31b22-8405-429b-984c-9a99c4994d62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2506917324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2506917324
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2529170024
Short name T7
Test name
Test status
Simulation time 8432017325 ps
CPU time 8.17 seconds
Started Mar 17 01:42:49 PM PDT 24
Finished Mar 17 01:42:57 PM PDT 24
Peak memory 203720 kb
Host smart-d45d13ea-5b41-412b-8fac-0c41cc955edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25291
70024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2529170024
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.4106679453
Short name T10
Test name
Test status
Simulation time 282435923 ps
CPU time 2.17 seconds
Started Mar 17 01:42:47 PM PDT 24
Finished Mar 17 01:42:49 PM PDT 24
Peak memory 203716 kb
Host smart-55f9d45c-9dea-4f3b-959d-8701b5ec985d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41066
79453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.4106679453
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1324624571
Short name T53
Test name
Test status
Simulation time 72800539 ps
CPU time 1.21 seconds
Started Mar 17 02:00:36 PM PDT 24
Finished Mar 17 02:00:38 PM PDT 24
Peak memory 212072 kb
Host smart-0f1545c8-896f-4804-9071-7c4844c22866
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324624571 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.1324624571
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2630948851
Short name T240
Test name
Test status
Simulation time 22424683 ps
CPU time 0.63 seconds
Started Mar 17 02:00:40 PM PDT 24
Finished Mar 17 02:00:42 PM PDT 24
Peak memory 202032 kb
Host smart-ff6a70cb-4ab2-4597-b503-07667439e9c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2630948851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2630948851
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2305898177
Short name T167
Test name
Test status
Simulation time 8361466349 ps
CPU time 7.4 seconds
Started Mar 17 01:40:34 PM PDT 24
Finished Mar 17 01:40:42 PM PDT 24
Peak memory 203456 kb
Host smart-3264fcb4-4eb3-4484-ac22-3d6b6161b33e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23058
98177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2305898177
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2689652962
Short name T48
Test name
Test status
Simulation time 106276153 ps
CPU time 0.91 seconds
Started Mar 17 01:38:30 PM PDT 24
Finished Mar 17 01:38:31 PM PDT 24
Peak memory 219508 kb
Host smart-6ef6ed3c-52c0-40c1-96c8-d0e7ef443a74
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2689652962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2689652962
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.102224436
Short name T204
Test name
Test status
Simulation time 225509998 ps
CPU time 1.97 seconds
Started Mar 17 01:42:30 PM PDT 24
Finished Mar 17 01:42:32 PM PDT 24
Peak memory 203780 kb
Host smart-2ef1e549-02bb-4750-a7c8-ba901fe5870f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10222
4436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.102224436
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1960834190
Short name T29
Test name
Test status
Simulation time 30827521 ps
CPU time 0.7 seconds
Started Mar 17 01:39:58 PM PDT 24
Finished Mar 17 01:39:59 PM PDT 24
Peak memory 203260 kb
Host smart-12811214-48e9-48ea-a7a8-2f691b2129b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19608
34190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1960834190
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1746411308
Short name T57
Test name
Test status
Simulation time 57480885 ps
CPU time 0.83 seconds
Started Mar 17 01:58:56 PM PDT 24
Finished Mar 17 01:58:57 PM PDT 24
Peak memory 202100 kb
Host smart-233d8d2e-e46f-43c0-985f-cbac31b2b151
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746411308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1746411308
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3161832937
Short name T18
Test name
Test status
Simulation time 8368141622 ps
CPU time 6.92 seconds
Started Mar 17 01:37:43 PM PDT 24
Finished Mar 17 01:37:50 PM PDT 24
Peak memory 203540 kb
Host smart-d7cb375b-01d6-4e90-b3ad-21064fdbb9ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31618
32937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3161832937
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2202032450
Short name T26
Test name
Test status
Simulation time 8424830876 ps
CPU time 7.66 seconds
Started Mar 17 01:39:26 PM PDT 24
Finished Mar 17 01:39:34 PM PDT 24
Peak memory 203664 kb
Host smart-4a981442-18d0-4239-b293-88b3fb461413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22020
32450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2202032450
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.749758761
Short name T238
Test name
Test status
Simulation time 23714629 ps
CPU time 0.64 seconds
Started Mar 17 02:01:05 PM PDT 24
Finished Mar 17 02:01:06 PM PDT 24
Peak memory 201992 kb
Host smart-7d4e721e-55f3-49d1-b169-96c650e096d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=749758761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.749758761
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.318081167
Short name T773
Test name
Test status
Simulation time 22816070 ps
CPU time 0.64 seconds
Started Mar 17 02:00:41 PM PDT 24
Finished Mar 17 02:00:42 PM PDT 24
Peak memory 201988 kb
Host smart-8a29e179-9678-40b7-93dc-8d4f645301f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=318081167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.318081167
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/default/18.usbdev_smoke.152689229
Short name T35
Test name
Test status
Simulation time 8473460457 ps
CPU time 7.94 seconds
Started Mar 17 01:40:33 PM PDT 24
Finished Mar 17 01:40:41 PM PDT 24
Peak memory 203680 kb
Host smart-49a719ef-3187-4ac9-bfd8-34f94ad78d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15268
9229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.152689229
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1708028269
Short name T54
Test name
Test status
Simulation time 135728424 ps
CPU time 1.5 seconds
Started Mar 17 02:00:01 PM PDT 24
Finished Mar 17 02:00:04 PM PDT 24
Peak memory 202264 kb
Host smart-45f32904-2420-4747-9aba-100e8b1fee2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708028269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c
sr_outstanding.1708028269
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1611271799
Short name T47
Test name
Test status
Simulation time 79925528 ps
CPU time 2.9 seconds
Started Mar 17 01:59:24 PM PDT 24
Finished Mar 17 01:59:27 PM PDT 24
Peak memory 202204 kb
Host smart-578af325-0710-40a8-9792-c50357bd75a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1611271799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1611271799
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2260541438
Short name T214
Test name
Test status
Simulation time 8474035437 ps
CPU time 8.93 seconds
Started Mar 17 01:42:28 PM PDT 24
Finished Mar 17 01:42:38 PM PDT 24
Peak memory 203648 kb
Host smart-d114e24a-2f87-47a7-98f0-01f774dec6d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22605
41438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2260541438
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3325090893
Short name T127
Test name
Test status
Simulation time 8476619636 ps
CPU time 7.84 seconds
Started Mar 17 01:39:58 PM PDT 24
Finished Mar 17 01:40:06 PM PDT 24
Peak memory 203744 kb
Host smart-64e4ebdc-3838-44dc-9a2a-0bb4e42422f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33250
90893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3325090893
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3108008808
Short name T144
Test name
Test status
Simulation time 8475080201 ps
CPU time 8.77 seconds
Started Mar 17 01:37:35 PM PDT 24
Finished Mar 17 01:37:44 PM PDT 24
Peak memory 203704 kb
Host smart-cb5c629a-7825-48ad-ae72-09d3f47f7430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31080
08808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3108008808
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2763825479
Short name T134
Test name
Test status
Simulation time 8473959645 ps
CPU time 7.96 seconds
Started Mar 17 01:37:53 PM PDT 24
Finished Mar 17 01:38:03 PM PDT 24
Peak memory 203744 kb
Host smart-ca02fd53-5f46-4ac0-bfd9-f7f7f6201f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27638
25479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2763825479
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_smoke.789305662
Short name T136
Test name
Test status
Simulation time 8472122819 ps
CPU time 7.86 seconds
Started Mar 17 01:39:17 PM PDT 24
Finished Mar 17 01:39:25 PM PDT 24
Peak memory 203728 kb
Host smart-121d6b6f-b32d-4c17-b2ee-be78e5caa33e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78930
5662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.789305662
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1710276571
Short name T140
Test name
Test status
Simulation time 8477760335 ps
CPU time 7.52 seconds
Started Mar 17 01:39:26 PM PDT 24
Finished Mar 17 01:39:35 PM PDT 24
Peak memory 203744 kb
Host smart-a162945c-629c-42cc-b790-0b19ca3ef39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17102
76571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1710276571
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2308286777
Short name T221
Test name
Test status
Simulation time 8413864240 ps
CPU time 7.63 seconds
Started Mar 17 01:38:09 PM PDT 24
Finished Mar 17 01:38:17 PM PDT 24
Peak memory 203712 kb
Host smart-201a533f-7043-464b-a7ac-39ac3acce91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23082
86777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2308286777
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1699498037
Short name T38
Test name
Test status
Simulation time 8473370182 ps
CPU time 9.54 seconds
Started Mar 17 01:42:14 PM PDT 24
Finished Mar 17 01:42:24 PM PDT 24
Peak memory 203692 kb
Host smart-a8f682cb-e07b-4aad-b833-64a9e6c050ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16994
98037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1699498037
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2884577899
Short name T245
Test name
Test status
Simulation time 25402898 ps
CPU time 0.61 seconds
Started Mar 17 02:01:00 PM PDT 24
Finished Mar 17 02:01:01 PM PDT 24
Peak memory 202008 kb
Host smart-f6182fdf-6927-4148-b7a6-1e551ccfe56a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2884577899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2884577899
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.323243164
Short name T51
Test name
Test status
Simulation time 29270986 ps
CPU time 0.74 seconds
Started Mar 17 01:59:14 PM PDT 24
Finished Mar 17 01:59:15 PM PDT 24
Peak memory 202136 kb
Host smart-e55f6102-ddf7-4807-b96e-2693a8d02c62
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323243164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.323243164
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1015855805
Short name T213
Test name
Test status
Simulation time 64795703 ps
CPU time 1.79 seconds
Started Mar 17 01:41:06 PM PDT 24
Finished Mar 17 01:41:08 PM PDT 24
Peak memory 203696 kb
Host smart-e9a1ad86-aadb-44bc-8951-fab5ba693243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10158
55805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1015855805
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_smoke.4171829166
Short name T207
Test name
Test status
Simulation time 8479411097 ps
CPU time 7.41 seconds
Started Mar 17 01:39:13 PM PDT 24
Finished Mar 17 01:39:20 PM PDT 24
Peak memory 203628 kb
Host smart-a330e17a-425c-4146-9b01-6228a7f39fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41718
29166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.4171829166
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3178742858
Short name T184
Test name
Test status
Simulation time 94382417 ps
CPU time 2.84 seconds
Started Mar 17 02:00:41 PM PDT 24
Finished Mar 17 02:00:44 PM PDT 24
Peak memory 202324 kb
Host smart-b143de2a-199c-45db-9562-28b645382c5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3178742858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3178742858
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1727868327
Short name T52
Test name
Test status
Simulation time 55294611 ps
CPU time 0.87 seconds
Started Mar 17 01:59:56 PM PDT 24
Finished Mar 17 01:59:57 PM PDT 24
Peak memory 202120 kb
Host smart-8b1c65b2-f165-4724-9371-75a2716b70be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727868327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1727868327
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1103449259
Short name T211
Test name
Test status
Simulation time 8409977391 ps
CPU time 7.72 seconds
Started Mar 17 01:39:18 PM PDT 24
Finished Mar 17 01:39:26 PM PDT 24
Peak memory 203716 kb
Host smart-94cb350c-4004-49df-af8c-f659b36146c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11034
49259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1103449259
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2763460322
Short name T74
Test name
Test status
Simulation time 26685554 ps
CPU time 0.65 seconds
Started Mar 17 01:39:47 PM PDT 24
Finished Mar 17 01:39:47 PM PDT 24
Peak memory 203284 kb
Host smart-e62d742b-1bff-430c-93bf-71739df8f9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27634
60322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2763460322
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.679108825
Short name T270
Test name
Test status
Simulation time 8358419250 ps
CPU time 7.91 seconds
Started Mar 17 01:37:48 PM PDT 24
Finished Mar 17 01:37:57 PM PDT 24
Peak memory 203548 kb
Host smart-0162620e-e767-4ed7-ada0-7a1910d1250b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67910
8825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.679108825
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.606252502
Short name T146
Test name
Test status
Simulation time 8479113054 ps
CPU time 7.41 seconds
Started Mar 17 01:39:32 PM PDT 24
Finished Mar 17 01:39:39 PM PDT 24
Peak memory 203768 kb
Host smart-e3e0a46b-6553-4a5c-a8be-e190b5b328f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60625
2502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.606252502
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_smoke.189634355
Short name T149
Test name
Test status
Simulation time 8478076643 ps
CPU time 7.88 seconds
Started Mar 17 01:41:09 PM PDT 24
Finished Mar 17 01:41:18 PM PDT 24
Peak memory 203680 kb
Host smart-b6528a03-c9eb-400c-9ebf-f3750b32f6ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18963
4355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.189634355
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.238636622
Short name T83
Test name
Test status
Simulation time 110425402 ps
CPU time 1.44 seconds
Started Mar 17 02:01:00 PM PDT 24
Finished Mar 17 02:01:01 PM PDT 24
Peak memory 202280 kb
Host smart-87695e4b-ce77-45d3-ac46-116368f64428
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238636622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_c
sr_outstanding.238636622
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.787236111
Short name T161
Test name
Test status
Simulation time 63592689 ps
CPU time 1.58 seconds
Started Mar 17 02:00:02 PM PDT 24
Finished Mar 17 02:00:04 PM PDT 24
Peak memory 202288 kb
Host smart-2c1dd6d7-6db4-4831-858c-25e1ca16a1ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787236111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_cs
r_outstanding.787236111
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3505281338
Short name T104
Test name
Test status
Simulation time 8432647218 ps
CPU time 7.89 seconds
Started Mar 17 01:37:41 PM PDT 24
Finished Mar 17 01:37:49 PM PDT 24
Peak memory 203728 kb
Host smart-7b5ef580-40d6-441a-8541-9b55b32a02a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35052
81338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3505281338
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.755958915
Short name T713
Test name
Test status
Simulation time 8416197841 ps
CPU time 7.59 seconds
Started Mar 17 01:39:17 PM PDT 24
Finished Mar 17 01:39:25 PM PDT 24
Peak memory 203712 kb
Host smart-732bb0c1-0cef-4795-a841-01e681ccbcfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75595
8915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.755958915
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.1912659114
Short name T88
Test name
Test status
Simulation time 8418096486 ps
CPU time 7.31 seconds
Started Mar 17 01:39:26 PM PDT 24
Finished Mar 17 01:39:34 PM PDT 24
Peak memory 203604 kb
Host smart-9ecae6fc-a40d-4763-bfec-9276e1a93762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19126
59114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.1912659114
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3625956686
Short name T106
Test name
Test status
Simulation time 8418049747 ps
CPU time 7.43 seconds
Started Mar 17 01:39:35 PM PDT 24
Finished Mar 17 01:39:43 PM PDT 24
Peak memory 203600 kb
Host smart-60cc07f4-950a-47a7-bb26-fde15c1873f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36259
56686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3625956686
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.990397008
Short name T158
Test name
Test status
Simulation time 8356524731 ps
CPU time 7.77 seconds
Started Mar 17 01:39:58 PM PDT 24
Finished Mar 17 01:40:06 PM PDT 24
Peak memory 203528 kb
Host smart-0330b8e7-1170-4b48-80cf-d73158813c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99039
7008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.990397008
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3074460736
Short name T640
Test name
Test status
Simulation time 8430450058 ps
CPU time 8.11 seconds
Started Mar 17 01:39:53 PM PDT 24
Finished Mar 17 01:40:01 PM PDT 24
Peak memory 203716 kb
Host smart-5ad5bd6f-d618-4a55-8bbb-7ce5bc91527d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30744
60736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3074460736
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3266327677
Short name T113
Test name
Test status
Simulation time 8418239393 ps
CPU time 8.14 seconds
Started Mar 17 01:40:05 PM PDT 24
Finished Mar 17 01:40:13 PM PDT 24
Peak memory 203684 kb
Host smart-3a3f6440-e9c1-4a1d-a50e-1380c77f4716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32663
27677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3266327677
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3179395281
Short name T100
Test name
Test status
Simulation time 8410585379 ps
CPU time 7.8 seconds
Started Mar 17 01:40:18 PM PDT 24
Finished Mar 17 01:40:26 PM PDT 24
Peak memory 203704 kb
Host smart-e3473ef2-298b-44c4-8bae-fcd9d4aa73b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31793
95281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3179395281
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2419404859
Short name T93
Test name
Test status
Simulation time 8384071475 ps
CPU time 7.62 seconds
Started Mar 17 01:38:08 PM PDT 24
Finished Mar 17 01:38:16 PM PDT 24
Peak memory 203724 kb
Host smart-5821a882-22ad-43f0-b241-8ce348e4b15e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24194
04859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2419404859
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.3851989310
Short name T110
Test name
Test status
Simulation time 8387254886 ps
CPU time 7.33 seconds
Started Mar 17 01:41:42 PM PDT 24
Finished Mar 17 01:41:49 PM PDT 24
Peak memory 203640 kb
Host smart-c09eacc5-c67c-4c7b-8fe0-4bf64d000ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38519
89310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.3851989310
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3455143876
Short name T547
Test name
Test status
Simulation time 8454213418 ps
CPU time 9.9 seconds
Started Mar 17 01:38:27 PM PDT 24
Finished Mar 17 01:38:37 PM PDT 24
Peak memory 203640 kb
Host smart-e23760ae-357f-4a24-8b6a-e92085b54346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34551
43876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3455143876
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1905681027
Short name T89
Test name
Test status
Simulation time 8415402131 ps
CPU time 7.8 seconds
Started Mar 17 01:42:58 PM PDT 24
Finished Mar 17 01:43:06 PM PDT 24
Peak memory 203720 kb
Host smart-fa0cfadf-416a-4500-a4d6-834497f3c157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19056
81027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1905681027
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3064230009
Short name T190
Test name
Test status
Simulation time 209918029 ps
CPU time 2.22 seconds
Started Mar 17 01:59:02 PM PDT 24
Finished Mar 17 01:59:05 PM PDT 24
Peak memory 202288 kb
Host smart-1a1da22a-9c65-4e22-956a-4aaa6cf52d8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064230009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3064230009
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1911101379
Short name T187
Test name
Test status
Simulation time 121592438 ps
CPU time 1.89 seconds
Started Mar 17 01:59:00 PM PDT 24
Finished Mar 17 01:59:03 PM PDT 24
Peak memory 210440 kb
Host smart-06fbe54e-2e4c-4608-8c95-c0bf1b95f701
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911101379 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.1911101379
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2727269374
Short name T770
Test name
Test status
Simulation time 32521588 ps
CPU time 0.68 seconds
Started Mar 17 01:58:56 PM PDT 24
Finished Mar 17 01:58:56 PM PDT 24
Peak memory 201940 kb
Host smart-2f9a750f-9a4b-457b-a09b-062f09a7cd9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2727269374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2727269374
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2701755759
Short name T778
Test name
Test status
Simulation time 61000351 ps
CPU time 2.09 seconds
Started Mar 17 01:58:56 PM PDT 24
Finished Mar 17 01:58:59 PM PDT 24
Peak memory 202324 kb
Host smart-1a7bbf0f-04d4-4182-b2b3-e8ace6f01071
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2701755759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2701755759
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3033806345
Short name T183
Test name
Test status
Simulation time 49154376 ps
CPU time 1.65 seconds
Started Mar 17 01:58:55 PM PDT 24
Finished Mar 17 01:58:57 PM PDT 24
Peak memory 202216 kb
Host smart-8427163b-8649-4450-b370-d441a8318a09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3033806345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3033806345
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.4264061957
Short name T772
Test name
Test status
Simulation time 216441052 ps
CPU time 2.16 seconds
Started Mar 17 01:59:19 PM PDT 24
Finished Mar 17 01:59:22 PM PDT 24
Peak memory 202240 kb
Host smart-9beb557f-5188-45d9-9787-1394033287de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264061957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.4264061957
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2024075612
Short name T196
Test name
Test status
Simulation time 26559345 ps
CPU time 0.79 seconds
Started Mar 17 01:59:18 PM PDT 24
Finished Mar 17 01:59:19 PM PDT 24
Peak memory 202100 kb
Host smart-01fc3b38-0fcb-420f-a401-162c56776c85
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024075612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2024075612
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.613555984
Short name T194
Test name
Test status
Simulation time 61265793 ps
CPU time 2.14 seconds
Started Mar 17 01:59:14 PM PDT 24
Finished Mar 17 01:59:16 PM PDT 24
Peak memory 202272 kb
Host smart-c38cd4be-0dee-486c-83a2-d13978f9797f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=613555984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.613555984
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.775820740
Short name T753
Test name
Test status
Simulation time 82501453 ps
CPU time 2.33 seconds
Started Mar 17 01:59:14 PM PDT 24
Finished Mar 17 01:59:17 PM PDT 24
Peak memory 202176 kb
Host smart-b92d600e-b94b-4fd2-a76b-90e16afda91d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=775820740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.775820740
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.501227336
Short name T794
Test name
Test status
Simulation time 39814009 ps
CPU time 1.04 seconds
Started Mar 17 01:59:25 PM PDT 24
Finished Mar 17 01:59:26 PM PDT 24
Peak memory 202240 kb
Host smart-a2f33c4e-be28-4fbc-b97a-82e34f0f350d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501227336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_cs
r_outstanding.501227336
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2321774054
Short name T754
Test name
Test status
Simulation time 65650626 ps
CPU time 2.37 seconds
Started Mar 17 01:59:05 PM PDT 24
Finished Mar 17 01:59:08 PM PDT 24
Peak memory 202336 kb
Host smart-75ce0298-dd67-4c43-9542-a3eccb7d25eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2321774054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2321774054
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.857009184
Short name T237
Test name
Test status
Simulation time 78684080 ps
CPU time 1.14 seconds
Started Mar 17 02:00:30 PM PDT 24
Finished Mar 17 02:00:32 PM PDT 24
Peak memory 202252 kb
Host smart-42443ebc-650b-4839-b151-bcb1e99cbc32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857009184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_c
sr_outstanding.857009184
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.219797042
Short name T783
Test name
Test status
Simulation time 96108044 ps
CPU time 1.46 seconds
Started Mar 17 02:00:22 PM PDT 24
Finished Mar 17 02:00:24 PM PDT 24
Peak memory 202340 kb
Host smart-bd3f8180-e7f9-4312-a757-fd4f3cab13f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=219797042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.219797042
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2494117354
Short name T197
Test name
Test status
Simulation time 57598393 ps
CPU time 1.31 seconds
Started Mar 17 02:00:35 PM PDT 24
Finished Mar 17 02:00:37 PM PDT 24
Peak memory 202224 kb
Host smart-4a764df4-f96b-48d0-9401-d11103ddb0cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494117354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_
csr_outstanding.2494117354
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3612977305
Short name T782
Test name
Test status
Simulation time 127762795 ps
CPU time 1.73 seconds
Started Mar 17 02:00:37 PM PDT 24
Finished Mar 17 02:00:39 PM PDT 24
Peak memory 202344 kb
Host smart-5a4a0e89-ca70-4f22-9669-0767285f4a7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3612977305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3612977305
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3527924964
Short name T193
Test name
Test status
Simulation time 92888106 ps
CPU time 1.18 seconds
Started Mar 17 02:00:40 PM PDT 24
Finished Mar 17 02:00:42 PM PDT 24
Peak memory 202268 kb
Host smart-566908c1-b4f3-4b69-ad0e-b4dfa99edaea
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527924964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3527924964
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2320462542
Short name T784
Test name
Test status
Simulation time 55506990 ps
CPU time 1.41 seconds
Started Mar 17 02:00:41 PM PDT 24
Finished Mar 17 02:00:43 PM PDT 24
Peak memory 202228 kb
Host smart-17124524-b604-4842-be7e-c18722280c0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320462542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_
csr_outstanding.2320462542
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.763073596
Short name T764
Test name
Test status
Simulation time 82745175 ps
CPU time 2.67 seconds
Started Mar 17 02:00:36 PM PDT 24
Finished Mar 17 02:00:39 PM PDT 24
Peak memory 202376 kb
Host smart-36a5d1a4-f7e8-48b6-ad97-1c148e1dbf1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=763073596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.763073596
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2511735966
Short name T755
Test name
Test status
Simulation time 46185139 ps
CPU time 1.43 seconds
Started Mar 17 02:00:41 PM PDT 24
Finished Mar 17 02:00:42 PM PDT 24
Peak memory 210532 kb
Host smart-7e19fe26-f979-442b-b075-006c7ec65152
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511735966 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.2511735966
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1231495908
Short name T198
Test name
Test status
Simulation time 78449999 ps
CPU time 1.14 seconds
Started Mar 17 02:00:43 PM PDT 24
Finished Mar 17 02:00:44 PM PDT 24
Peak memory 202252 kb
Host smart-c324231d-74af-4c3d-b4cb-3215798539d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231495908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_
csr_outstanding.1231495908
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1994799090
Short name T765
Test name
Test status
Simulation time 122725834 ps
CPU time 1.84 seconds
Started Mar 17 02:00:48 PM PDT 24
Finished Mar 17 02:00:50 PM PDT 24
Peak memory 210544 kb
Host smart-e73631cc-3b85-4143-a724-4ceb2f50ba53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994799090 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.1994799090
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4179355284
Short name T188
Test name
Test status
Simulation time 118172830 ps
CPU time 1.67 seconds
Started Mar 17 02:00:41 PM PDT 24
Finished Mar 17 02:00:43 PM PDT 24
Peak memory 202312 kb
Host smart-ec02a378-240a-4d7c-beba-f905e937a993
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4179355284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.4179355284
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2795161367
Short name T759
Test name
Test status
Simulation time 69728901 ps
CPU time 1.04 seconds
Started Mar 17 02:00:47 PM PDT 24
Finished Mar 17 02:00:48 PM PDT 24
Peak memory 202236 kb
Host smart-2c50991f-3765-475f-9fdf-75cff97478c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795161367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2795161367
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2161933384
Short name T785
Test name
Test status
Simulation time 24695819 ps
CPU time 0.63 seconds
Started Mar 17 02:00:47 PM PDT 24
Finished Mar 17 02:00:48 PM PDT 24
Peak memory 202036 kb
Host smart-a08e0ed7-cfe3-44d6-8802-827cde042e4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2161933384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2161933384
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1285270298
Short name T234
Test name
Test status
Simulation time 90833186 ps
CPU time 1.36 seconds
Started Mar 17 02:00:48 PM PDT 24
Finished Mar 17 02:00:49 PM PDT 24
Peak memory 202392 kb
Host smart-7bb2aa67-441b-4ae3-a330-489b6fdcc199
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1285270298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1285270298
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3289909871
Short name T760
Test name
Test status
Simulation time 126105088 ps
CPU time 1.73 seconds
Started Mar 17 02:00:54 PM PDT 24
Finished Mar 17 02:00:56 PM PDT 24
Peak memory 210584 kb
Host smart-5c63807f-75d0-4dbf-b819-c3dd1089020a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289909871 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.3289909871
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.957788805
Short name T80
Test name
Test status
Simulation time 24776876 ps
CPU time 0.79 seconds
Started Mar 17 02:00:48 PM PDT 24
Finished Mar 17 02:00:49 PM PDT 24
Peak memory 202088 kb
Host smart-0072da67-14a7-4262-b745-96ac3eae7b74
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957788805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.957788805
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2540794187
Short name T789
Test name
Test status
Simulation time 66854262 ps
CPU time 0.98 seconds
Started Mar 17 02:00:57 PM PDT 24
Finished Mar 17 02:00:58 PM PDT 24
Peak memory 202240 kb
Host smart-9fb98ab5-1449-4d02-a38e-f26081382b66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540794187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_
csr_outstanding.2540794187
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1667857106
Short name T758
Test name
Test status
Simulation time 234375350 ps
CPU time 2.81 seconds
Started Mar 17 02:00:49 PM PDT 24
Finished Mar 17 02:00:52 PM PDT 24
Peak memory 202340 kb
Host smart-9d48deda-f475-4500-9bc4-1f69870ab2de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1667857106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1667857106
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.652287654
Short name T792
Test name
Test status
Simulation time 141650304 ps
CPU time 1.63 seconds
Started Mar 17 02:00:53 PM PDT 24
Finished Mar 17 02:00:55 PM PDT 24
Peak memory 210548 kb
Host smart-a473651e-dfac-48c5-b883-a4c02073cd3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652287654 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.652287654
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.398623530
Short name T235
Test name
Test status
Simulation time 82173865 ps
CPU time 1.13 seconds
Started Mar 17 02:00:58 PM PDT 24
Finished Mar 17 02:00:59 PM PDT 24
Peak memory 202292 kb
Host smart-d132bf36-a57b-4f76-bae3-0f3e50ff976d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398623530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_c
sr_outstanding.398623530
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1009644010
Short name T790
Test name
Test status
Simulation time 150707341 ps
CPU time 2.43 seconds
Started Mar 17 02:00:53 PM PDT 24
Finished Mar 17 02:00:56 PM PDT 24
Peak memory 202236 kb
Host smart-93dd3f65-b19c-45bd-8354-17bae1f72ed6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1009644010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1009644010
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3665858384
Short name T195
Test name
Test status
Simulation time 53724359 ps
CPU time 0.88 seconds
Started Mar 17 02:00:54 PM PDT 24
Finished Mar 17 02:00:55 PM PDT 24
Peak memory 202088 kb
Host smart-4d78a69c-79e3-4703-bc6c-7c261c1ec504
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665858384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3665858384
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.808151610
Short name T60
Test name
Test status
Simulation time 25970430 ps
CPU time 0.66 seconds
Started Mar 17 02:00:56 PM PDT 24
Finished Mar 17 02:00:57 PM PDT 24
Peak memory 201980 kb
Host smart-2fd66457-ef4b-42fe-9440-4b249df42f27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=808151610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.808151610
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1176768699
Short name T766
Test name
Test status
Simulation time 101839343 ps
CPU time 1.67 seconds
Started Mar 17 02:00:57 PM PDT 24
Finished Mar 17 02:00:58 PM PDT 24
Peak memory 202324 kb
Host smart-c41fef1b-931d-4ea7-8b5b-fb382b83eca4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1176768699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1176768699
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1253304538
Short name T81
Test name
Test status
Simulation time 82822783 ps
CPU time 1.29 seconds
Started Mar 17 02:01:00 PM PDT 24
Finished Mar 17 02:01:01 PM PDT 24
Peak memory 210448 kb
Host smart-86018863-a899-42cd-820a-6c21f9e905f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253304538 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.1253304538
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3477562805
Short name T186
Test name
Test status
Simulation time 182982664 ps
CPU time 2.32 seconds
Started Mar 17 02:01:00 PM PDT 24
Finished Mar 17 02:01:03 PM PDT 24
Peak memory 202288 kb
Host smart-643971e0-64b2-4fa8-8d10-98c1f0f6da4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3477562805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3477562805
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.687200870
Short name T56
Test name
Test status
Simulation time 375497951 ps
CPU time 3.63 seconds
Started Mar 17 01:59:30 PM PDT 24
Finished Mar 17 01:59:34 PM PDT 24
Peak memory 202328 kb
Host smart-239f7f2a-40b9-4108-8813-910b3a4d186f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687200870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.687200870
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2119829381
Short name T58
Test name
Test status
Simulation time 55506073 ps
CPU time 0.89 seconds
Started Mar 17 01:59:30 PM PDT 24
Finished Mar 17 01:59:31 PM PDT 24
Peak memory 202104 kb
Host smart-cad9d540-7a91-47ba-ba21-44044cfaf1d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119829381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2119829381
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2548623136
Short name T236
Test name
Test status
Simulation time 81629940 ps
CPU time 1.2 seconds
Started Mar 17 01:59:36 PM PDT 24
Finished Mar 17 01:59:38 PM PDT 24
Peak memory 210420 kb
Host smart-89a0cf95-f695-4070-a384-ce0f0bb1850f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548623136 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.2548623136
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1943541427
Short name T776
Test name
Test status
Simulation time 173850473 ps
CPU time 2.37 seconds
Started Mar 17 01:59:30 PM PDT 24
Finished Mar 17 01:59:33 PM PDT 24
Peak memory 202280 kb
Host smart-7001c9e0-ee08-4ee4-a344-793da6232d8a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1943541427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1943541427
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3733348509
Short name T751
Test name
Test status
Simulation time 85593038 ps
CPU time 2.4 seconds
Started Mar 17 01:59:29 PM PDT 24
Finished Mar 17 01:59:32 PM PDT 24
Peak memory 202236 kb
Host smart-7ad921d0-60f4-4970-9ff5-4e3877bf53fc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3733348509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3733348509
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3026957822
Short name T66
Test name
Test status
Simulation time 23325683 ps
CPU time 0.66 seconds
Started Mar 17 02:01:02 PM PDT 24
Finished Mar 17 02:01:03 PM PDT 24
Peak memory 201984 kb
Host smart-0053f789-2748-4709-be12-bb1d33473592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3026957822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3026957822
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4163690305
Short name T788
Test name
Test status
Simulation time 25324377 ps
CPU time 0.61 seconds
Started Mar 17 02:01:13 PM PDT 24
Finished Mar 17 02:01:14 PM PDT 24
Peak memory 202036 kb
Host smart-f4278d48-bec6-4b23-b681-d551711ac7c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4163690305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.4163690305
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2642938981
Short name T61
Test name
Test status
Simulation time 23217550 ps
CPU time 0.71 seconds
Started Mar 17 02:01:13 PM PDT 24
Finished Mar 17 02:01:14 PM PDT 24
Peak memory 202032 kb
Host smart-6b2da266-4c90-44ad-92b2-fa8d6e2ededf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2642938981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2642938981
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.30718055
Short name T82
Test name
Test status
Simulation time 338533656 ps
CPU time 3.79 seconds
Started Mar 17 01:59:43 PM PDT 24
Finished Mar 17 01:59:47 PM PDT 24
Peak memory 202256 kb
Host smart-0381306f-1214-459a-9d3b-7ae578ab70fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30718055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.30718055
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2795423140
Short name T59
Test name
Test status
Simulation time 25740592 ps
CPU time 0.73 seconds
Started Mar 17 01:59:43 PM PDT 24
Finished Mar 17 01:59:44 PM PDT 24
Peak memory 202012 kb
Host smart-d5042afa-3acb-4682-891a-0a8f1589b274
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795423140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2795423140
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.432803654
Short name T46
Test name
Test status
Simulation time 58667684 ps
CPU time 1.81 seconds
Started Mar 17 01:59:49 PM PDT 24
Finished Mar 17 01:59:51 PM PDT 24
Peak memory 210472 kb
Host smart-d35cb29b-3cba-4056-a57c-945080a81a37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432803654 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.432803654
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.619437825
Short name T780
Test name
Test status
Simulation time 24263220 ps
CPU time 0.65 seconds
Started Mar 17 01:59:37 PM PDT 24
Finished Mar 17 01:59:38 PM PDT 24
Peak memory 202024 kb
Host smart-7851df9f-6980-45dd-bfef-5ea8dde35f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=619437825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.619437825
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2267737107
Short name T192
Test name
Test status
Simulation time 172596591 ps
CPU time 2.22 seconds
Started Mar 17 01:59:36 PM PDT 24
Finished Mar 17 01:59:39 PM PDT 24
Peak memory 202236 kb
Host smart-618ad566-6cfe-4917-b194-ab81a8b21d4b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2267737107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2267737107
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3187411300
Short name T752
Test name
Test status
Simulation time 248317954 ps
CPU time 2.58 seconds
Started Mar 17 01:59:39 PM PDT 24
Finished Mar 17 01:59:42 PM PDT 24
Peak memory 202220 kb
Host smart-c941036d-d3ab-4b3b-af33-f12fd77b5f20
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3187411300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3187411300
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.406970213
Short name T762
Test name
Test status
Simulation time 188960523 ps
CPU time 2.36 seconds
Started Mar 17 01:59:40 PM PDT 24
Finished Mar 17 01:59:42 PM PDT 24
Peak memory 202316 kb
Host smart-71929d9a-f28e-440d-97ee-42bde00838e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=406970213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.406970213
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2868523864
Short name T246
Test name
Test status
Simulation time 31673826 ps
CPU time 0.67 seconds
Started Mar 17 02:01:06 PM PDT 24
Finished Mar 17 02:01:07 PM PDT 24
Peak memory 202008 kb
Host smart-d5628e8a-cd2b-4d04-97f1-71fa00cad7fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2868523864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2868523864
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3275401941
Short name T769
Test name
Test status
Simulation time 21511135 ps
CPU time 0.65 seconds
Started Mar 17 02:01:07 PM PDT 24
Finished Mar 17 02:01:07 PM PDT 24
Peak memory 202028 kb
Host smart-f1f1f6b6-cab7-455a-a6e4-6c5023dee55d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3275401941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3275401941
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3048391281
Short name T65
Test name
Test status
Simulation time 22140794 ps
CPU time 0.64 seconds
Started Mar 17 02:01:20 PM PDT 24
Finished Mar 17 02:01:22 PM PDT 24
Peak memory 202044 kb
Host smart-62f68137-c17e-4edf-844e-1e3b925ee89b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3048391281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3048391281
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2005523832
Short name T767
Test name
Test status
Simulation time 23980357 ps
CPU time 0.65 seconds
Started Mar 17 02:01:13 PM PDT 24
Finished Mar 17 02:01:14 PM PDT 24
Peak memory 202008 kb
Host smart-8c9ead7f-a43c-40cd-8114-0dba36c035a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2005523832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2005523832
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3497870090
Short name T242
Test name
Test status
Simulation time 24131835 ps
CPU time 0.63 seconds
Started Mar 17 02:01:14 PM PDT 24
Finished Mar 17 02:01:14 PM PDT 24
Peak memory 202008 kb
Host smart-d40e7187-601b-4610-9a60-f642d9139bb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3497870090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3497870090
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3752980549
Short name T768
Test name
Test status
Simulation time 401152883 ps
CPU time 3.75 seconds
Started Mar 17 02:00:00 PM PDT 24
Finished Mar 17 02:00:05 PM PDT 24
Peak memory 202256 kb
Host smart-b03d1c71-b9fb-4d8b-b9a0-f5f6bc4c1e65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752980549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3752980549
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3482016751
Short name T191
Test name
Test status
Simulation time 358189372 ps
CPU time 8.92 seconds
Started Mar 17 01:59:55 PM PDT 24
Finished Mar 17 02:00:04 PM PDT 24
Peak memory 202264 kb
Host smart-454508db-d1cc-4ae7-8b24-4547c9c0d8be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482016751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3482016751
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1900341410
Short name T239
Test name
Test status
Simulation time 25730850 ps
CPU time 0.6 seconds
Started Mar 17 01:59:54 PM PDT 24
Finished Mar 17 01:59:55 PM PDT 24
Peak memory 201964 kb
Host smart-39c29365-cdad-422f-9acd-abab59a06c2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1900341410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1900341410
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.803036235
Short name T189
Test name
Test status
Simulation time 99612122 ps
CPU time 1.45 seconds
Started Mar 17 01:59:54 PM PDT 24
Finished Mar 17 01:59:56 PM PDT 24
Peak memory 202296 kb
Host smart-4fb9c885-dcdc-4be8-8d51-09d2c2d2be74
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=803036235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.803036235
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1796198144
Short name T791
Test name
Test status
Simulation time 470845358 ps
CPU time 4.1 seconds
Started Mar 17 01:59:56 PM PDT 24
Finished Mar 17 02:00:00 PM PDT 24
Peak memory 202220 kb
Host smart-588df100-e661-4b18-a5ff-73259aa0cc91
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1796198144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1796198144
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3102355238
Short name T756
Test name
Test status
Simulation time 166886344 ps
CPU time 2.35 seconds
Started Mar 17 01:59:49 PM PDT 24
Finished Mar 17 01:59:51 PM PDT 24
Peak memory 202356 kb
Host smart-dc6b5180-6ab9-4d13-9b6f-e968a0c98576
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3102355238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3102355238
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3918975252
Short name T793
Test name
Test status
Simulation time 24895817 ps
CPU time 0.65 seconds
Started Mar 17 02:01:13 PM PDT 24
Finished Mar 17 02:01:14 PM PDT 24
Peak memory 201992 kb
Host smart-f2c4da66-cd92-4d22-8717-f1811d6a7ba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3918975252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3918975252
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1117160979
Short name T241
Test name
Test status
Simulation time 19035089 ps
CPU time 0.68 seconds
Started Mar 17 02:01:21 PM PDT 24
Finished Mar 17 02:01:22 PM PDT 24
Peak memory 201952 kb
Host smart-36c64e5f-687f-4c8c-94b0-f0dcba8b951b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1117160979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1117160979
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3745593393
Short name T64
Test name
Test status
Simulation time 27394004 ps
CPU time 0.64 seconds
Started Mar 17 02:01:20 PM PDT 24
Finished Mar 17 02:01:22 PM PDT 24
Peak memory 201952 kb
Host smart-dbaac967-c6b9-4ac2-a64b-f76b6785c3f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3745593393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3745593393
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1946335533
Short name T63
Test name
Test status
Simulation time 19026583 ps
CPU time 0.61 seconds
Started Mar 17 02:01:21 PM PDT 24
Finished Mar 17 02:01:22 PM PDT 24
Peak memory 202000 kb
Host smart-53088f56-0a3a-4372-94de-688c0c1cf9e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1946335533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1946335533
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1926908059
Short name T786
Test name
Test status
Simulation time 20968313 ps
CPU time 0.66 seconds
Started Mar 17 02:01:21 PM PDT 24
Finished Mar 17 02:01:22 PM PDT 24
Peak memory 202008 kb
Host smart-09bd4efe-8977-43e0-9a98-ca25bb3bf764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1926908059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1926908059
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.4199158377
Short name T774
Test name
Test status
Simulation time 20209171 ps
CPU time 0.65 seconds
Started Mar 17 02:01:20 PM PDT 24
Finished Mar 17 02:01:21 PM PDT 24
Peak memory 202024 kb
Host smart-e80742f5-3aec-451b-944d-deab29ba6673
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4199158377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.4199158377
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2349568988
Short name T243
Test name
Test status
Simulation time 21624344 ps
CPU time 0.72 seconds
Started Mar 17 02:01:21 PM PDT 24
Finished Mar 17 02:01:22 PM PDT 24
Peak memory 201992 kb
Host smart-16e3688f-9888-45dc-947e-7ebb3db79a42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2349568988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2349568988
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1809484245
Short name T775
Test name
Test status
Simulation time 154964458 ps
CPU time 1.77 seconds
Started Mar 17 02:00:07 PM PDT 24
Finished Mar 17 02:00:09 PM PDT 24
Peak memory 210556 kb
Host smart-7fa18025-60b2-4bc1-9f01-958fee5a136c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809484245 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.1809484245
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.482868621
Short name T761
Test name
Test status
Simulation time 85089657 ps
CPU time 2.85 seconds
Started Mar 17 02:00:02 PM PDT 24
Finished Mar 17 02:00:06 PM PDT 24
Peak memory 202300 kb
Host smart-536e65f4-d415-4fcf-acd2-b4a52564266b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=482868621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.482868621
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1017279792
Short name T55
Test name
Test status
Simulation time 24694834 ps
CPU time 0.81 seconds
Started Mar 17 02:00:08 PM PDT 24
Finished Mar 17 02:00:09 PM PDT 24
Peak memory 202136 kb
Host smart-50a67850-d99a-4038-ad9d-7a6cd2cfb519
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017279792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1017279792
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1108561959
Short name T244
Test name
Test status
Simulation time 26518865 ps
CPU time 0.68 seconds
Started Mar 17 02:00:07 PM PDT 24
Finished Mar 17 02:00:08 PM PDT 24
Peak memory 202028 kb
Host smart-080bb549-3027-456d-ad44-a42bf2d927a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1108561959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1108561959
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3524962688
Short name T199
Test name
Test status
Simulation time 69648269 ps
CPU time 1.12 seconds
Started Mar 17 02:00:07 PM PDT 24
Finished Mar 17 02:00:08 PM PDT 24
Peak memory 202304 kb
Host smart-48ae1f1e-a7a0-43a5-a157-fea60ae2a6e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524962688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c
sr_outstanding.3524962688
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2000723733
Short name T185
Test name
Test status
Simulation time 245002220 ps
CPU time 2.61 seconds
Started Mar 17 02:00:08 PM PDT 24
Finished Mar 17 02:00:11 PM PDT 24
Peak memory 202340 kb
Host smart-13d39c97-879e-4b06-a804-af41e0ca45ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2000723733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2000723733
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.300723848
Short name T757
Test name
Test status
Simulation time 32401915 ps
CPU time 0.81 seconds
Started Mar 17 02:00:16 PM PDT 24
Finished Mar 17 02:00:17 PM PDT 24
Peak memory 202068 kb
Host smart-ec8bd9e7-6d72-47c9-af10-478498bd78f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300723848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.300723848
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1417533685
Short name T200
Test name
Test status
Simulation time 100088294 ps
CPU time 1.22 seconds
Started Mar 17 02:00:17 PM PDT 24
Finished Mar 17 02:00:19 PM PDT 24
Peak memory 202264 kb
Host smart-6df073e7-b7ea-4d17-b932-4e30b7070f47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417533685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c
sr_outstanding.1417533685
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1254552964
Short name T45
Test name
Test status
Simulation time 114408740 ps
CPU time 1.49 seconds
Started Mar 17 02:00:07 PM PDT 24
Finished Mar 17 02:00:09 PM PDT 24
Peak memory 202296 kb
Host smart-9df7afd5-8c8c-4ba7-b982-a11516219e44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1254552964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1254552964
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2249794844
Short name T787
Test name
Test status
Simulation time 47384441 ps
CPU time 1.71 seconds
Started Mar 17 02:00:22 PM PDT 24
Finished Mar 17 02:00:24 PM PDT 24
Peak memory 210560 kb
Host smart-73eb8317-a5f8-484d-a22b-a9ed14aca115
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249794844 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.2249794844
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1711164151
Short name T779
Test name
Test status
Simulation time 22585897 ps
CPU time 0.64 seconds
Started Mar 17 02:00:17 PM PDT 24
Finished Mar 17 02:00:17 PM PDT 24
Peak memory 201936 kb
Host smart-05cbfd69-80a0-45b9-98ca-f76d60ab05e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1711164151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1711164151
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2600351514
Short name T777
Test name
Test status
Simulation time 259151842 ps
CPU time 2.65 seconds
Started Mar 17 02:00:16 PM PDT 24
Finished Mar 17 02:00:19 PM PDT 24
Peak memory 202348 kb
Host smart-25376871-46ff-43c0-b87a-5c3a88519a4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2600351514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2600351514
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2993819575
Short name T781
Test name
Test status
Simulation time 21200328 ps
CPU time 0.63 seconds
Started Mar 17 02:00:23 PM PDT 24
Finished Mar 17 02:00:24 PM PDT 24
Peak memory 201964 kb
Host smart-da02c6b6-92e1-41d3-b4bd-2bf20f2f7825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2993819575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2993819575
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.908074459
Short name T771
Test name
Test status
Simulation time 34217074 ps
CPU time 1.02 seconds
Started Mar 17 02:00:23 PM PDT 24
Finished Mar 17 02:00:24 PM PDT 24
Peak memory 201820 kb
Host smart-109e9195-c7c4-4164-a3f5-e680533a8f6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908074459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_cs
r_outstanding.908074459
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3458068128
Short name T763
Test name
Test status
Simulation time 207770167 ps
CPU time 2.87 seconds
Started Mar 17 02:00:21 PM PDT 24
Finished Mar 17 02:00:24 PM PDT 24
Peak memory 202260 kb
Host smart-7bb947f1-0ee3-4165-ae9b-7d54cf4f9036
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3458068128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3458068128
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.4254259278
Short name T589
Test name
Test status
Simulation time 8368596054 ps
CPU time 7.75 seconds
Started Mar 17 01:37:42 PM PDT 24
Finished Mar 17 01:37:49 PM PDT 24
Peak memory 203748 kb
Host smart-3b528e46-13e0-440c-81a0-65f1805fc388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42542
59278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.4254259278
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2656059868
Short name T44
Test name
Test status
Simulation time 125441587 ps
CPU time 1.3 seconds
Started Mar 17 01:37:36 PM PDT 24
Finished Mar 17 01:37:37 PM PDT 24
Peak memory 203780 kb
Host smart-7dcadb8a-54dd-47e6-9068-8a450f2f9506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26560
59868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2656059868
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.767107359
Short name T642
Test name
Test status
Simulation time 8361385836 ps
CPU time 7.7 seconds
Started Mar 17 01:37:48 PM PDT 24
Finished Mar 17 01:37:57 PM PDT 24
Peak memory 203480 kb
Host smart-a5376abc-a446-4048-8a09-62cc790a2d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76710
7359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.767107359
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2765084306
Short name T463
Test name
Test status
Simulation time 8449864787 ps
CPU time 7.32 seconds
Started Mar 17 01:37:44 PM PDT 24
Finished Mar 17 01:37:52 PM PDT 24
Peak memory 203716 kb
Host smart-024985bc-6b33-4bea-907f-e5c9d056036b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27650
84306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2765084306
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2776034856
Short name T461
Test name
Test status
Simulation time 8409395536 ps
CPU time 7.95 seconds
Started Mar 17 01:37:41 PM PDT 24
Finished Mar 17 01:37:49 PM PDT 24
Peak memory 203664 kb
Host smart-adbda8a8-0989-4b76-ad75-eee417031575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27760
34856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2776034856
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2360872101
Short name T3
Test name
Test status
Simulation time 8365057462 ps
CPU time 6.87 seconds
Started Mar 17 01:37:42 PM PDT 24
Finished Mar 17 01:37:49 PM PDT 24
Peak memory 203680 kb
Host smart-0da444f5-830c-423e-8045-fe5c62edd4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23608
72101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2360872101
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1867182205
Short name T354
Test name
Test status
Simulation time 8398718305 ps
CPU time 7.22 seconds
Started Mar 17 01:37:42 PM PDT 24
Finished Mar 17 01:37:49 PM PDT 24
Peak memory 203688 kb
Host smart-5e9f925a-ce30-4c14-afd4-9e90da4fe962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18671
82205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1867182205
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3219960601
Short name T471
Test name
Test status
Simulation time 23558788 ps
CPU time 0.61 seconds
Started Mar 17 01:37:48 PM PDT 24
Finished Mar 17 01:37:50 PM PDT 24
Peak memory 203192 kb
Host smart-44056f67-c277-45d8-82de-ecf262132fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32199
60601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3219960601
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.3899170158
Short name T692
Test name
Test status
Simulation time 8395729898 ps
CPU time 8.64 seconds
Started Mar 17 01:37:44 PM PDT 24
Finished Mar 17 01:37:53 PM PDT 24
Peak memory 203688 kb
Host smart-dc88a8d9-c3ac-4961-98c1-b7bb8f70dc90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38991
70158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3899170158
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.615912367
Short name T219
Test name
Test status
Simulation time 8377493942 ps
CPU time 7.71 seconds
Started Mar 17 01:37:49 PM PDT 24
Finished Mar 17 01:37:58 PM PDT 24
Peak memory 203684 kb
Host smart-2cc9fb67-f15f-418f-bcf8-4c1763d501f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61591
2367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.615912367
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2198611702
Short name T50
Test name
Test status
Simulation time 195598924 ps
CPU time 1.06 seconds
Started Mar 17 01:37:49 PM PDT 24
Finished Mar 17 01:37:51 PM PDT 24
Peak memory 219920 kb
Host smart-e0a422c4-76e0-4ff3-910a-327de8f59f9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2198611702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2198611702
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2751474781
Short name T489
Test name
Test status
Simulation time 8367226601 ps
CPU time 7.28 seconds
Started Mar 17 01:37:48 PM PDT 24
Finished Mar 17 01:37:57 PM PDT 24
Peak memory 203692 kb
Host smart-e6df0f88-babe-4516-a289-da5ce8adfa0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27514
74781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2751474781
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.272890397
Short name T266
Test name
Test status
Simulation time 270899838 ps
CPU time 2.15 seconds
Started Mar 17 01:37:55 PM PDT 24
Finished Mar 17 01:37:58 PM PDT 24
Peak memory 203688 kb
Host smart-ce8f1fbf-bff3-4c6b-afce-071317790ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27289
0397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.272890397
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.2178127100
Short name T171
Test name
Test status
Simulation time 8364078106 ps
CPU time 7.43 seconds
Started Mar 17 01:38:03 PM PDT 24
Finished Mar 17 01:38:10 PM PDT 24
Peak memory 203496 kb
Host smart-74882b37-d222-4198-a527-e47af788761d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21781
27100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.2178127100
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.3398633494
Short name T397
Test name
Test status
Simulation time 8454777742 ps
CPU time 7.01 seconds
Started Mar 17 01:37:54 PM PDT 24
Finished Mar 17 01:38:02 PM PDT 24
Peak memory 203692 kb
Host smart-e09041ee-5674-43be-aa72-d89f292ebe1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33986
33494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.3398633494
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.754720237
Short name T264
Test name
Test status
Simulation time 8410759803 ps
CPU time 7.27 seconds
Started Mar 17 01:37:54 PM PDT 24
Finished Mar 17 01:38:03 PM PDT 24
Peak memory 203600 kb
Host smart-d4cff26d-7179-4114-8df5-1ef43006c46d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75472
0237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.754720237
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.771624361
Short name T334
Test name
Test status
Simulation time 8364141147 ps
CPU time 7.5 seconds
Started Mar 17 01:37:57 PM PDT 24
Finished Mar 17 01:38:05 PM PDT 24
Peak memory 203680 kb
Host smart-bf1c54ed-0c15-4a94-b265-935c9f28277c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77162
4361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.771624361
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.149890061
Short name T602
Test name
Test status
Simulation time 8391234280 ps
CPU time 7.16 seconds
Started Mar 17 01:37:56 PM PDT 24
Finished Mar 17 01:38:04 PM PDT 24
Peak memory 203536 kb
Host smart-ba8ecb6f-49bc-4c8d-a6a0-ce8eafdc942c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14989
0061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.149890061
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.4011008569
Short name T232
Test name
Test status
Simulation time 8382622664 ps
CPU time 7.69 seconds
Started Mar 17 01:37:54 PM PDT 24
Finished Mar 17 01:38:03 PM PDT 24
Peak memory 203640 kb
Host smart-fdfe3f9c-9300-4ea8-bce3-0034c719cef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40110
08569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.4011008569
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1297450730
Short name T627
Test name
Test status
Simulation time 37817172 ps
CPU time 0.61 seconds
Started Mar 17 01:38:01 PM PDT 24
Finished Mar 17 01:38:03 PM PDT 24
Peak memory 203368 kb
Host smart-5012002f-b519-4e7e-bdb3-4653608b0555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12974
50730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1297450730
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.2540987963
Short name T267
Test name
Test status
Simulation time 8372065655 ps
CPU time 9.13 seconds
Started Mar 17 01:38:02 PM PDT 24
Finished Mar 17 01:38:12 PM PDT 24
Peak memory 203672 kb
Host smart-ed51ce8e-9290-42b9-af2d-c018eb69c791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25409
87963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.2540987963
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.648853838
Short name T67
Test name
Test status
Simulation time 111032091 ps
CPU time 0.9 seconds
Started Mar 17 01:38:03 PM PDT 24
Finished Mar 17 01:38:04 PM PDT 24
Peak memory 218792 kb
Host smart-1fd3448e-0257-4abd-bf77-c9d5b8558724
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=648853838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.648853838
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.2466664541
Short name T712
Test name
Test status
Simulation time 8359329686 ps
CPU time 7.79 seconds
Started Mar 17 01:38:02 PM PDT 24
Finished Mar 17 01:38:10 PM PDT 24
Peak memory 203608 kb
Host smart-d80f7142-4e96-4d57-b4e6-ec413f5fea61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24666
64541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.2466664541
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3278270491
Short name T320
Test name
Test status
Simulation time 8364659440 ps
CPU time 8.5 seconds
Started Mar 17 01:39:17 PM PDT 24
Finished Mar 17 01:39:26 PM PDT 24
Peak memory 203652 kb
Host smart-391e54f1-3548-4331-a54c-06b19bc4fd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32782
70491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3278270491
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.1356736411
Short name T701
Test name
Test status
Simulation time 144252749 ps
CPU time 1.39 seconds
Started Mar 17 01:39:18 PM PDT 24
Finished Mar 17 01:39:20 PM PDT 24
Peak memory 203760 kb
Host smart-716f66e1-c3db-4dd4-9127-fb6017408b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13567
36411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.1356736411
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3267430316
Short name T532
Test name
Test status
Simulation time 8356433813 ps
CPU time 8.6 seconds
Started Mar 17 01:39:25 PM PDT 24
Finished Mar 17 01:39:34 PM PDT 24
Peak memory 203508 kb
Host smart-cd992c10-2ba1-4fd6-8cc1-9402d9dec140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32674
30316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3267430316
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3467965677
Short name T538
Test name
Test status
Simulation time 8425259763 ps
CPU time 8.11 seconds
Started Mar 17 01:39:17 PM PDT 24
Finished Mar 17 01:39:25 PM PDT 24
Peak memory 203676 kb
Host smart-d123fc98-4a3b-41c4-b526-74b70c1dba1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34679
65677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3467965677
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3691461965
Short name T356
Test name
Test status
Simulation time 8405945592 ps
CPU time 9.46 seconds
Started Mar 17 01:39:17 PM PDT 24
Finished Mar 17 01:39:27 PM PDT 24
Peak memory 203716 kb
Host smart-c749d743-f869-4e82-9e1f-128d37e990ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36914
61965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3691461965
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1107225597
Short name T292
Test name
Test status
Simulation time 8368353959 ps
CPU time 8.98 seconds
Started Mar 17 01:39:16 PM PDT 24
Finished Mar 17 01:39:25 PM PDT 24
Peak memory 203696 kb
Host smart-66114ec5-323d-4722-81a4-1aa4dd9db482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11072
25597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1107225597
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2209523911
Short name T716
Test name
Test status
Simulation time 8400551911 ps
CPU time 8.73 seconds
Started Mar 17 01:39:17 PM PDT 24
Finished Mar 17 01:39:26 PM PDT 24
Peak memory 203704 kb
Host smart-6ac8c0d8-b564-4e3b-bb78-2aedde57f0c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22095
23911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2209523911
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.110954433
Short name T350
Test name
Test status
Simulation time 8381767951 ps
CPU time 8.94 seconds
Started Mar 17 01:39:19 PM PDT 24
Finished Mar 17 01:39:29 PM PDT 24
Peak memory 203692 kb
Host smart-0390792d-b524-4965-a257-bfbac49136b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11095
4433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.110954433
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2976838544
Short name T413
Test name
Test status
Simulation time 24168738 ps
CPU time 0.64 seconds
Started Mar 17 01:39:25 PM PDT 24
Finished Mar 17 01:39:27 PM PDT 24
Peak memory 203152 kb
Host smart-c3cd72c7-a801-4677-87ef-aac8dc38f283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29768
38544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2976838544
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.153112935
Short name T525
Test name
Test status
Simulation time 8380821129 ps
CPU time 7.59 seconds
Started Mar 17 01:39:16 PM PDT 24
Finished Mar 17 01:39:24 PM PDT 24
Peak memory 203692 kb
Host smart-707f2444-eea9-4040-b0a1-029042ca7e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15311
2935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.153112935
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.2692151416
Short name T418
Test name
Test status
Simulation time 8363305603 ps
CPU time 8.1 seconds
Started Mar 17 01:39:27 PM PDT 24
Finished Mar 17 01:39:36 PM PDT 24
Peak memory 203536 kb
Host smart-f2bed2e9-0cc8-4cac-b6ef-e8d2c9dccf6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26921
51416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.2692151416
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.4253840162
Short name T512
Test name
Test status
Simulation time 8372127099 ps
CPU time 7.19 seconds
Started Mar 17 01:39:26 PM PDT 24
Finished Mar 17 01:39:34 PM PDT 24
Peak memory 203700 kb
Host smart-e596e7c1-22a6-4920-b423-d4b185aeda3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42538
40162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.4253840162
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.147352966
Short name T78
Test name
Test status
Simulation time 64003902 ps
CPU time 1.73 seconds
Started Mar 17 01:39:23 PM PDT 24
Finished Mar 17 01:39:26 PM PDT 24
Peak memory 203672 kb
Host smart-bb891b90-1361-4b0d-84c1-ba69b407e42f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14735
2966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.147352966
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3616327515
Short name T155
Test name
Test status
Simulation time 8356457024 ps
CPU time 6.94 seconds
Started Mar 17 01:39:31 PM PDT 24
Finished Mar 17 01:39:38 PM PDT 24
Peak memory 203548 kb
Host smart-a609ee80-09ef-4f60-ae87-c5a942c9cd8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36163
27515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3616327515
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.776897018
Short name T484
Test name
Test status
Simulation time 8407240028 ps
CPU time 9.06 seconds
Started Mar 17 01:39:24 PM PDT 24
Finished Mar 17 01:39:35 PM PDT 24
Peak memory 203736 kb
Host smart-b796af35-7730-453b-9094-bee2f3061229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77689
7018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.776897018
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2120808090
Short name T448
Test name
Test status
Simulation time 8361691496 ps
CPU time 7.38 seconds
Started Mar 17 01:39:24 PM PDT 24
Finished Mar 17 01:39:33 PM PDT 24
Peak memory 203828 kb
Host smart-4918d5a4-88fc-4677-8d86-150929b1a090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21208
08090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2120808090
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2259725002
Short name T610
Test name
Test status
Simulation time 8394989996 ps
CPU time 8.12 seconds
Started Mar 17 01:39:23 PM PDT 24
Finished Mar 17 01:39:33 PM PDT 24
Peak memory 203720 kb
Host smart-5c4e49b8-6791-4fa2-b64c-0047732f78d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22597
25002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2259725002
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1018747649
Short name T265
Test name
Test status
Simulation time 8399163751 ps
CPU time 8.66 seconds
Started Mar 17 01:39:27 PM PDT 24
Finished Mar 17 01:39:37 PM PDT 24
Peak memory 203548 kb
Host smart-6a38180b-2261-4aec-a03d-adcba5427a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10187
47649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1018747649
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3050338647
Short name T516
Test name
Test status
Simulation time 30029183 ps
CPU time 0.64 seconds
Started Mar 17 01:39:29 PM PDT 24
Finished Mar 17 01:39:30 PM PDT 24
Peak memory 203272 kb
Host smart-76d4c2d2-82bf-4d4a-b74d-3ce25038dac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30503
38647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3050338647
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.648161566
Short name T725
Test name
Test status
Simulation time 8407202472 ps
CPU time 7.98 seconds
Started Mar 17 01:39:30 PM PDT 24
Finished Mar 17 01:39:38 PM PDT 24
Peak memory 203680 kb
Host smart-73ff695c-a386-43de-be32-d8e791346720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64816
1566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.648161566
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.2147533173
Short name T328
Test name
Test status
Simulation time 8360108327 ps
CPU time 7.1 seconds
Started Mar 17 01:39:31 PM PDT 24
Finished Mar 17 01:39:39 PM PDT 24
Peak memory 203668 kb
Host smart-e0368df9-2ad3-475e-b222-1d568671e1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21475
33173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.2147533173
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2887442838
Short name T360
Test name
Test status
Simulation time 8360292361 ps
CPU time 9.88 seconds
Started Mar 17 01:39:30 PM PDT 24
Finished Mar 17 01:39:41 PM PDT 24
Peak memory 203692 kb
Host smart-88b2aa9c-5c61-4a1c-9c63-b69fefcbd7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28874
42838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2887442838
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1605260469
Short name T492
Test name
Test status
Simulation time 8370279005 ps
CPU time 8.28 seconds
Started Mar 17 01:39:28 PM PDT 24
Finished Mar 17 01:39:36 PM PDT 24
Peak memory 203668 kb
Host smart-85291d16-b720-4593-9e8d-5a887c8ef531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16052
60469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1605260469
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1406374092
Short name T218
Test name
Test status
Simulation time 171801179 ps
CPU time 1.74 seconds
Started Mar 17 01:39:31 PM PDT 24
Finished Mar 17 01:39:33 PM PDT 24
Peak memory 203720 kb
Host smart-638d07b0-89aa-435f-922e-50932ef00425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14063
74092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1406374092
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.130303825
Short name T21
Test name
Test status
Simulation time 8356867834 ps
CPU time 7.3 seconds
Started Mar 17 01:39:35 PM PDT 24
Finished Mar 17 01:39:42 PM PDT 24
Peak memory 203532 kb
Host smart-c04d3d90-27cf-43e7-87b9-89e6c76c1604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13030
3825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.130303825
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2419499012
Short name T726
Test name
Test status
Simulation time 8448622476 ps
CPU time 8.17 seconds
Started Mar 17 01:39:30 PM PDT 24
Finished Mar 17 01:39:38 PM PDT 24
Peak memory 203712 kb
Host smart-48967c25-04ec-451a-8476-23fd97cb2b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24194
99012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2419499012
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.2195422621
Short name T524
Test name
Test status
Simulation time 8405286463 ps
CPU time 7.68 seconds
Started Mar 17 01:39:30 PM PDT 24
Finished Mar 17 01:39:38 PM PDT 24
Peak memory 203692 kb
Host smart-4d7d97bd-d77d-4f74-bde7-0e7c408e5d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21954
22621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.2195422621
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2652463398
Short name T392
Test name
Test status
Simulation time 8360083298 ps
CPU time 6.97 seconds
Started Mar 17 01:39:34 PM PDT 24
Finished Mar 17 01:39:42 PM PDT 24
Peak memory 203692 kb
Host smart-3e092bb5-b44f-40f4-a41c-712412af5312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26524
63398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2652463398
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1854289189
Short name T601
Test name
Test status
Simulation time 8390948161 ps
CPU time 7.28 seconds
Started Mar 17 01:39:35 PM PDT 24
Finished Mar 17 01:39:43 PM PDT 24
Peak memory 203696 kb
Host smart-212e1b12-6447-4a7a-b519-76517c0d0d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18542
89189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1854289189
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.42278132
Short name T287
Test name
Test status
Simulation time 8383594148 ps
CPU time 8.11 seconds
Started Mar 17 01:39:35 PM PDT 24
Finished Mar 17 01:39:43 PM PDT 24
Peak memory 203716 kb
Host smart-cb2c5071-bdfd-419a-9a1c-fce414df75f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42278
132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.42278132
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.563956203
Short name T719
Test name
Test status
Simulation time 25289482 ps
CPU time 0.63 seconds
Started Mar 17 01:39:35 PM PDT 24
Finished Mar 17 01:39:35 PM PDT 24
Peak memory 203136 kb
Host smart-33008938-05c1-4eee-a384-ebfffb33a8d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56395
6203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.563956203
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2337651705
Short name T277
Test name
Test status
Simulation time 8385405182 ps
CPU time 7.35 seconds
Started Mar 17 01:39:35 PM PDT 24
Finished Mar 17 01:39:42 PM PDT 24
Peak memory 203700 kb
Host smart-e8a188d5-7aad-4526-873a-c854550d1b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23376
51705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2337651705
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.1913236950
Short name T260
Test name
Test status
Simulation time 8379139391 ps
CPU time 7.57 seconds
Started Mar 17 01:39:34 PM PDT 24
Finished Mar 17 01:39:42 PM PDT 24
Peak memory 203732 kb
Host smart-41408f8d-136c-4b1b-9558-91de77bf9ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19132
36950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.1913236950
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3533786358
Short name T431
Test name
Test status
Simulation time 8361488934 ps
CPU time 7.76 seconds
Started Mar 17 01:39:35 PM PDT 24
Finished Mar 17 01:39:43 PM PDT 24
Peak memory 203564 kb
Host smart-6df15a3a-4813-432d-91dd-7e9eba869d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35337
86358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3533786358
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3876799231
Short name T32
Test name
Test status
Simulation time 8371190566 ps
CPU time 8.39 seconds
Started Mar 17 01:39:36 PM PDT 24
Finished Mar 17 01:39:45 PM PDT 24
Peak memory 203700 kb
Host smart-2015a367-8e5e-4c21-a81d-9e1f5ac8900c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38767
99231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3876799231
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.644668809
Short name T662
Test name
Test status
Simulation time 46611866 ps
CPU time 1.11 seconds
Started Mar 17 01:39:40 PM PDT 24
Finished Mar 17 01:39:42 PM PDT 24
Peak memory 203428 kb
Host smart-0a14ce03-c513-4c3e-bf26-64f88b41939f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64466
8809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.644668809
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.1313385144
Short name T357
Test name
Test status
Simulation time 8364083771 ps
CPU time 7.45 seconds
Started Mar 17 01:39:46 PM PDT 24
Finished Mar 17 01:39:53 PM PDT 24
Peak memory 203524 kb
Host smart-a0282993-ddc3-4104-8daa-64658c172a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13133
85144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.1313385144
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1732916044
Short name T603
Test name
Test status
Simulation time 8403778585 ps
CPU time 7.4 seconds
Started Mar 17 01:39:41 PM PDT 24
Finished Mar 17 01:39:49 PM PDT 24
Peak memory 203716 kb
Host smart-4526877c-0521-46f3-beda-7d26793f0acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17329
16044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1732916044
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1652879639
Short name T268
Test name
Test status
Simulation time 8404467083 ps
CPU time 7.31 seconds
Started Mar 17 01:39:42 PM PDT 24
Finished Mar 17 01:39:50 PM PDT 24
Peak memory 203756 kb
Host smart-b0459dc4-2a9e-4ca1-adf5-f6d79caf1e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16528
79639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1652879639
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2606333389
Short name T215
Test name
Test status
Simulation time 8362782575 ps
CPU time 7.99 seconds
Started Mar 17 01:39:46 PM PDT 24
Finished Mar 17 01:39:54 PM PDT 24
Peak memory 203724 kb
Host smart-49c12620-5016-480c-831c-6e044118f95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26063
33389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2606333389
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3438589473
Short name T86
Test name
Test status
Simulation time 8428214900 ps
CPU time 8.79 seconds
Started Mar 17 01:39:42 PM PDT 24
Finished Mar 17 01:39:51 PM PDT 24
Peak memory 203600 kb
Host smart-e7ea4697-0ff6-47de-a090-f4986bf55b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34385
89473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3438589473
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.2363561772
Short name T228
Test name
Test status
Simulation time 8405902603 ps
CPU time 8.08 seconds
Started Mar 17 01:39:41 PM PDT 24
Finished Mar 17 01:39:50 PM PDT 24
Peak memory 203696 kb
Host smart-b37431e9-161a-47dd-87d3-4e8f58f6b7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23635
61772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.2363561772
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1834100658
Short name T284
Test name
Test status
Simulation time 8384298039 ps
CPU time 7.62 seconds
Started Mar 17 01:39:42 PM PDT 24
Finished Mar 17 01:39:50 PM PDT 24
Peak memory 203584 kb
Host smart-a434216e-777b-4330-b1f6-49e1210af905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18341
00658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1834100658
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3832174395
Short name T20
Test name
Test status
Simulation time 8434282152 ps
CPU time 9.66 seconds
Started Mar 17 01:39:46 PM PDT 24
Finished Mar 17 01:39:56 PM PDT 24
Peak memory 203728 kb
Host smart-4f7c114b-85de-44c9-bbb1-d69d9ceb2eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38321
74395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3832174395
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.2990611815
Short name T441
Test name
Test status
Simulation time 8393717049 ps
CPU time 7.54 seconds
Started Mar 17 01:39:43 PM PDT 24
Finished Mar 17 01:39:51 PM PDT 24
Peak memory 203720 kb
Host smart-35e46471-bb5b-45b6-9324-c3f71177ca78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29906
11815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.2990611815
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1204371113
Short name T250
Test name
Test status
Simulation time 8360068742 ps
CPU time 7.74 seconds
Started Mar 17 01:39:46 PM PDT 24
Finished Mar 17 01:39:54 PM PDT 24
Peak memory 203568 kb
Host smart-bee3c503-e62e-43cb-9614-d655dd642aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12043
71113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1204371113
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.2547437217
Short name T36
Test name
Test status
Simulation time 8479820518 ps
CPU time 8.49 seconds
Started Mar 17 01:39:37 PM PDT 24
Finished Mar 17 01:39:46 PM PDT 24
Peak memory 203768 kb
Host smart-d1cf1087-9b03-423d-abb6-633db72ad3b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25474
37217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2547437217
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.1058075138
Short name T519
Test name
Test status
Simulation time 8372854446 ps
CPU time 7.74 seconds
Started Mar 17 01:39:48 PM PDT 24
Finished Mar 17 01:39:56 PM PDT 24
Peak memory 203676 kb
Host smart-27be34b2-9a9a-434d-a40a-e95d513e47f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10580
75138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.1058075138
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.4247172749
Short name T79
Test name
Test status
Simulation time 298205534 ps
CPU time 2.22 seconds
Started Mar 17 01:39:52 PM PDT 24
Finished Mar 17 01:39:55 PM PDT 24
Peak memory 203484 kb
Host smart-32ade6a6-5b50-49c5-91c2-650a0c97089e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42471
72749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.4247172749
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.662265169
Short name T694
Test name
Test status
Simulation time 8437445904 ps
CPU time 7.88 seconds
Started Mar 17 01:39:52 PM PDT 24
Finished Mar 17 01:40:00 PM PDT 24
Peak memory 203604 kb
Host smart-fcae21c8-7e47-4e8a-9911-943a2f6e5c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66226
5169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.662265169
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.3687634335
Short name T727
Test name
Test status
Simulation time 8412296743 ps
CPU time 7.77 seconds
Started Mar 17 01:39:53 PM PDT 24
Finished Mar 17 01:40:01 PM PDT 24
Peak memory 203680 kb
Host smart-02395cbb-b1a6-4fe2-ad45-8d30d7d70ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36876
34335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.3687634335
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2421947974
Short name T263
Test name
Test status
Simulation time 8360703845 ps
CPU time 7.18 seconds
Started Mar 17 01:39:52 PM PDT 24
Finished Mar 17 01:39:59 PM PDT 24
Peak memory 203648 kb
Host smart-98545c8c-f515-4378-b898-ade4e396bd61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24219
47974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2421947974
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3532302221
Short name T452
Test name
Test status
Simulation time 8383528832 ps
CPU time 9.69 seconds
Started Mar 17 01:39:59 PM PDT 24
Finished Mar 17 01:40:08 PM PDT 24
Peak memory 203528 kb
Host smart-2e6e8500-a079-4a37-8fa6-03c802614646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35323
02221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3532302221
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3685443678
Short name T680
Test name
Test status
Simulation time 8404306175 ps
CPU time 7.04 seconds
Started Mar 17 01:39:57 PM PDT 24
Finished Mar 17 01:40:04 PM PDT 24
Peak memory 203500 kb
Host smart-29b63a19-d126-4015-a93c-b0f3f5c852fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36854
43678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3685443678
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2958620578
Short name T288
Test name
Test status
Simulation time 8411364884 ps
CPU time 7.65 seconds
Started Mar 17 01:39:59 PM PDT 24
Finished Mar 17 01:40:07 PM PDT 24
Peak memory 203712 kb
Host smart-0eb833fe-e471-4935-93ea-2d4f021d6701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29586
20578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2958620578
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.2934567834
Short name T541
Test name
Test status
Simulation time 8393589599 ps
CPU time 7.77 seconds
Started Mar 17 01:40:00 PM PDT 24
Finished Mar 17 01:40:08 PM PDT 24
Peak memory 203696 kb
Host smart-f67dc0d8-0f42-4021-82ee-fdef87041356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29345
67834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.2934567834
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2464774467
Short name T508
Test name
Test status
Simulation time 8359786861 ps
CPU time 7.21 seconds
Started Mar 17 01:39:59 PM PDT 24
Finished Mar 17 01:40:06 PM PDT 24
Peak memory 203536 kb
Host smart-b589e3fe-a8f0-4d39-bbc3-59e1fbb66271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24647
74467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2464774467
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.864109236
Short name T137
Test name
Test status
Simulation time 8471312813 ps
CPU time 8.21 seconds
Started Mar 17 01:39:46 PM PDT 24
Finished Mar 17 01:39:54 PM PDT 24
Peak memory 203672 kb
Host smart-54f71384-076d-474f-bc76-09631b4212d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86410
9236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.864109236
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1723769303
Short name T528
Test name
Test status
Simulation time 8367551673 ps
CPU time 7.73 seconds
Started Mar 17 01:40:04 PM PDT 24
Finished Mar 17 01:40:11 PM PDT 24
Peak memory 203704 kb
Host smart-7e9f4758-8e8c-422c-90cc-692af30d8dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17237
69303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1723769303
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2587069074
Short name T206
Test name
Test status
Simulation time 54895678 ps
CPU time 1.55 seconds
Started Mar 17 01:40:05 PM PDT 24
Finished Mar 17 01:40:07 PM PDT 24
Peak memory 203808 kb
Host smart-d078fa32-39dd-47d2-8fb0-cff5ed46857b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25870
69074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2587069074
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2747966609
Short name T166
Test name
Test status
Simulation time 8355517092 ps
CPU time 7.45 seconds
Started Mar 17 01:40:12 PM PDT 24
Finished Mar 17 01:40:19 PM PDT 24
Peak memory 203516 kb
Host smart-346e458e-623c-4450-a94b-30d75e68c150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27479
66609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2747966609
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2591778085
Short name T374
Test name
Test status
Simulation time 8415886385 ps
CPU time 7.2 seconds
Started Mar 17 01:40:05 PM PDT 24
Finished Mar 17 01:40:12 PM PDT 24
Peak memory 203700 kb
Host smart-6c350098-e64d-4097-9b4f-548ed284b26c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25917
78085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2591778085
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3216788335
Short name T493
Test name
Test status
Simulation time 8403215215 ps
CPU time 7.47 seconds
Started Mar 17 01:40:05 PM PDT 24
Finished Mar 17 01:40:13 PM PDT 24
Peak memory 203700 kb
Host smart-71ed54c4-0a97-4061-b009-63a07cba8daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32167
88335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3216788335
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3382626705
Short name T385
Test name
Test status
Simulation time 8360158734 ps
CPU time 7.86 seconds
Started Mar 17 01:40:04 PM PDT 24
Finished Mar 17 01:40:12 PM PDT 24
Peak memory 203644 kb
Host smart-d97fe522-4774-4f28-8db4-eeb6a9fa124f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33826
26705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3382626705
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1681379548
Short name T314
Test name
Test status
Simulation time 8376817175 ps
CPU time 7.01 seconds
Started Mar 17 01:40:03 PM PDT 24
Finished Mar 17 01:40:10 PM PDT 24
Peak memory 203544 kb
Host smart-95cdb2d3-f422-4c5a-8eba-1c5e663d6386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16813
79548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1681379548
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3522814726
Short name T332
Test name
Test status
Simulation time 8374918380 ps
CPU time 8.54 seconds
Started Mar 17 01:40:03 PM PDT 24
Finished Mar 17 01:40:12 PM PDT 24
Peak memory 203656 kb
Host smart-fcb43e86-cfb5-4256-a9d0-d94c6627527d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35228
14726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3522814726
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3932977472
Short name T376
Test name
Test status
Simulation time 24862788 ps
CPU time 0.62 seconds
Started Mar 17 01:40:09 PM PDT 24
Finished Mar 17 01:40:10 PM PDT 24
Peak memory 203144 kb
Host smart-d8c59735-ec73-4c35-8c18-49ea5f2ca172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39329
77472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3932977472
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3049146219
Short name T674
Test name
Test status
Simulation time 8372812847 ps
CPU time 7.26 seconds
Started Mar 17 01:40:04 PM PDT 24
Finished Mar 17 01:40:12 PM PDT 24
Peak memory 203712 kb
Host smart-5dcbe3eb-716f-4221-9f21-5335ce2c12dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30491
46219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3049146219
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.1196423098
Short name T604
Test name
Test status
Simulation time 8373475874 ps
CPU time 7.76 seconds
Started Mar 17 01:40:08 PM PDT 24
Finished Mar 17 01:40:16 PM PDT 24
Peak memory 203648 kb
Host smart-767e93a5-60c3-4678-92c5-bf18af39dc76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11964
23098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.1196423098
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.845732120
Short name T632
Test name
Test status
Simulation time 8354629391 ps
CPU time 7.06 seconds
Started Mar 17 01:40:10 PM PDT 24
Finished Mar 17 01:40:18 PM PDT 24
Peak memory 203564 kb
Host smart-82706ec7-8b6d-450f-9235-c0b0e753018a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84573
2120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.845732120
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2508634700
Short name T703
Test name
Test status
Simulation time 8372969415 ps
CPU time 7.99 seconds
Started Mar 17 01:40:16 PM PDT 24
Finished Mar 17 01:40:24 PM PDT 24
Peak memory 203664 kb
Host smart-2b540f5d-e942-437e-b2a3-7551a6c1f96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25086
34700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2508634700
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3884993683
Short name T248
Test name
Test status
Simulation time 66859521 ps
CPU time 1.98 seconds
Started Mar 17 01:40:19 PM PDT 24
Finished Mar 17 01:40:21 PM PDT 24
Peak memory 203680 kb
Host smart-cb636b2d-7795-428a-b506-566fedfb4c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38849
93683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3884993683
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.466838021
Short name T178
Test name
Test status
Simulation time 8360754565 ps
CPU time 8.9 seconds
Started Mar 17 01:40:20 PM PDT 24
Finished Mar 17 01:40:30 PM PDT 24
Peak memory 203488 kb
Host smart-5310f40e-56b3-418d-b0a6-833677140f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46683
8021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.466838021
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.976895310
Short name T115
Test name
Test status
Simulation time 8377949854 ps
CPU time 7.27 seconds
Started Mar 17 01:40:20 PM PDT 24
Finished Mar 17 01:40:27 PM PDT 24
Peak memory 203664 kb
Host smart-73936017-2343-4074-8aa5-776703599266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97689
5310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.976895310
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.4170349293
Short name T676
Test name
Test status
Simulation time 8408467343 ps
CPU time 7.29 seconds
Started Mar 17 01:40:16 PM PDT 24
Finished Mar 17 01:40:24 PM PDT 24
Peak memory 203684 kb
Host smart-d20ecc50-cc3c-4e38-83cb-136e4e806790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41703
49293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.4170349293
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.2620251357
Short name T575
Test name
Test status
Simulation time 8366247211 ps
CPU time 7.84 seconds
Started Mar 17 01:40:16 PM PDT 24
Finished Mar 17 01:40:24 PM PDT 24
Peak memory 203692 kb
Host smart-f1ab3667-b399-464a-976f-88cd988ee89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26202
51357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.2620251357
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1537223386
Short name T256
Test name
Test status
Simulation time 8395012713 ps
CPU time 8.48 seconds
Started Mar 17 01:40:17 PM PDT 24
Finished Mar 17 01:40:25 PM PDT 24
Peak memory 203556 kb
Host smart-586907bd-6671-41c0-a42c-6c0274db3a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15372
23386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1537223386
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3231358820
Short name T558
Test name
Test status
Simulation time 8403320204 ps
CPU time 9.01 seconds
Started Mar 17 01:40:16 PM PDT 24
Finished Mar 17 01:40:25 PM PDT 24
Peak memory 203528 kb
Host smart-9ae2fae6-5a5d-41f0-a163-b087363c4757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32313
58820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3231358820
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2651074935
Short name T649
Test name
Test status
Simulation time 31250587 ps
CPU time 0.7 seconds
Started Mar 17 01:40:25 PM PDT 24
Finished Mar 17 01:40:27 PM PDT 24
Peak memory 203196 kb
Host smart-d622e376-fd8f-42a3-8b0e-870ff4dbd613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26510
74935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2651074935
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2829279705
Short name T122
Test name
Test status
Simulation time 8387491365 ps
CPU time 7.52 seconds
Started Mar 17 01:40:25 PM PDT 24
Finished Mar 17 01:40:33 PM PDT 24
Peak memory 203728 kb
Host smart-1cb7f5f1-b260-4632-8ba7-f05a9ac5c055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28292
79705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2829279705
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.3118621094
Short name T327
Test name
Test status
Simulation time 8400482430 ps
CPU time 7.26 seconds
Started Mar 17 01:40:22 PM PDT 24
Finished Mar 17 01:40:30 PM PDT 24
Peak memory 203708 kb
Host smart-394a07c3-7b5c-4d57-8657-e584459c20ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31186
21094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.3118621094
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.1204128271
Short name T714
Test name
Test status
Simulation time 8357233128 ps
CPU time 7.48 seconds
Started Mar 17 01:40:22 PM PDT 24
Finished Mar 17 01:40:29 PM PDT 24
Peak memory 203556 kb
Host smart-8257e213-a682-406c-83ea-ce9abd24522b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12041
28271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.1204128271
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.706156549
Short name T651
Test name
Test status
Simulation time 8469258236 ps
CPU time 7.32 seconds
Started Mar 17 01:40:10 PM PDT 24
Finished Mar 17 01:40:18 PM PDT 24
Peak memory 203740 kb
Host smart-20df740c-c561-4d38-888b-a0949d7b1a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70615
6549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.706156549
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.413379468
Short name T527
Test name
Test status
Simulation time 8371080341 ps
CPU time 7.99 seconds
Started Mar 17 01:40:25 PM PDT 24
Finished Mar 17 01:40:34 PM PDT 24
Peak memory 203736 kb
Host smart-bb611ec5-14aa-4904-9931-4c5eabd8a004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41337
9468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.413379468
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1432353567
Short name T444
Test name
Test status
Simulation time 48801815 ps
CPU time 1.33 seconds
Started Mar 17 01:40:31 PM PDT 24
Finished Mar 17 01:40:32 PM PDT 24
Peak memory 203744 kb
Host smart-6bb5df86-dac1-4a36-89cb-634f3c25f8c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14323
53567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1432353567
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3233563303
Short name T367
Test name
Test status
Simulation time 8450360024 ps
CPU time 9.28 seconds
Started Mar 17 01:40:26 PM PDT 24
Finished Mar 17 01:40:35 PM PDT 24
Peak memory 203712 kb
Host smart-2960e368-c9aa-4dd3-9627-c00f60a4a1cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32335
63303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3233563303
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2495507748
Short name T689
Test name
Test status
Simulation time 8406984751 ps
CPU time 7.12 seconds
Started Mar 17 01:40:28 PM PDT 24
Finished Mar 17 01:40:35 PM PDT 24
Peak memory 203696 kb
Host smart-875e9c3e-3614-4185-966c-8cf0a0f8567c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24955
07748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2495507748
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3734148757
Short name T473
Test name
Test status
Simulation time 8365128263 ps
CPU time 7.53 seconds
Started Mar 17 01:40:30 PM PDT 24
Finished Mar 17 01:40:37 PM PDT 24
Peak memory 203660 kb
Host smart-cb387503-4acf-4a2a-8550-dc147b12a658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37341
48757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3734148757
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2302174262
Short name T98
Test name
Test status
Simulation time 8425307178 ps
CPU time 7.14 seconds
Started Mar 17 01:40:28 PM PDT 24
Finished Mar 17 01:40:35 PM PDT 24
Peak memory 203736 kb
Host smart-15a10070-3d0d-4731-9577-bcc6399108c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23021
74262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2302174262
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2042998645
Short name T373
Test name
Test status
Simulation time 8369281835 ps
CPU time 7.16 seconds
Started Mar 17 01:40:28 PM PDT 24
Finished Mar 17 01:40:35 PM PDT 24
Peak memory 203544 kb
Host smart-080146df-7fec-4a26-a635-b7e0dae57f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20429
98645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2042998645
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2944405634
Short name T503
Test name
Test status
Simulation time 8388767101 ps
CPU time 7.53 seconds
Started Mar 17 01:40:30 PM PDT 24
Finished Mar 17 01:40:37 PM PDT 24
Peak memory 203552 kb
Host smart-9878832a-7f71-471e-8c31-d75c0d1432dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29444
05634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2944405634
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3663871148
Short name T621
Test name
Test status
Simulation time 27073662 ps
CPU time 0.66 seconds
Started Mar 17 01:40:37 PM PDT 24
Finished Mar 17 01:40:38 PM PDT 24
Peak memory 203232 kb
Host smart-96255418-d0c5-43e4-a09a-f6cbf1d11c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36638
71148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3663871148
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.3441880069
Short name T669
Test name
Test status
Simulation time 8437394176 ps
CPU time 7.6 seconds
Started Mar 17 01:40:35 PM PDT 24
Finished Mar 17 01:40:42 PM PDT 24
Peak memory 203728 kb
Host smart-22c8a268-963d-4012-b447-fb87e62ea0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34418
80069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3441880069
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.3497391208
Short name T681
Test name
Test status
Simulation time 8371788621 ps
CPU time 7.05 seconds
Started Mar 17 01:40:33 PM PDT 24
Finished Mar 17 01:40:40 PM PDT 24
Peak memory 203712 kb
Host smart-8ce67a6e-1df1-4581-9c8c-77ca340d45bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34973
91208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.3497391208
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.4005419085
Short name T553
Test name
Test status
Simulation time 8357883672 ps
CPU time 8.01 seconds
Started Mar 17 01:40:34 PM PDT 24
Finished Mar 17 01:40:42 PM PDT 24
Peak memory 203596 kb
Host smart-6d9f68d3-6e9c-4484-9f7b-2e057bdaeed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40054
19085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.4005419085
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.120895281
Short name T41
Test name
Test status
Simulation time 8473020642 ps
CPU time 7.42 seconds
Started Mar 17 01:40:25 PM PDT 24
Finished Mar 17 01:40:32 PM PDT 24
Peak memory 203740 kb
Host smart-71da3aa9-c35d-440a-b842-04672ec3866c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12089
5281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.120895281
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1754921543
Short name T33
Test name
Test status
Simulation time 8372286382 ps
CPU time 9.27 seconds
Started Mar 17 01:40:38 PM PDT 24
Finished Mar 17 01:40:48 PM PDT 24
Peak memory 203684 kb
Host smart-e4f1638c-5c9f-458a-b55d-6a25785788fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17549
21543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1754921543
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2414495931
Short name T555
Test name
Test status
Simulation time 113080204 ps
CPU time 1.34 seconds
Started Mar 17 01:40:36 PM PDT 24
Finished Mar 17 01:40:38 PM PDT 24
Peak memory 203672 kb
Host smart-1268309a-6bd7-4aa8-9607-681bf3786ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24144
95931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2414495931
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.771965953
Short name T150
Test name
Test status
Simulation time 8356529988 ps
CPU time 7.81 seconds
Started Mar 17 01:40:54 PM PDT 24
Finished Mar 17 01:41:03 PM PDT 24
Peak memory 203516 kb
Host smart-bd935598-fc56-4f7a-8265-90905d3af5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77196
5953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.771965953
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1431963944
Short name T27
Test name
Test status
Simulation time 8427658835 ps
CPU time 8.03 seconds
Started Mar 17 01:40:40 PM PDT 24
Finished Mar 17 01:40:49 PM PDT 24
Peak memory 203656 kb
Host smart-1116401c-939f-4cc2-807c-b9011ae801e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14319
63944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1431963944
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2340064696
Short name T390
Test name
Test status
Simulation time 8411112680 ps
CPU time 7.41 seconds
Started Mar 17 01:40:38 PM PDT 24
Finished Mar 17 01:40:46 PM PDT 24
Peak memory 203692 kb
Host smart-77cca798-5e0c-4eea-9dac-c51af576f5cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23400
64696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2340064696
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.967234706
Short name T6
Test name
Test status
Simulation time 8363793741 ps
CPU time 7.36 seconds
Started Mar 17 01:40:40 PM PDT 24
Finished Mar 17 01:40:48 PM PDT 24
Peak memory 203708 kb
Host smart-4b4d0ebc-e602-4e07-9d8a-49f60c485f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96723
4706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.967234706
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.442627523
Short name T563
Test name
Test status
Simulation time 8443940551 ps
CPU time 7.11 seconds
Started Mar 17 01:40:42 PM PDT 24
Finished Mar 17 01:40:50 PM PDT 24
Peak memory 203688 kb
Host smart-627d84dd-2103-4eda-b50b-92b8df1d2006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44262
7523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.442627523
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1877141777
Short name T571
Test name
Test status
Simulation time 8405367592 ps
CPU time 9.27 seconds
Started Mar 17 01:40:39 PM PDT 24
Finished Mar 17 01:40:49 PM PDT 24
Peak memory 203704 kb
Host smart-a7f822d1-59d2-4a40-9196-645bcfccd096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18771
41777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1877141777
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.893634082
Short name T375
Test name
Test status
Simulation time 8402885550 ps
CPU time 7.31 seconds
Started Mar 17 01:40:43 PM PDT 24
Finished Mar 17 01:40:50 PM PDT 24
Peak memory 203556 kb
Host smart-f525b211-a2f4-47b7-b0f3-1a3ae50820a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89363
4082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.893634082
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.1338006372
Short name T333
Test name
Test status
Simulation time 27201871 ps
CPU time 0.64 seconds
Started Mar 17 01:40:44 PM PDT 24
Finished Mar 17 01:40:44 PM PDT 24
Peak memory 203180 kb
Host smart-1c8f0640-e15f-42e5-b134-c7918d208751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13380
06372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.1338006372
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.628197350
Short name T465
Test name
Test status
Simulation time 8449460421 ps
CPU time 8.7 seconds
Started Mar 17 01:40:40 PM PDT 24
Finished Mar 17 01:40:49 PM PDT 24
Peak memory 203764 kb
Host smart-fc368677-63c0-4fde-b144-8476887f291b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62819
7350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.628197350
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.3627107744
Short name T254
Test name
Test status
Simulation time 8382631378 ps
CPU time 7.63 seconds
Started Mar 17 01:40:45 PM PDT 24
Finished Mar 17 01:40:53 PM PDT 24
Peak memory 203752 kb
Host smart-82cf854f-c09d-41ff-95d5-c2402111c0c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36271
07744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.3627107744
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1412384370
Short name T331
Test name
Test status
Simulation time 8362744570 ps
CPU time 9.57 seconds
Started Mar 17 01:40:44 PM PDT 24
Finished Mar 17 01:40:54 PM PDT 24
Peak memory 203552 kb
Host smart-fc7f5b07-4f80-458c-960a-254b099c0355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14123
84370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1412384370
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.2939860470
Short name T675
Test name
Test status
Simulation time 8367467514 ps
CPU time 8.3 seconds
Started Mar 17 01:40:44 PM PDT 24
Finished Mar 17 01:40:53 PM PDT 24
Peak memory 203736 kb
Host smart-5b4ffe7d-2786-44e5-9ad5-c865076e3d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29398
60470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.2939860470
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1263568161
Short name T742
Test name
Test status
Simulation time 40042861 ps
CPU time 1.07 seconds
Started Mar 17 01:40:56 PM PDT 24
Finished Mar 17 01:40:58 PM PDT 24
Peak memory 203608 kb
Host smart-340f26fd-6ebc-4bb0-a673-97cc597321ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12635
68161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1263568161
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.3184920508
Short name T154
Test name
Test status
Simulation time 8364664250 ps
CPU time 7.33 seconds
Started Mar 17 01:40:58 PM PDT 24
Finished Mar 17 01:41:05 PM PDT 24
Peak memory 203512 kb
Host smart-dbb76e06-b625-4c05-8cac-5fa6cdd72eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31849
20508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.3184920508
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.1593535266
Short name T19
Test name
Test status
Simulation time 8443201130 ps
CPU time 8.09 seconds
Started Mar 17 01:40:54 PM PDT 24
Finished Mar 17 01:41:04 PM PDT 24
Peak memory 203740 kb
Host smart-11b61e2d-8b90-4ac3-9beb-19379b466862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15935
35266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1593535266
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.841629756
Short name T671
Test name
Test status
Simulation time 8404823716 ps
CPU time 7.46 seconds
Started Mar 17 01:40:48 PM PDT 24
Finished Mar 17 01:40:56 PM PDT 24
Peak memory 203436 kb
Host smart-dadeca80-4e1f-4e4b-9c4d-43969f5e63a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84162
9756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.841629756
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.636562715
Short name T567
Test name
Test status
Simulation time 8364849267 ps
CPU time 7.73 seconds
Started Mar 17 01:40:53 PM PDT 24
Finished Mar 17 01:41:03 PM PDT 24
Peak memory 203688 kb
Host smart-e93caa7c-5815-4e38-8c6d-64538a5737c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63656
2715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.636562715
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.4007341289
Short name T652
Test name
Test status
Simulation time 8424492289 ps
CPU time 7.22 seconds
Started Mar 17 01:40:52 PM PDT 24
Finished Mar 17 01:41:01 PM PDT 24
Peak memory 203688 kb
Host smart-4f001a62-7814-4cfc-9066-953bd243999c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40073
41289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.4007341289
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2963669328
Short name T389
Test name
Test status
Simulation time 8394517953 ps
CPU time 7.98 seconds
Started Mar 17 01:40:52 PM PDT 24
Finished Mar 17 01:41:01 PM PDT 24
Peak memory 203524 kb
Host smart-35c87c04-8a47-4bfc-9a18-97a73c9c128d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29636
69328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2963669328
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1659205229
Short name T708
Test name
Test status
Simulation time 8394667216 ps
CPU time 7.12 seconds
Started Mar 17 01:40:53 PM PDT 24
Finished Mar 17 01:41:02 PM PDT 24
Peak memory 203512 kb
Host smart-52dcc7d1-4aa2-4d1b-99e3-605805895d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16592
05229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1659205229
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1694069674
Short name T351
Test name
Test status
Simulation time 25740265 ps
CPU time 0.62 seconds
Started Mar 17 01:40:58 PM PDT 24
Finished Mar 17 01:40:59 PM PDT 24
Peak memory 203224 kb
Host smart-39fc1396-eb90-4dec-b8df-886e6e716747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16940
69674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1694069674
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3586028139
Short name T728
Test name
Test status
Simulation time 8446294460 ps
CPU time 8.17 seconds
Started Mar 17 01:40:52 PM PDT 24
Finished Mar 17 01:41:03 PM PDT 24
Peak memory 203684 kb
Host smart-6dc52e7e-a126-4b85-b738-bd06711d8700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35860
28139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3586028139
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.1352410050
Short name T490
Test name
Test status
Simulation time 8408925954 ps
CPU time 7.78 seconds
Started Mar 17 01:40:57 PM PDT 24
Finished Mar 17 01:41:05 PM PDT 24
Peak memory 203696 kb
Host smart-97bbaaf5-b26b-457d-90d7-a722eb3b5af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13524
10050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.1352410050
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.4214303531
Short name T422
Test name
Test status
Simulation time 8358506609 ps
CPU time 7.42 seconds
Started Mar 17 01:40:57 PM PDT 24
Finished Mar 17 01:41:05 PM PDT 24
Peak memory 203516 kb
Host smart-110a7f38-ee3c-4163-8bd3-a08ef098931b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42143
03531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.4214303531
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2526440594
Short name T135
Test name
Test status
Simulation time 8472078229 ps
CPU time 7.89 seconds
Started Mar 17 01:40:44 PM PDT 24
Finished Mar 17 01:40:52 PM PDT 24
Peak memory 203660 kb
Host smart-79f7408a-ec9b-464f-98c2-7c0ed9a6c2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25264
40594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2526440594
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.4263938758
Short name T364
Test name
Test status
Simulation time 8369550136 ps
CPU time 8.77 seconds
Started Mar 17 01:38:03 PM PDT 24
Finished Mar 17 01:38:12 PM PDT 24
Peak memory 203728 kb
Host smart-c670629c-94a4-483f-8118-81f8a1372386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42639
38758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.4263938758
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.3834218845
Short name T455
Test name
Test status
Simulation time 95480152 ps
CPU time 1.2 seconds
Started Mar 17 01:38:02 PM PDT 24
Finished Mar 17 01:38:03 PM PDT 24
Peak memory 203632 kb
Host smart-2b68791b-9059-4a64-b67f-3647e52a487a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38342
18845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.3834218845
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.4076118174
Short name T165
Test name
Test status
Simulation time 8359095743 ps
CPU time 7.19 seconds
Started Mar 17 01:38:14 PM PDT 24
Finished Mar 17 01:38:22 PM PDT 24
Peak memory 203448 kb
Host smart-50052257-9bbe-42b3-9e9c-b857611895bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40761
18174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.4076118174
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.867625666
Short name T453
Test name
Test status
Simulation time 8410055940 ps
CPU time 7.5 seconds
Started Mar 17 01:38:08 PM PDT 24
Finished Mar 17 01:38:16 PM PDT 24
Peak memory 203664 kb
Host smart-2db28fa9-6c86-4a3a-8ed2-e2831f03ae5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86762
5666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.867625666
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.1814775383
Short name T216
Test name
Test status
Simulation time 8362096061 ps
CPU time 7.45 seconds
Started Mar 17 01:38:13 PM PDT 24
Finished Mar 17 01:38:20 PM PDT 24
Peak memory 203708 kb
Host smart-bb5ad1eb-3fa9-40f3-b509-ae02f0791dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18147
75383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.1814775383
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.2012010034
Short name T660
Test name
Test status
Simulation time 8405716096 ps
CPU time 7.94 seconds
Started Mar 17 01:38:14 PM PDT 24
Finished Mar 17 01:38:22 PM PDT 24
Peak memory 203572 kb
Host smart-55b20a21-2150-4666-a98d-40fbab66a789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20120
10034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.2012010034
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1271453742
Short name T70
Test name
Test status
Simulation time 8362980377 ps
CPU time 7.57 seconds
Started Mar 17 01:38:14 PM PDT 24
Finished Mar 17 01:38:22 PM PDT 24
Peak memory 203672 kb
Host smart-11292a03-5be6-4668-9173-98c2a5dc9758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12714
53742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1271453742
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.113507433
Short name T663
Test name
Test status
Simulation time 27516635 ps
CPU time 0.67 seconds
Started Mar 17 01:38:14 PM PDT 24
Finished Mar 17 01:38:15 PM PDT 24
Peak memory 203256 kb
Host smart-17612c86-4614-4feb-ab7c-dde29286559f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11350
7433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.113507433
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3419784392
Short name T125
Test name
Test status
Simulation time 8391016308 ps
CPU time 9.49 seconds
Started Mar 17 01:38:08 PM PDT 24
Finished Mar 17 01:38:18 PM PDT 24
Peak memory 203672 kb
Host smart-9e3cbc19-9665-48fa-a425-4d38c81da5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34197
84392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3419784392
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.809396707
Short name T417
Test name
Test status
Simulation time 8405637665 ps
CPU time 7.21 seconds
Started Mar 17 01:38:14 PM PDT 24
Finished Mar 17 01:38:22 PM PDT 24
Peak memory 203708 kb
Host smart-51c5f361-21bc-43b3-9a9e-cddae4e290f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80939
6707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.809396707
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.4127794579
Short name T49
Test name
Test status
Simulation time 93971536 ps
CPU time 0.85 seconds
Started Mar 17 01:38:17 PM PDT 24
Finished Mar 17 01:38:19 PM PDT 24
Peak memory 219432 kb
Host smart-3ca97733-a3b0-454b-b4c5-9edcaccb690b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4127794579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.4127794579
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3323153923
Short name T596
Test name
Test status
Simulation time 8357452441 ps
CPU time 8.57 seconds
Started Mar 17 01:38:14 PM PDT 24
Finished Mar 17 01:38:23 PM PDT 24
Peak memory 203576 kb
Host smart-15215598-3990-4b4c-a133-f6c4d8d571b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33231
53923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3323153923
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.4277458205
Short name T138
Test name
Test status
Simulation time 8474757733 ps
CPU time 8.38 seconds
Started Mar 17 01:38:02 PM PDT 24
Finished Mar 17 01:38:11 PM PDT 24
Peak memory 203620 kb
Host smart-15ba3d42-f1f7-4de7-bf23-daf7cc985e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42774
58205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.4277458205
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.155048525
Short name T546
Test name
Test status
Simulation time 8368393738 ps
CPU time 7.54 seconds
Started Mar 17 01:41:03 PM PDT 24
Finished Mar 17 01:41:11 PM PDT 24
Peak memory 203664 kb
Host smart-eaa3e4e3-5328-4112-bb72-feb849978677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15504
8525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.155048525
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1865827691
Short name T475
Test name
Test status
Simulation time 8364280495 ps
CPU time 9.35 seconds
Started Mar 17 01:41:13 PM PDT 24
Finished Mar 17 01:41:22 PM PDT 24
Peak memory 203568 kb
Host smart-9b235d0b-8a8e-42ec-908d-24c29841100d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18658
27691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1865827691
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2086371276
Short name T570
Test name
Test status
Simulation time 8420202779 ps
CPU time 7.46 seconds
Started Mar 17 01:41:07 PM PDT 24
Finished Mar 17 01:41:15 PM PDT 24
Peak memory 203752 kb
Host smart-2b176a78-8ec6-45bd-ba2b-068e8d1093d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20863
71276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2086371276
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.3036709933
Short name T359
Test name
Test status
Simulation time 8407722431 ps
CPU time 7.91 seconds
Started Mar 17 01:41:06 PM PDT 24
Finished Mar 17 01:41:14 PM PDT 24
Peak memory 203704 kb
Host smart-e6e5bd44-b041-4864-9101-8320b90e09b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30367
09933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.3036709933
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.3052735958
Short name T462
Test name
Test status
Simulation time 8365445015 ps
CPU time 8.1 seconds
Started Mar 17 01:41:12 PM PDT 24
Finished Mar 17 01:41:20 PM PDT 24
Peak memory 203732 kb
Host smart-373c289a-fa90-4822-9aae-cb92e7a8627c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30527
35958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.3052735958
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.85525575
Short name T450
Test name
Test status
Simulation time 8390982889 ps
CPU time 8.58 seconds
Started Mar 17 01:41:11 PM PDT 24
Finished Mar 17 01:41:20 PM PDT 24
Peak memory 203588 kb
Host smart-346e22f5-520f-4067-b824-2d018dcecc4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85525
575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.85525575
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2323262423
Short name T2
Test name
Test status
Simulation time 8377059102 ps
CPU time 7.69 seconds
Started Mar 17 01:41:15 PM PDT 24
Finished Mar 17 01:41:23 PM PDT 24
Peak memory 203496 kb
Host smart-5f74d0c9-631f-40e2-a977-7ac73dd84406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23232
62423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2323262423
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.516450792
Short name T657
Test name
Test status
Simulation time 31013437 ps
CPU time 0.64 seconds
Started Mar 17 01:41:12 PM PDT 24
Finished Mar 17 01:41:13 PM PDT 24
Peak memory 203180 kb
Host smart-927e58d9-7813-4c89-9801-f03d6b1e4be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51645
0792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.516450792
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1986119460
Short name T403
Test name
Test status
Simulation time 8426847712 ps
CPU time 7.61 seconds
Started Mar 17 01:41:09 PM PDT 24
Finished Mar 17 01:41:17 PM PDT 24
Peak memory 203704 kb
Host smart-258f0c84-6117-40d9-b929-e02657bf3b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19861
19460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1986119460
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.2759553883
Short name T540
Test name
Test status
Simulation time 8404656334 ps
CPU time 7.62 seconds
Started Mar 17 01:41:10 PM PDT 24
Finished Mar 17 01:41:17 PM PDT 24
Peak memory 203672 kb
Host smart-d3cb2031-5c46-4fe9-bb30-12cd3e49561e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27595
53883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.2759553883
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.758144949
Short name T518
Test name
Test status
Simulation time 8357237564 ps
CPU time 7.51 seconds
Started Mar 17 01:41:10 PM PDT 24
Finished Mar 17 01:41:17 PM PDT 24
Peak memory 203536 kb
Host smart-93913eea-6eac-49fe-b94d-5330b6e963dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75814
4949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.758144949
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.3330369301
Short name T226
Test name
Test status
Simulation time 8373191706 ps
CPU time 7.63 seconds
Started Mar 17 01:41:10 PM PDT 24
Finished Mar 17 01:41:18 PM PDT 24
Peak memory 203712 kb
Host smart-26f3c8b4-5ccb-462d-b20a-350724e21357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33303
69301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.3330369301
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.2843739188
Short name T406
Test name
Test status
Simulation time 98533000 ps
CPU time 1.1 seconds
Started Mar 17 01:41:10 PM PDT 24
Finished Mar 17 01:41:12 PM PDT 24
Peak memory 203724 kb
Host smart-b3c16f2e-48da-4455-ab08-ab5b1d9c8947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28437
39188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.2843739188
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2587912316
Short name T179
Test name
Test status
Simulation time 8358994051 ps
CPU time 7.12 seconds
Started Mar 17 01:41:16 PM PDT 24
Finished Mar 17 01:41:23 PM PDT 24
Peak memory 203532 kb
Host smart-7d3fa212-aa95-430d-bc02-f877efc91167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25879
12316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2587912316
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3673584869
Short name T119
Test name
Test status
Simulation time 8445200307 ps
CPU time 8.4 seconds
Started Mar 17 01:41:16 PM PDT 24
Finished Mar 17 01:41:24 PM PDT 24
Peak memory 203752 kb
Host smart-2749c10d-9ebb-486d-9136-22f12e9c924e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36735
84869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3673584869
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1397361780
Short name T306
Test name
Test status
Simulation time 8407451602 ps
CPU time 8.38 seconds
Started Mar 17 01:41:19 PM PDT 24
Finished Mar 17 01:41:27 PM PDT 24
Peak memory 203640 kb
Host smart-79a1ece4-e10d-4d77-a5d8-f84d24400984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13973
61780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1397361780
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.1272696115
Short name T380
Test name
Test status
Simulation time 8361220744 ps
CPU time 7.15 seconds
Started Mar 17 01:41:25 PM PDT 24
Finished Mar 17 01:41:32 PM PDT 24
Peak memory 203584 kb
Host smart-44f065ee-3910-427d-9888-043cb9a95f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12726
96115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1272696115
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3263074535
Short name T661
Test name
Test status
Simulation time 8373210902 ps
CPU time 9.41 seconds
Started Mar 17 01:41:17 PM PDT 24
Finished Mar 17 01:41:27 PM PDT 24
Peak memory 203664 kb
Host smart-9d627dcf-0512-4e99-bfb1-aaeac349730a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32630
74535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3263074535
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1814491810
Short name T472
Test name
Test status
Simulation time 8392042480 ps
CPU time 7.28 seconds
Started Mar 17 01:41:18 PM PDT 24
Finished Mar 17 01:41:26 PM PDT 24
Peak memory 203492 kb
Host smart-1ad88c29-736f-4331-a904-2427edf0b6d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18144
91810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1814491810
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.3899616166
Short name T667
Test name
Test status
Simulation time 31979881 ps
CPU time 0.64 seconds
Started Mar 17 01:41:16 PM PDT 24
Finished Mar 17 01:41:17 PM PDT 24
Peak memory 203244 kb
Host smart-90a7a427-9a71-4df8-baf1-24242b095620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38996
16166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.3899616166
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3608418571
Short name T704
Test name
Test status
Simulation time 8441331488 ps
CPU time 7.91 seconds
Started Mar 17 01:41:16 PM PDT 24
Finished Mar 17 01:41:24 PM PDT 24
Peak memory 203728 kb
Host smart-62c9f4d9-5c8e-4bb5-8403-cb4f3ba901e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36084
18571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3608418571
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.509599151
Short name T747
Test name
Test status
Simulation time 8359158682 ps
CPU time 7.4 seconds
Started Mar 17 01:41:16 PM PDT 24
Finished Mar 17 01:41:24 PM PDT 24
Peak memory 203732 kb
Host smart-5de65d4f-168b-4ec6-8b45-04c69c49cc8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50959
9151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.509599151
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.306577170
Short name T644
Test name
Test status
Simulation time 8354382364 ps
CPU time 8.6 seconds
Started Mar 17 01:41:17 PM PDT 24
Finished Mar 17 01:41:26 PM PDT 24
Peak memory 203616 kb
Host smart-fc967632-0d64-4f50-ae55-fff2e063521d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30657
7170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.306577170
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1076052295
Short name T145
Test name
Test status
Simulation time 8476642542 ps
CPU time 7.82 seconds
Started Mar 17 01:41:10 PM PDT 24
Finished Mar 17 01:41:18 PM PDT 24
Peak memory 203732 kb
Host smart-36380482-a9c6-4ddc-b528-6360d1351ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10760
52295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1076052295
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3373384376
Short name T295
Test name
Test status
Simulation time 8367913307 ps
CPU time 8.2 seconds
Started Mar 17 01:41:25 PM PDT 24
Finished Mar 17 01:41:33 PM PDT 24
Peak memory 203712 kb
Host smart-0b2d9c56-5b60-4a17-ae4a-be2ed5714a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33733
84376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3373384376
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3777963589
Short name T382
Test name
Test status
Simulation time 46399499 ps
CPU time 1.3 seconds
Started Mar 17 01:41:22 PM PDT 24
Finished Mar 17 01:41:24 PM PDT 24
Peak memory 203476 kb
Host smart-42f71bcf-a046-4701-bb66-1817da917eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37779
63589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3777963589
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2519384259
Short name T308
Test name
Test status
Simulation time 8361940769 ps
CPU time 7.9 seconds
Started Mar 17 01:41:27 PM PDT 24
Finished Mar 17 01:41:35 PM PDT 24
Peak memory 203432 kb
Host smart-653f1f9d-3b69-42af-857e-100bf5fad0c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25193
84259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2519384259
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1592662399
Short name T678
Test name
Test status
Simulation time 8391867934 ps
CPU time 8.09 seconds
Started Mar 17 01:41:22 PM PDT 24
Finished Mar 17 01:41:30 PM PDT 24
Peak memory 203736 kb
Host smart-34556d4e-ac8f-4490-b838-91b31c45206e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15926
62399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1592662399
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2087106837
Short name T457
Test name
Test status
Simulation time 8407768858 ps
CPU time 7.46 seconds
Started Mar 17 01:41:26 PM PDT 24
Finished Mar 17 01:41:34 PM PDT 24
Peak memory 203732 kb
Host smart-0688f245-2183-4c9b-9b28-33989ae2b9ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20871
06837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2087106837
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3097328945
Short name T321
Test name
Test status
Simulation time 8364663209 ps
CPU time 7.01 seconds
Started Mar 17 01:41:26 PM PDT 24
Finished Mar 17 01:41:33 PM PDT 24
Peak memory 203680 kb
Host smart-b032e3b7-3f1a-437f-9f40-8db357184c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30973
28945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3097328945
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3313123312
Short name T111
Test name
Test status
Simulation time 8454700044 ps
CPU time 8.57 seconds
Started Mar 17 01:41:23 PM PDT 24
Finished Mar 17 01:41:31 PM PDT 24
Peak memory 203708 kb
Host smart-f0085d14-07c2-4f6c-8e4e-116bbe7a3bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33131
23312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3313123312
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2808104873
Short name T498
Test name
Test status
Simulation time 8405210802 ps
CPU time 7.79 seconds
Started Mar 17 01:41:22 PM PDT 24
Finished Mar 17 01:41:30 PM PDT 24
Peak memory 203720 kb
Host smart-d06ffabf-77e1-4b86-8032-ec1511258be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28081
04873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2808104873
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.3230048742
Short name T290
Test name
Test status
Simulation time 8370375193 ps
CPU time 8.16 seconds
Started Mar 17 01:41:26 PM PDT 24
Finished Mar 17 01:41:34 PM PDT 24
Peak memory 203520 kb
Host smart-15ba2fec-5772-4410-ad20-0caed82751dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32300
48742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.3230048742
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1413851784
Short name T509
Test name
Test status
Simulation time 30718792 ps
CPU time 0.62 seconds
Started Mar 17 01:41:30 PM PDT 24
Finished Mar 17 01:41:30 PM PDT 24
Peak memory 203164 kb
Host smart-295f2867-8f9a-4335-8881-ffd59800914a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14138
51784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1413851784
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1489212635
Short name T412
Test name
Test status
Simulation time 8395376177 ps
CPU time 7.68 seconds
Started Mar 17 01:41:27 PM PDT 24
Finished Mar 17 01:41:34 PM PDT 24
Peak memory 203728 kb
Host smart-d171ea49-823b-4c17-9230-9ad597e18fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14892
12635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1489212635
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.1383407779
Short name T371
Test name
Test status
Simulation time 8394292334 ps
CPU time 7.05 seconds
Started Mar 17 01:41:30 PM PDT 24
Finished Mar 17 01:41:37 PM PDT 24
Peak memory 203676 kb
Host smart-6599ecb4-980d-47a3-ac15-b4d364f8d834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13834
07779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.1383407779
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.250388894
Short name T588
Test name
Test status
Simulation time 8354075762 ps
CPU time 7.73 seconds
Started Mar 17 01:41:34 PM PDT 24
Finished Mar 17 01:41:41 PM PDT 24
Peak memory 203536 kb
Host smart-a6ca971b-715d-4b33-9d6f-9ef390ef61bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25038
8894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.250388894
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1528398027
Short name T336
Test name
Test status
Simulation time 8477388126 ps
CPU time 7.9 seconds
Started Mar 17 01:41:25 PM PDT 24
Finished Mar 17 01:41:33 PM PDT 24
Peak memory 203716 kb
Host smart-a59b4419-c098-48d5-9ae4-3de262df87ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15283
98027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1528398027
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2586487317
Short name T402
Test name
Test status
Simulation time 8368762754 ps
CPU time 7.11 seconds
Started Mar 17 01:41:31 PM PDT 24
Finished Mar 17 01:41:38 PM PDT 24
Peak memory 203752 kb
Host smart-7e86ac66-5ff9-48d3-8408-7f7b25edf3b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25864
87317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2586487317
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3709135938
Short name T222
Test name
Test status
Simulation time 117604616 ps
CPU time 1.3 seconds
Started Mar 17 01:41:34 PM PDT 24
Finished Mar 17 01:41:35 PM PDT 24
Peak memory 203752 kb
Host smart-1d8a7bd6-d454-4e83-9699-ea7a873da37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37091
35938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3709135938
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1803826081
Short name T168
Test name
Test status
Simulation time 8356534509 ps
CPU time 8.05 seconds
Started Mar 17 01:41:44 PM PDT 24
Finished Mar 17 01:41:52 PM PDT 24
Peak memory 203492 kb
Host smart-1435fdb4-baf2-48fe-bff7-13fe58f1e996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18038
26081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1803826081
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.210859990
Short name T343
Test name
Test status
Simulation time 8455069581 ps
CPU time 7.39 seconds
Started Mar 17 01:41:32 PM PDT 24
Finished Mar 17 01:41:40 PM PDT 24
Peak memory 203688 kb
Host smart-b798e323-214f-456e-8046-5f72b4b294fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21085
9990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.210859990
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.1225866018
Short name T319
Test name
Test status
Simulation time 8409520373 ps
CPU time 9.01 seconds
Started Mar 17 01:41:33 PM PDT 24
Finished Mar 17 01:41:43 PM PDT 24
Peak memory 203660 kb
Host smart-3b3674eb-62c4-4b2b-aece-5d512b7f0408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12258
66018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.1225866018
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.932441771
Short name T673
Test name
Test status
Simulation time 8368509075 ps
CPU time 8.52 seconds
Started Mar 17 01:41:34 PM PDT 24
Finished Mar 17 01:41:42 PM PDT 24
Peak memory 203664 kb
Host smart-600c6a4b-0e4e-49b7-92eb-ec70961222c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93244
1771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.932441771
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2846493175
Short name T388
Test name
Test status
Simulation time 8369427790 ps
CPU time 7.49 seconds
Started Mar 17 01:41:35 PM PDT 24
Finished Mar 17 01:41:42 PM PDT 24
Peak memory 203604 kb
Host smart-37d9ccc0-cceb-49e5-8381-2e97c2b426cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28464
93175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2846493175
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3730510711
Short name T683
Test name
Test status
Simulation time 8384391780 ps
CPU time 6.97 seconds
Started Mar 17 01:41:33 PM PDT 24
Finished Mar 17 01:41:40 PM PDT 24
Peak memory 203516 kb
Host smart-2605d59b-0564-45c5-8306-6ecbc9a5989f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37305
10711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3730510711
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1002594487
Short name T341
Test name
Test status
Simulation time 22208917 ps
CPU time 0.64 seconds
Started Mar 17 01:41:35 PM PDT 24
Finished Mar 17 01:41:35 PM PDT 24
Peak memory 203076 kb
Host smart-9586613a-a9bf-450d-95aa-49a8c00f1a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10025
94487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1002594487
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2095940593
Short name T458
Test name
Test status
Simulation time 8384676007 ps
CPU time 7.39 seconds
Started Mar 17 01:41:34 PM PDT 24
Finished Mar 17 01:41:41 PM PDT 24
Peak memory 203704 kb
Host smart-d580454c-09f0-492d-ab9c-1c965f75c90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20959
40593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2095940593
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.2826844459
Short name T370
Test name
Test status
Simulation time 8397643601 ps
CPU time 7.77 seconds
Started Mar 17 01:41:34 PM PDT 24
Finished Mar 17 01:41:42 PM PDT 24
Peak memory 203660 kb
Host smart-8cbb04c0-7b02-4cac-89dc-d3f9946dd3c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28268
44459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.2826844459
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2759952761
Short name T11
Test name
Test status
Simulation time 8355335265 ps
CPU time 6.95 seconds
Started Mar 17 01:41:33 PM PDT 24
Finished Mar 17 01:41:40 PM PDT 24
Peak memory 203612 kb
Host smart-22f4939f-35cf-4dda-af12-97751b34d330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27599
52761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2759952761
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.2439723131
Short name T633
Test name
Test status
Simulation time 8478546144 ps
CPU time 9.4 seconds
Started Mar 17 01:41:27 PM PDT 24
Finished Mar 17 01:41:37 PM PDT 24
Peak memory 203768 kb
Host smart-93a51e41-a224-4eca-b12b-48b7dde5821f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24397
23131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.2439723131
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3499787682
Short name T500
Test name
Test status
Simulation time 8367088771 ps
CPU time 7.13 seconds
Started Mar 17 01:41:39 PM PDT 24
Finished Mar 17 01:41:46 PM PDT 24
Peak memory 203688 kb
Host smart-d6105c34-df70-4802-8c50-6636bd852f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34997
87682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3499787682
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.4119920854
Short name T283
Test name
Test status
Simulation time 186238667 ps
CPU time 1.61 seconds
Started Mar 17 01:41:38 PM PDT 24
Finished Mar 17 01:41:40 PM PDT 24
Peak memory 203660 kb
Host smart-73eebb75-3608-47dd-a6f5-7fa8befee249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41199
20854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.4119920854
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3818905675
Short name T159
Test name
Test status
Simulation time 8361776878 ps
CPU time 7.51 seconds
Started Mar 17 01:41:48 PM PDT 24
Finished Mar 17 01:41:55 PM PDT 24
Peak memory 203452 kb
Host smart-506bff04-ab5f-49e4-8b25-4fe3f2f11029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38189
05675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3818905675
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.368775076
Short name T511
Test name
Test status
Simulation time 8458032877 ps
CPU time 7.45 seconds
Started Mar 17 01:41:40 PM PDT 24
Finished Mar 17 01:41:47 PM PDT 24
Peak memory 203676 kb
Host smart-3ff06e85-b3f0-4e8a-8e6c-b7ac8851d81b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36877
5076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.368775076
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.3895204128
Short name T479
Test name
Test status
Simulation time 8410126143 ps
CPU time 8 seconds
Started Mar 17 01:41:37 PM PDT 24
Finished Mar 17 01:41:45 PM PDT 24
Peak memory 203692 kb
Host smart-29a8ae36-df22-439b-96fa-f0b6385e65b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38952
04128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3895204128
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.141197192
Short name T697
Test name
Test status
Simulation time 8362916936 ps
CPU time 7.98 seconds
Started Mar 17 01:41:45 PM PDT 24
Finished Mar 17 01:41:53 PM PDT 24
Peak memory 203656 kb
Host smart-ff6ab1b8-9f82-47d3-ae8e-ccda24ded9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14119
7192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.141197192
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3604776263
Short name T349
Test name
Test status
Simulation time 8402710826 ps
CPU time 7.7 seconds
Started Mar 17 01:41:44 PM PDT 24
Finished Mar 17 01:41:52 PM PDT 24
Peak memory 203512 kb
Host smart-a7bb7b77-1e6b-463d-9d71-cc9d63eb073d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36047
76263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3604776263
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2703483319
Short name T372
Test name
Test status
Simulation time 8395068543 ps
CPU time 7.45 seconds
Started Mar 17 01:41:39 PM PDT 24
Finished Mar 17 01:41:46 PM PDT 24
Peak memory 203704 kb
Host smart-b4891a27-b065-449f-b6fe-90a27fc7d03f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27034
83319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2703483319
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2524745126
Short name T740
Test name
Test status
Simulation time 26105238 ps
CPU time 0.66 seconds
Started Mar 17 01:41:49 PM PDT 24
Finished Mar 17 01:41:50 PM PDT 24
Peak memory 203196 kb
Host smart-c2e4fe30-3003-4b34-93d0-b762cd6db3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25247
45126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2524745126
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.2697057161
Short name T705
Test name
Test status
Simulation time 8453102568 ps
CPU time 10.04 seconds
Started Mar 17 01:41:38 PM PDT 24
Finished Mar 17 01:41:48 PM PDT 24
Peak memory 203732 kb
Host smart-4ffd7068-ce11-4e80-9c2d-ee10d0f892f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26970
57161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2697057161
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.1724149709
Short name T664
Test name
Test status
Simulation time 8400804949 ps
CPU time 7.79 seconds
Started Mar 17 01:41:39 PM PDT 24
Finished Mar 17 01:41:48 PM PDT 24
Peak memory 203696 kb
Host smart-21403d5d-16b3-42bb-8a59-b9710016e01e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17241
49709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.1724149709
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2296330819
Short name T73
Test name
Test status
Simulation time 8357463202 ps
CPU time 7 seconds
Started Mar 17 01:41:36 PM PDT 24
Finished Mar 17 01:41:43 PM PDT 24
Peak memory 203580 kb
Host smart-da52087c-0df7-4193-8f56-dfecb612966a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22963
30819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2296330819
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.51483028
Short name T141
Test name
Test status
Simulation time 8470621935 ps
CPU time 7.47 seconds
Started Mar 17 01:41:40 PM PDT 24
Finished Mar 17 01:41:48 PM PDT 24
Peak memory 203648 kb
Host smart-4612f137-792a-41e9-8082-28fb2e1b3231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51483
028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.51483028
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3114079394
Short name T355
Test name
Test status
Simulation time 8367162793 ps
CPU time 7.32 seconds
Started Mar 17 01:41:45 PM PDT 24
Finished Mar 17 01:41:53 PM PDT 24
Peak memory 203740 kb
Host smart-36056918-b02d-47de-82b3-17ae15aaba63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31140
79394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3114079394
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1752245714
Short name T562
Test name
Test status
Simulation time 52233262 ps
CPU time 1.48 seconds
Started Mar 17 01:41:44 PM PDT 24
Finished Mar 17 01:41:46 PM PDT 24
Peak memory 203800 kb
Host smart-bbee92c1-26d3-4240-bed3-17924f1a7061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17522
45714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1752245714
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.4074064378
Short name T172
Test name
Test status
Simulation time 8360855621 ps
CPU time 6.92 seconds
Started Mar 17 01:41:54 PM PDT 24
Finished Mar 17 01:42:01 PM PDT 24
Peak memory 203504 kb
Host smart-63de45bb-1320-4437-b685-2be2c627394d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40740
64378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.4074064378
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3201148783
Short name T421
Test name
Test status
Simulation time 8412675611 ps
CPU time 8.65 seconds
Started Mar 17 01:41:45 PM PDT 24
Finished Mar 17 01:41:54 PM PDT 24
Peak memory 203712 kb
Host smart-e049868d-a682-4b68-8a82-bf161d6218ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32011
48783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3201148783
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1870860779
Short name T486
Test name
Test status
Simulation time 8406799246 ps
CPU time 8.8 seconds
Started Mar 17 01:41:54 PM PDT 24
Finished Mar 17 01:42:03 PM PDT 24
Peak memory 203696 kb
Host smart-6dbe041c-707f-4f52-88ff-d22dd0f5faa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18708
60779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1870860779
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3663589879
Short name T391
Test name
Test status
Simulation time 8368499628 ps
CPU time 8.02 seconds
Started Mar 17 01:41:55 PM PDT 24
Finished Mar 17 01:42:03 PM PDT 24
Peak memory 203692 kb
Host smart-1978bfed-cb6b-4958-a452-e061f6dd2922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36635
89879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3663589879
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.951298761
Short name T101
Test name
Test status
Simulation time 8446718189 ps
CPU time 8.07 seconds
Started Mar 17 01:41:53 PM PDT 24
Finished Mar 17 01:42:02 PM PDT 24
Peak memory 203712 kb
Host smart-f7412941-c4db-4bf5-aeee-10bf49536623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95129
8761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.951298761
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.46020280
Short name T715
Test name
Test status
Simulation time 8402127379 ps
CPU time 7.69 seconds
Started Mar 17 01:41:52 PM PDT 24
Finished Mar 17 01:42:00 PM PDT 24
Peak memory 203572 kb
Host smart-6f94fb65-3196-4896-81b9-61c790153fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46020
280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.46020280
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1417665541
Short name T630
Test name
Test status
Simulation time 8367936460 ps
CPU time 10.1 seconds
Started Mar 17 01:41:54 PM PDT 24
Finished Mar 17 01:42:04 PM PDT 24
Peak memory 203668 kb
Host smart-5f810778-7d39-4552-87ba-252fe0afeb14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14176
65541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1417665541
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.686302390
Short name T309
Test name
Test status
Simulation time 26098581 ps
CPU time 0.63 seconds
Started Mar 17 01:41:50 PM PDT 24
Finished Mar 17 01:41:51 PM PDT 24
Peak memory 203144 kb
Host smart-c9c8a30c-a1c4-4f4c-9fe7-7ade226da264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68630
2390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.686302390
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1256099581
Short name T706
Test name
Test status
Simulation time 8412299081 ps
CPU time 7.52 seconds
Started Mar 17 01:41:51 PM PDT 24
Finished Mar 17 01:42:00 PM PDT 24
Peak memory 203736 kb
Host smart-2aaa690a-d841-4708-9898-596d2eda7932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12560
99581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1256099581
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.1197583875
Short name T303
Test name
Test status
Simulation time 8384801794 ps
CPU time 8.08 seconds
Started Mar 17 01:41:51 PM PDT 24
Finished Mar 17 01:41:59 PM PDT 24
Peak memory 203724 kb
Host smart-9ea3f25a-8a13-4150-8269-ffb236f02e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11975
83875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.1197583875
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2191017410
Short name T460
Test name
Test status
Simulation time 8365130682 ps
CPU time 8.39 seconds
Started Mar 17 01:41:52 PM PDT 24
Finished Mar 17 01:42:01 PM PDT 24
Peak memory 203556 kb
Host smart-1d1c0ce7-e48d-4962-b69b-400762c9a40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21910
17410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2191017410
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2184498636
Short name T1
Test name
Test status
Simulation time 8476768373 ps
CPU time 7.37 seconds
Started Mar 17 01:41:47 PM PDT 24
Finished Mar 17 01:41:55 PM PDT 24
Peak memory 203720 kb
Host smart-91565226-792e-47e0-9da8-e4ca1945b9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21844
98636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2184498636
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.228309056
Short name T393
Test name
Test status
Simulation time 8369766467 ps
CPU time 8.31 seconds
Started Mar 17 01:41:50 PM PDT 24
Finished Mar 17 01:41:58 PM PDT 24
Peak memory 203860 kb
Host smart-d8ed4240-816f-4d43-9cdb-1c82dde10dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22830
9056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.228309056
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.225503494
Short name T43
Test name
Test status
Simulation time 71365005 ps
CPU time 2.01 seconds
Started Mar 17 01:41:57 PM PDT 24
Finished Mar 17 01:41:59 PM PDT 24
Peak memory 203696 kb
Host smart-3d078c8d-c4e6-44ae-8992-fb8dbb4fb677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22550
3494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.225503494
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.32602401
Short name T22
Test name
Test status
Simulation time 8364467852 ps
CPU time 8.16 seconds
Started Mar 17 01:42:00 PM PDT 24
Finished Mar 17 01:42:09 PM PDT 24
Peak memory 203496 kb
Host smart-5bd2144e-78e6-4811-8dde-1203dec38ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32602
401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.32602401
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3974216609
Short name T748
Test name
Test status
Simulation time 8460510690 ps
CPU time 8.43 seconds
Started Mar 17 01:42:04 PM PDT 24
Finished Mar 17 01:42:14 PM PDT 24
Peak memory 203664 kb
Host smart-ed60c36c-99c4-42cc-94ab-c1030f05bfe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39742
16609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3974216609
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.1193791290
Short name T271
Test name
Test status
Simulation time 8406473862 ps
CPU time 7.97 seconds
Started Mar 17 01:41:57 PM PDT 24
Finished Mar 17 01:42:05 PM PDT 24
Peak memory 203668 kb
Host smart-3abff736-b433-43f8-b8b4-3972c3a0715f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11937
91290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.1193791290
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2183783199
Short name T72
Test name
Test status
Simulation time 8366080666 ps
CPU time 8.62 seconds
Started Mar 17 01:41:55 PM PDT 24
Finished Mar 17 01:42:04 PM PDT 24
Peak memory 203668 kb
Host smart-47744db6-1a31-43f5-ae59-c4016aecd42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21837
83199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2183783199
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3559472826
Short name T690
Test name
Test status
Simulation time 8421907468 ps
CPU time 8.8 seconds
Started Mar 17 01:42:01 PM PDT 24
Finished Mar 17 01:42:10 PM PDT 24
Peak memory 203664 kb
Host smart-54429baf-e181-4dbb-8f85-f2e458b00900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35594
72826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3559472826
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.667729418
Short name T258
Test name
Test status
Simulation time 8368425605 ps
CPU time 7.36 seconds
Started Mar 17 01:41:57 PM PDT 24
Finished Mar 17 01:42:05 PM PDT 24
Peak memory 203684 kb
Host smart-1c7bf53e-ddaa-4459-af2c-397537f97c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66772
9418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.667729418
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.909462184
Short name T611
Test name
Test status
Simulation time 8402384041 ps
CPU time 7.75 seconds
Started Mar 17 01:41:59 PM PDT 24
Finished Mar 17 01:42:07 PM PDT 24
Peak memory 203564 kb
Host smart-5c3cbec1-863a-46ab-9006-0e71f0d9218c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90946
2184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.909462184
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1030128221
Short name T451
Test name
Test status
Simulation time 29386962 ps
CPU time 0.65 seconds
Started Mar 17 01:42:02 PM PDT 24
Finished Mar 17 01:42:02 PM PDT 24
Peak memory 203236 kb
Host smart-7177ace0-0d23-4222-b1e3-dd3c93d7203c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10301
28221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1030128221
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.859190891
Short name T483
Test name
Test status
Simulation time 8408262013 ps
CPU time 8.18 seconds
Started Mar 17 01:42:06 PM PDT 24
Finished Mar 17 01:42:14 PM PDT 24
Peak memory 203720 kb
Host smart-d0f3b99f-ac4d-4bee-a116-268102a4fa38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85919
0891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.859190891
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.4047195390
Short name T515
Test name
Test status
Simulation time 8391854323 ps
CPU time 7.48 seconds
Started Mar 17 01:41:58 PM PDT 24
Finished Mar 17 01:42:06 PM PDT 24
Peak memory 203636 kb
Host smart-e20ae0d6-fdc7-4381-b78c-c1088ee4ece9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40471
95390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.4047195390
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2432820738
Short name T737
Test name
Test status
Simulation time 8357165815 ps
CPU time 7.5 seconds
Started Mar 17 01:42:00 PM PDT 24
Finished Mar 17 01:42:08 PM PDT 24
Peak memory 203500 kb
Host smart-48f1ffeb-45e1-4dfc-967f-f0e4c0b3e817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24328
20738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2432820738
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.714077857
Short name T710
Test name
Test status
Simulation time 8479077202 ps
CPU time 7.81 seconds
Started Mar 17 01:41:52 PM PDT 24
Finished Mar 17 01:42:00 PM PDT 24
Peak memory 203740 kb
Host smart-caf5a2a0-12be-4ee7-baf8-b092c37bbe8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71407
7857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.714077857
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.934169926
Short name T330
Test name
Test status
Simulation time 8372802674 ps
CPU time 7.47 seconds
Started Mar 17 01:42:05 PM PDT 24
Finished Mar 17 01:42:13 PM PDT 24
Peak memory 203712 kb
Host smart-14f5efca-0c1c-45f5-83ea-79d1d6b47dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93416
9926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.934169926
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1321576262
Short name T275
Test name
Test status
Simulation time 35822623 ps
CPU time 1.06 seconds
Started Mar 17 01:42:04 PM PDT 24
Finished Mar 17 01:42:05 PM PDT 24
Peak memory 203716 kb
Host smart-726c3a31-4d40-43fa-bfba-6df188437521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13215
76262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1321576262
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3739658457
Short name T345
Test name
Test status
Simulation time 8358924851 ps
CPU time 9.53 seconds
Started Mar 17 01:42:09 PM PDT 24
Finished Mar 17 01:42:19 PM PDT 24
Peak memory 203520 kb
Host smart-c2b060cd-5701-481a-854a-164a93416c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37396
58457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3739658457
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.276125066
Short name T476
Test name
Test status
Simulation time 8421238309 ps
CPU time 7.71 seconds
Started Mar 17 01:42:03 PM PDT 24
Finished Mar 17 01:42:11 PM PDT 24
Peak memory 203728 kb
Host smart-463857f3-0ce2-4563-a4d7-6f1be827c725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27612
5066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.276125066
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.3597188594
Short name T262
Test name
Test status
Simulation time 8404691978 ps
CPU time 7.41 seconds
Started Mar 17 01:42:03 PM PDT 24
Finished Mar 17 01:42:11 PM PDT 24
Peak memory 203676 kb
Host smart-32b016f5-c03d-43e6-a17f-9481087a98ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35971
88594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.3597188594
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1744209127
Short name T717
Test name
Test status
Simulation time 8362950415 ps
CPU time 7.23 seconds
Started Mar 17 01:42:09 PM PDT 24
Finished Mar 17 01:42:17 PM PDT 24
Peak memory 203724 kb
Host smart-467a6824-aed7-457f-ab89-c550a5a811f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17442
09127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1744209127
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.4256672028
Short name T96
Test name
Test status
Simulation time 8429822248 ps
CPU time 10.15 seconds
Started Mar 17 01:42:06 PM PDT 24
Finished Mar 17 01:42:16 PM PDT 24
Peak memory 203724 kb
Host smart-c2e5e2ce-2b81-439b-bc57-e5a6e63397a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42566
72028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.4256672028
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1194522642
Short name T435
Test name
Test status
Simulation time 8372311840 ps
CPU time 7.69 seconds
Started Mar 17 01:42:09 PM PDT 24
Finished Mar 17 01:42:17 PM PDT 24
Peak memory 203564 kb
Host smart-6a146b58-704f-4921-9442-82d741565c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11945
22642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1194522642
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1208610677
Short name T420
Test name
Test status
Simulation time 8394576583 ps
CPU time 9.61 seconds
Started Mar 17 01:42:04 PM PDT 24
Finished Mar 17 01:42:14 PM PDT 24
Peak memory 203436 kb
Host smart-d579b3b5-d2b8-4219-9de7-9ee9d3b21307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12086
10677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1208610677
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3897416156
Short name T432
Test name
Test status
Simulation time 30571040 ps
CPU time 0.61 seconds
Started Mar 17 01:42:12 PM PDT 24
Finished Mar 17 01:42:13 PM PDT 24
Peak memory 203132 kb
Host smart-0ae7728d-1d5c-4a91-9bfe-611d3c803581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38974
16156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3897416156
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3116802983
Short name T366
Test name
Test status
Simulation time 8392855697 ps
CPU time 7.37 seconds
Started Mar 17 01:42:08 PM PDT 24
Finished Mar 17 01:42:16 PM PDT 24
Peak memory 203728 kb
Host smart-668d7c2b-c66e-4b47-99de-ee26e65a6a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31168
02983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3116802983
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.3804723087
Short name T208
Test name
Test status
Simulation time 8379338601 ps
CPU time 8.85 seconds
Started Mar 17 01:42:05 PM PDT 24
Finished Mar 17 01:42:14 PM PDT 24
Peak memory 203592 kb
Host smart-d7a0ccf8-cb62-4fcb-b135-f8a1920958d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38047
23087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.3804723087
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1975825540
Short name T572
Test name
Test status
Simulation time 8360642880 ps
CPU time 8 seconds
Started Mar 17 01:42:08 PM PDT 24
Finished Mar 17 01:42:16 PM PDT 24
Peak memory 203492 kb
Host smart-e519d621-bbd9-4cd4-8b72-7e8258b36db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19758
25540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1975825540
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2132576230
Short name T605
Test name
Test status
Simulation time 8475642099 ps
CPU time 9.17 seconds
Started Mar 17 01:42:02 PM PDT 24
Finished Mar 17 01:42:12 PM PDT 24
Peak memory 203720 kb
Host smart-19cc2d0b-6f33-46b5-bc39-799222e6a37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21325
76230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2132576230
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.19282487
Short name T358
Test name
Test status
Simulation time 8366437216 ps
CPU time 9.23 seconds
Started Mar 17 01:42:09 PM PDT 24
Finished Mar 17 01:42:18 PM PDT 24
Peak memory 203688 kb
Host smart-244c1f9f-6c12-46f3-80e6-8b3a11b4118a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19282
487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.19282487
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2935599770
Short name T520
Test name
Test status
Simulation time 31540225 ps
CPU time 0.95 seconds
Started Mar 17 01:42:09 PM PDT 24
Finished Mar 17 01:42:10 PM PDT 24
Peak memory 203616 kb
Host smart-dfbac76f-a831-4fd7-b8e2-9fd2eb20f107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29355
99770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2935599770
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.2348539005
Short name T177
Test name
Test status
Simulation time 8359352789 ps
CPU time 9.58 seconds
Started Mar 17 01:42:15 PM PDT 24
Finished Mar 17 01:42:24 PM PDT 24
Peak memory 203456 kb
Host smart-46a82654-891c-40b4-8fa9-f9976b8fede8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23485
39005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2348539005
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.161946011
Short name T502
Test name
Test status
Simulation time 8390304135 ps
CPU time 7.78 seconds
Started Mar 17 01:42:10 PM PDT 24
Finished Mar 17 01:42:18 PM PDT 24
Peak memory 203624 kb
Host smart-fdd76da6-e840-4efd-897d-2f6aaa7573bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16194
6011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.161946011
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2998891932
Short name T478
Test name
Test status
Simulation time 8405182506 ps
CPU time 7.18 seconds
Started Mar 17 01:42:08 PM PDT 24
Finished Mar 17 01:42:16 PM PDT 24
Peak memory 203712 kb
Host smart-836a899f-19c6-4830-b68a-34bb6ac83eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29988
91932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2998891932
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1717317190
Short name T624
Test name
Test status
Simulation time 8361954143 ps
CPU time 7.08 seconds
Started Mar 17 01:42:18 PM PDT 24
Finished Mar 17 01:42:26 PM PDT 24
Peak memory 203700 kb
Host smart-06885df2-28e1-434d-b10a-84cb6a9b8a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17173
17190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1717317190
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3646744524
Short name T530
Test name
Test status
Simulation time 8410432618 ps
CPU time 7.11 seconds
Started Mar 17 01:42:11 PM PDT 24
Finished Mar 17 01:42:18 PM PDT 24
Peak memory 203592 kb
Host smart-3de727ed-1a80-4756-90e4-7b77850903aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36467
44524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3646744524
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.4108732433
Short name T510
Test name
Test status
Simulation time 8369328808 ps
CPU time 7.27 seconds
Started Mar 17 01:42:10 PM PDT 24
Finished Mar 17 01:42:18 PM PDT 24
Peak memory 203520 kb
Host smart-29d5adeb-1b7c-45ee-93cc-9f2cea820006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41087
32433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.4108732433
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.1629587196
Short name T379
Test name
Test status
Simulation time 8379479613 ps
CPU time 8.02 seconds
Started Mar 17 01:42:10 PM PDT 24
Finished Mar 17 01:42:18 PM PDT 24
Peak memory 203580 kb
Host smart-7dccd8ab-19a0-4ddf-846c-a36abe84d608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16295
87196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.1629587196
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1712786341
Short name T325
Test name
Test status
Simulation time 27318891 ps
CPU time 0.63 seconds
Started Mar 17 01:42:17 PM PDT 24
Finished Mar 17 01:42:18 PM PDT 24
Peak memory 203172 kb
Host smart-d16ab6ec-314b-40a4-9c2c-d9673ecebed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17127
86341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1712786341
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1324856400
Short name T647
Test name
Test status
Simulation time 8427087784 ps
CPU time 9.56 seconds
Started Mar 17 01:42:12 PM PDT 24
Finished Mar 17 01:42:23 PM PDT 24
Peak memory 203596 kb
Host smart-9bcdbfa4-58c5-4989-ab8b-fa55b6fda30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13248
56400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1324856400
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.3682983161
Short name T378
Test name
Test status
Simulation time 8398596321 ps
CPU time 7.54 seconds
Started Mar 17 01:42:12 PM PDT 24
Finished Mar 17 01:42:19 PM PDT 24
Peak memory 203704 kb
Host smart-d99303a8-7d50-4492-a1c5-1691abe5be22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36829
83161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.3682983161
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.4213875267
Short name T442
Test name
Test status
Simulation time 8359185366 ps
CPU time 7.79 seconds
Started Mar 17 01:42:11 PM PDT 24
Finished Mar 17 01:42:20 PM PDT 24
Peak memory 203584 kb
Host smart-fbd36526-b48e-4974-812e-2af01cb16655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42138
75267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.4213875267
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.221778325
Short name T557
Test name
Test status
Simulation time 8474453815 ps
CPU time 9.1 seconds
Started Mar 17 01:42:10 PM PDT 24
Finished Mar 17 01:42:19 PM PDT 24
Peak memory 203708 kb
Host smart-2e247fd6-441d-48ae-a5f0-1ef031e264bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22177
8325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.221778325
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.3102284259
Short name T40
Test name
Test status
Simulation time 8373065958 ps
CPU time 7.83 seconds
Started Mar 17 01:42:15 PM PDT 24
Finished Mar 17 01:42:23 PM PDT 24
Peak memory 203664 kb
Host smart-cbf117af-fa7b-4040-bf05-cb7b80e9eca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31022
84259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3102284259
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1906800613
Short name T205
Test name
Test status
Simulation time 189152038 ps
CPU time 1.72 seconds
Started Mar 17 01:42:16 PM PDT 24
Finished Mar 17 01:42:18 PM PDT 24
Peak memory 203740 kb
Host smart-c152abf7-048e-41eb-9af7-4672f71f7d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19068
00613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1906800613
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2424213108
Short name T173
Test name
Test status
Simulation time 8362161642 ps
CPU time 7.37 seconds
Started Mar 17 01:42:15 PM PDT 24
Finished Mar 17 01:42:23 PM PDT 24
Peak memory 203512 kb
Host smart-93216bb8-2515-4e7e-8ed3-3608ebd10306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24242
13108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2424213108
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.439486388
Short name T734
Test name
Test status
Simulation time 8403015731 ps
CPU time 7.55 seconds
Started Mar 17 01:42:13 PM PDT 24
Finished Mar 17 01:42:21 PM PDT 24
Peak memory 203616 kb
Host smart-633a339b-c6ea-470c-8fb8-911dba80a8ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43948
6388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.439486388
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3212924469
Short name T326
Test name
Test status
Simulation time 8364986280 ps
CPU time 9.01 seconds
Started Mar 17 01:42:16 PM PDT 24
Finished Mar 17 01:42:25 PM PDT 24
Peak memory 203748 kb
Host smart-6ed177aa-2b33-41df-8285-0bf60b72d64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32129
24469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3212924469
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.853081519
Short name T84
Test name
Test status
Simulation time 8402628746 ps
CPU time 7.8 seconds
Started Mar 17 01:42:15 PM PDT 24
Finished Mar 17 01:42:23 PM PDT 24
Peak memory 203704 kb
Host smart-522c2eeb-3932-4d21-a091-7ff89b91a74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85308
1519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.853081519
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.1371425269
Short name T315
Test name
Test status
Simulation time 8367557241 ps
CPU time 8.75 seconds
Started Mar 17 01:42:16 PM PDT 24
Finished Mar 17 01:42:25 PM PDT 24
Peak memory 203588 kb
Host smart-bb3f7864-30b3-4922-be31-8d1db398883e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13714
25269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.1371425269
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2814565909
Short name T363
Test name
Test status
Simulation time 8400220960 ps
CPU time 7.31 seconds
Started Mar 17 01:42:13 PM PDT 24
Finished Mar 17 01:42:20 PM PDT 24
Peak memory 203504 kb
Host smart-6f86adc0-ac0e-40e4-adc1-85e1b97f7a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28145
65909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2814565909
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2748526582
Short name T439
Test name
Test status
Simulation time 27441010 ps
CPU time 0.62 seconds
Started Mar 17 01:42:15 PM PDT 24
Finished Mar 17 01:42:16 PM PDT 24
Peak memory 203208 kb
Host smart-a84e6678-4e48-4d88-a2ba-098342c741b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27485
26582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2748526582
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.2832307468
Short name T584
Test name
Test status
Simulation time 8436631451 ps
CPU time 7.96 seconds
Started Mar 17 01:42:15 PM PDT 24
Finished Mar 17 01:42:23 PM PDT 24
Peak memory 203644 kb
Host smart-1dd0e4c9-8487-427f-9fba-a37f3432232b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28323
07468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2832307468
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.2251966680
Short name T278
Test name
Test status
Simulation time 8377146160 ps
CPU time 7.59 seconds
Started Mar 17 01:42:15 PM PDT 24
Finished Mar 17 01:42:23 PM PDT 24
Peak memory 203636 kb
Host smart-a7f9570e-01b3-4af2-81b4-dec625160791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22519
66680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.2251966680
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1927515031
Short name T231
Test name
Test status
Simulation time 8359996182 ps
CPU time 8.01 seconds
Started Mar 17 01:42:17 PM PDT 24
Finished Mar 17 01:42:25 PM PDT 24
Peak memory 203584 kb
Host smart-1446e04f-acca-426e-9179-2db6a92369e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19275
15031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1927515031
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.388379325
Short name T470
Test name
Test status
Simulation time 8367276304 ps
CPU time 9.99 seconds
Started Mar 17 01:38:21 PM PDT 24
Finished Mar 17 01:38:31 PM PDT 24
Peak memory 203700 kb
Host smart-7b76c325-3628-40d1-86e6-98e163cc59dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38837
9325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.388379325
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.513933393
Short name T361
Test name
Test status
Simulation time 40259735 ps
CPU time 1.13 seconds
Started Mar 17 01:38:27 PM PDT 24
Finished Mar 17 01:38:28 PM PDT 24
Peak memory 203504 kb
Host smart-ead37a9c-b715-4e5e-97db-177a5de72b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51393
3393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.513933393
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3775738444
Short name T160
Test name
Test status
Simulation time 8355028886 ps
CPU time 7.18 seconds
Started Mar 17 01:38:26 PM PDT 24
Finished Mar 17 01:38:33 PM PDT 24
Peak memory 203472 kb
Host smart-6a1fcd47-1b19-4039-8cef-5c7c34a165bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37757
38444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3775738444
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3674533116
Short name T129
Test name
Test status
Simulation time 8400641003 ps
CPU time 7.28 seconds
Started Mar 17 01:38:28 PM PDT 24
Finished Mar 17 01:38:36 PM PDT 24
Peak memory 203712 kb
Host smart-09beac07-b64f-47e1-a6e8-cffbda837caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36745
33116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3674533116
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.769778099
Short name T407
Test name
Test status
Simulation time 8408352134 ps
CPU time 7.88 seconds
Started Mar 17 01:38:27 PM PDT 24
Finished Mar 17 01:38:35 PM PDT 24
Peak memory 203668 kb
Host smart-6a3168e0-4250-4651-8b45-c5dab884f80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76977
8099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.769778099
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.787830045
Short name T579
Test name
Test status
Simulation time 8364396668 ps
CPU time 9.62 seconds
Started Mar 17 01:38:26 PM PDT 24
Finished Mar 17 01:38:36 PM PDT 24
Peak memory 203692 kb
Host smart-2f6c3045-0b57-4143-a632-716098d3b779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78783
0045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.787830045
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2252479264
Short name T687
Test name
Test status
Simulation time 8398849086 ps
CPU time 7.01 seconds
Started Mar 17 01:38:25 PM PDT 24
Finished Mar 17 01:38:32 PM PDT 24
Peak memory 203668 kb
Host smart-21147f46-2b58-4fda-84d8-7bec4ff4eb5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22524
79264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2252479264
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3330707344
Short name T369
Test name
Test status
Simulation time 8373674480 ps
CPU time 8.97 seconds
Started Mar 17 01:38:30 PM PDT 24
Finished Mar 17 01:38:39 PM PDT 24
Peak memory 203552 kb
Host smart-63441da6-e9b0-4cd4-8596-2b42e1b1fb3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33307
07344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3330707344
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.542463167
Short name T405
Test name
Test status
Simulation time 32298733 ps
CPU time 0.64 seconds
Started Mar 17 01:38:27 PM PDT 24
Finished Mar 17 01:38:28 PM PDT 24
Peak memory 203120 kb
Host smart-098d5c91-f27f-4571-9406-10ae316f162c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54246
3167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.542463167
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.3970255913
Short name T578
Test name
Test status
Simulation time 8394734879 ps
CPU time 7.79 seconds
Started Mar 17 01:38:27 PM PDT 24
Finished Mar 17 01:38:35 PM PDT 24
Peak memory 203712 kb
Host smart-48dcb600-a390-4369-afd7-b995af45edcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39702
55913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3970255913
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.4225660984
Short name T347
Test name
Test status
Simulation time 8394339657 ps
CPU time 8.13 seconds
Started Mar 17 01:38:26 PM PDT 24
Finished Mar 17 01:38:34 PM PDT 24
Peak memory 203620 kb
Host smart-b396ee45-672b-431a-a18d-2015365bc56a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42256
60984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.4225660984
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.384841191
Short name T438
Test name
Test status
Simulation time 8358133387 ps
CPU time 7.8 seconds
Started Mar 17 01:38:27 PM PDT 24
Finished Mar 17 01:38:35 PM PDT 24
Peak memory 203596 kb
Host smart-943ace1d-0196-4615-83ae-8afeb417f2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38484
1191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.384841191
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.3159001764
Short name T467
Test name
Test status
Simulation time 8477155386 ps
CPU time 7.62 seconds
Started Mar 17 01:38:20 PM PDT 24
Finished Mar 17 01:38:27 PM PDT 24
Peak memory 203732 kb
Host smart-edf43de5-8e0e-42b8-999f-9954dd589858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31590
01764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3159001764
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1019176437
Short name T499
Test name
Test status
Simulation time 8367789133 ps
CPU time 7.1 seconds
Started Mar 17 01:42:17 PM PDT 24
Finished Mar 17 01:42:24 PM PDT 24
Peak memory 203688 kb
Host smart-63093636-798b-4993-8606-9be0afd1e98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10191
76437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1019176437
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2806742688
Short name T229
Test name
Test status
Simulation time 107784759 ps
CPU time 1.15 seconds
Started Mar 17 01:42:16 PM PDT 24
Finished Mar 17 01:42:17 PM PDT 24
Peak memory 203492 kb
Host smart-11120f34-83c4-4641-9ed5-8b4a239748ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28067
42688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2806742688
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3738064296
Short name T176
Test name
Test status
Simulation time 8355903995 ps
CPU time 7.94 seconds
Started Mar 17 01:42:20 PM PDT 24
Finished Mar 17 01:42:30 PM PDT 24
Peak memory 203464 kb
Host smart-470c5f91-a783-4161-9262-019eb3370573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37380
64296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3738064296
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.4030960835
Short name T124
Test name
Test status
Simulation time 8452099372 ps
CPU time 8.83 seconds
Started Mar 17 01:42:14 PM PDT 24
Finished Mar 17 01:42:23 PM PDT 24
Peak memory 203740 kb
Host smart-c9bf662d-3606-4a9d-b408-9377f42739f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40309
60835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.4030960835
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2125156057
Short name T344
Test name
Test status
Simulation time 8410048509 ps
CPU time 7.68 seconds
Started Mar 17 01:42:17 PM PDT 24
Finished Mar 17 01:42:25 PM PDT 24
Peak memory 203752 kb
Host smart-8f885820-630f-4864-bbf2-a2020c538f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21251
56057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2125156057
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.4112332400
Short name T665
Test name
Test status
Simulation time 8364242688 ps
CPU time 9.48 seconds
Started Mar 17 01:42:15 PM PDT 24
Finished Mar 17 01:42:24 PM PDT 24
Peak memory 203720 kb
Host smart-433386ac-e0a2-4804-bcee-42eab6777f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41123
32400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.4112332400
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.788670403
Short name T85
Test name
Test status
Simulation time 8426657150 ps
CPU time 8.61 seconds
Started Mar 17 01:42:14 PM PDT 24
Finished Mar 17 01:42:22 PM PDT 24
Peak memory 203724 kb
Host smart-33e5a6ab-6475-4a87-81dc-f751f4294a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78867
0403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.788670403
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.861287869
Short name T419
Test name
Test status
Simulation time 8378603032 ps
CPU time 8.98 seconds
Started Mar 17 01:42:15 PM PDT 24
Finished Mar 17 01:42:24 PM PDT 24
Peak memory 203520 kb
Host smart-5b81968d-f494-466e-8a8d-d307627be65a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86128
7869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.861287869
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3448821731
Short name T261
Test name
Test status
Simulation time 8374399469 ps
CPU time 7.75 seconds
Started Mar 17 01:42:15 PM PDT 24
Finished Mar 17 01:42:23 PM PDT 24
Peak memory 203516 kb
Host smart-70d8974e-f9b2-4487-9520-acfe94ee7f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34488
21731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3448821731
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2902743660
Short name T494
Test name
Test status
Simulation time 26206494 ps
CPU time 0.63 seconds
Started Mar 17 01:42:20 PM PDT 24
Finished Mar 17 01:42:23 PM PDT 24
Peak memory 203300 kb
Host smart-43c2849f-465e-4467-8b34-eb0e099fa2fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29027
43660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2902743660
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.4035260398
Short name T437
Test name
Test status
Simulation time 8403530509 ps
CPU time 7.66 seconds
Started Mar 17 01:42:15 PM PDT 24
Finished Mar 17 01:42:23 PM PDT 24
Peak memory 203748 kb
Host smart-cd1965f8-84b1-4ab3-a28c-4dc37d5b8137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40352
60398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.4035260398
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.2514900418
Short name T249
Test name
Test status
Simulation time 8368396025 ps
CPU time 8.98 seconds
Started Mar 17 01:42:21 PM PDT 24
Finished Mar 17 01:42:31 PM PDT 24
Peak memory 203728 kb
Host smart-faa18e39-bc2b-4687-9050-c58625b42ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25149
00418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.2514900418
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3093583831
Short name T718
Test name
Test status
Simulation time 8361658073 ps
CPU time 7.22 seconds
Started Mar 17 01:42:22 PM PDT 24
Finished Mar 17 01:42:29 PM PDT 24
Peak memory 203676 kb
Host smart-cfeb8888-73b3-49ea-bc92-9a0ef649ed4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30935
83831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3093583831
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.587859207
Short name T746
Test name
Test status
Simulation time 8474520699 ps
CPU time 7.91 seconds
Started Mar 17 01:42:13 PM PDT 24
Finished Mar 17 01:42:21 PM PDT 24
Peak memory 203708 kb
Host smart-11039e05-89c4-4363-a435-7d2345d90dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58785
9207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.587859207
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2691533341
Short name T722
Test name
Test status
Simulation time 8364633727 ps
CPU time 9.33 seconds
Started Mar 17 01:42:21 PM PDT 24
Finished Mar 17 01:42:31 PM PDT 24
Peak memory 203648 kb
Host smart-7de28d80-5de1-4ad6-a2df-2480f75b60f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26915
33341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2691533341
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.545143245
Short name T625
Test name
Test status
Simulation time 174074187 ps
CPU time 1.91 seconds
Started Mar 17 01:42:22 PM PDT 24
Finished Mar 17 01:42:25 PM PDT 24
Peak memory 203632 kb
Host smart-49396df0-926a-4a2a-b307-4dee38dddf55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54514
3245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.545143245
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.852765368
Short name T163
Test name
Test status
Simulation time 8360620269 ps
CPU time 8.36 seconds
Started Mar 17 01:42:21 PM PDT 24
Finished Mar 17 01:42:30 PM PDT 24
Peak memory 203460 kb
Host smart-5c21abd3-e396-4b03-84b2-00bdf5106ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85276
5368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.852765368
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.259496900
Short name T537
Test name
Test status
Simulation time 8401500415 ps
CPU time 8.17 seconds
Started Mar 17 01:42:20 PM PDT 24
Finished Mar 17 01:42:29 PM PDT 24
Peak memory 203640 kb
Host smart-1d4685a1-983f-4df0-b9ab-89c138673c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25949
6900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.259496900
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.543354863
Short name T594
Test name
Test status
Simulation time 8410936977 ps
CPU time 9.18 seconds
Started Mar 17 01:42:23 PM PDT 24
Finished Mar 17 01:42:33 PM PDT 24
Peak memory 203692 kb
Host smart-3643eca3-e521-4dbb-83c2-d51000c3aaa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54335
4863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.543354863
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.875991166
Short name T646
Test name
Test status
Simulation time 8363990150 ps
CPU time 8.33 seconds
Started Mar 17 01:42:20 PM PDT 24
Finished Mar 17 01:42:30 PM PDT 24
Peak memory 203712 kb
Host smart-a66c442e-372b-4795-8f4f-d455cdc773a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87599
1166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.875991166
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.699220593
Short name T91
Test name
Test status
Simulation time 8426218155 ps
CPU time 7.41 seconds
Started Mar 17 01:42:22 PM PDT 24
Finished Mar 17 01:42:31 PM PDT 24
Peak memory 203700 kb
Host smart-505ce8cb-1685-46aa-9110-7b22eef41173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69922
0593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.699220593
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.323019869
Short name T340
Test name
Test status
Simulation time 8372623801 ps
CPU time 8.7 seconds
Started Mar 17 01:42:21 PM PDT 24
Finished Mar 17 01:42:30 PM PDT 24
Peak memory 203712 kb
Host smart-35bfc098-642f-41c9-ba89-f24f3cf1b771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32301
9869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.323019869
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1463112674
Short name T534
Test name
Test status
Simulation time 8400732873 ps
CPU time 7.69 seconds
Started Mar 17 01:42:21 PM PDT 24
Finished Mar 17 01:42:30 PM PDT 24
Peak memory 203524 kb
Host smart-3420c7ed-f9ac-4dac-a6a9-d32fa1d58e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14631
12674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1463112674
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1969827122
Short name T551
Test name
Test status
Simulation time 21412344 ps
CPU time 0.61 seconds
Started Mar 17 01:42:25 PM PDT 24
Finished Mar 17 01:42:26 PM PDT 24
Peak memory 203156 kb
Host smart-d45bda29-6e24-4cc4-a242-61bc7263503e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19698
27122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1969827122
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.865124610
Short name T114
Test name
Test status
Simulation time 8410106199 ps
CPU time 8.32 seconds
Started Mar 17 01:42:21 PM PDT 24
Finished Mar 17 01:42:30 PM PDT 24
Peak memory 203600 kb
Host smart-cea05c12-40e7-49c4-8fee-bba61f732bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86512
4610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.865124610
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.2192079274
Short name T201
Test name
Test status
Simulation time 8389656698 ps
CPU time 7.2 seconds
Started Mar 17 01:42:24 PM PDT 24
Finished Mar 17 01:42:32 PM PDT 24
Peak memory 203732 kb
Host smart-c1ba307f-af0a-400a-8259-524d6d2d7a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21920
79274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.2192079274
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2088644923
Short name T561
Test name
Test status
Simulation time 8356869363 ps
CPU time 7.92 seconds
Started Mar 17 01:42:21 PM PDT 24
Finished Mar 17 01:42:30 PM PDT 24
Peak memory 203644 kb
Host smart-4997f556-a556-4c04-9b7d-aa3b8f9922aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20886
44923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2088644923
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3494048167
Short name T42
Test name
Test status
Simulation time 8476832979 ps
CPU time 7.86 seconds
Started Mar 17 01:42:21 PM PDT 24
Finished Mar 17 01:42:30 PM PDT 24
Peak memory 203736 kb
Host smart-c07af5d3-7e26-4117-bc0d-b9c64a4d051b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34940
48167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3494048167
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.4284910619
Short name T501
Test name
Test status
Simulation time 8368205646 ps
CPU time 7.47 seconds
Started Mar 17 01:42:24 PM PDT 24
Finished Mar 17 01:42:32 PM PDT 24
Peak memory 203696 kb
Host smart-82338b7a-58c5-41b5-9c04-290e85b06574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42849
10619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.4284910619
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.367472625
Short name T286
Test name
Test status
Simulation time 135174558 ps
CPU time 1.32 seconds
Started Mar 17 01:42:30 PM PDT 24
Finished Mar 17 01:42:32 PM PDT 24
Peak memory 203744 kb
Host smart-11369953-12fe-4d2e-8113-20063ccc0f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36747
2625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.367472625
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1086188379
Short name T174
Test name
Test status
Simulation time 8357236065 ps
CPU time 9.11 seconds
Started Mar 17 01:42:34 PM PDT 24
Finished Mar 17 01:42:43 PM PDT 24
Peak memory 203472 kb
Host smart-f625ae5b-9777-4775-bd87-5803d3ad8538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10861
88379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1086188379
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1976054884
Short name T132
Test name
Test status
Simulation time 8390067553 ps
CPU time 8.02 seconds
Started Mar 17 01:42:25 PM PDT 24
Finished Mar 17 01:42:33 PM PDT 24
Peak memory 203704 kb
Host smart-108edb2d-559c-4a9f-8a77-a88b0adc8ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19760
54884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1976054884
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3805240402
Short name T543
Test name
Test status
Simulation time 8405336371 ps
CPU time 7.15 seconds
Started Mar 17 01:42:34 PM PDT 24
Finished Mar 17 01:42:41 PM PDT 24
Peak memory 203652 kb
Host smart-7270f994-a97f-40c4-95ab-1a04a60bbca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38052
40402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3805240402
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3853185355
Short name T544
Test name
Test status
Simulation time 8362912782 ps
CPU time 7.5 seconds
Started Mar 17 01:42:28 PM PDT 24
Finished Mar 17 01:42:36 PM PDT 24
Peak memory 203732 kb
Host smart-589654d0-b45f-4969-8ae9-74230fc58059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38531
85355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3853185355
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.3151534943
Short name T107
Test name
Test status
Simulation time 8407087226 ps
CPU time 7.6 seconds
Started Mar 17 01:42:26 PM PDT 24
Finished Mar 17 01:42:34 PM PDT 24
Peak memory 203600 kb
Host smart-07d6b7e5-f088-41fb-9d32-638b9d8594f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31515
34943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3151534943
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.4074123124
Short name T481
Test name
Test status
Simulation time 8373527933 ps
CPU time 7.87 seconds
Started Mar 17 01:42:34 PM PDT 24
Finished Mar 17 01:42:42 PM PDT 24
Peak memory 203496 kb
Host smart-e2b5d2dc-9053-46b0-8583-74bf5f80515c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40741
23124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.4074123124
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.2100030702
Short name T15
Test name
Test status
Simulation time 8365340636 ps
CPU time 7.83 seconds
Started Mar 17 01:42:26 PM PDT 24
Finished Mar 17 01:42:34 PM PDT 24
Peak memory 203696 kb
Host smart-072a900c-a9f2-4473-95dd-07002d51f89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21000
30702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.2100030702
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3943726086
Short name T468
Test name
Test status
Simulation time 29592890 ps
CPU time 0.68 seconds
Started Mar 17 01:42:26 PM PDT 24
Finished Mar 17 01:42:28 PM PDT 24
Peak memory 203156 kb
Host smart-2bde9a36-8f9b-4248-8c20-a71b0670047f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39437
26086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3943726086
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.4080092449
Short name T497
Test name
Test status
Simulation time 8426369480 ps
CPU time 8.06 seconds
Started Mar 17 01:42:31 PM PDT 24
Finished Mar 17 01:42:40 PM PDT 24
Peak memory 203676 kb
Host smart-b301b85a-b018-48e4-93cb-ada50fc417a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40800
92449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.4080092449
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.1943639896
Short name T549
Test name
Test status
Simulation time 8393596720 ps
CPU time 7.77 seconds
Started Mar 17 01:42:29 PM PDT 24
Finished Mar 17 01:42:37 PM PDT 24
Peak memory 203704 kb
Host smart-8c10252c-9578-47f7-b51b-aea211bb195c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19436
39896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.1943639896
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.667574558
Short name T14
Test name
Test status
Simulation time 8363754085 ps
CPU time 7.29 seconds
Started Mar 17 01:42:28 PM PDT 24
Finished Mar 17 01:42:35 PM PDT 24
Peak memory 203676 kb
Host smart-f3b8d7a1-39ed-41ff-abc8-b2c8cd42f46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66757
4558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.667574558
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2353802427
Short name T609
Test name
Test status
Simulation time 8472871074 ps
CPU time 7.48 seconds
Started Mar 17 01:42:23 PM PDT 24
Finished Mar 17 01:42:31 PM PDT 24
Peak memory 203724 kb
Host smart-20fac3a6-c9aa-4d61-bb8b-df99c28c90c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23538
02427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2353802427
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.954478191
Short name T514
Test name
Test status
Simulation time 8368908910 ps
CPU time 7.63 seconds
Started Mar 17 01:42:28 PM PDT 24
Finished Mar 17 01:42:36 PM PDT 24
Peak memory 203704 kb
Host smart-08fbe906-8aa6-4cfd-88d6-66f3c571dc13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95447
8191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.954478191
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1420459840
Short name T203
Test name
Test status
Simulation time 73669585 ps
CPU time 1.89 seconds
Started Mar 17 01:42:27 PM PDT 24
Finished Mar 17 01:42:30 PM PDT 24
Peak memory 203728 kb
Host smart-4eb0b93b-921b-4f87-81b9-df8d3cbde853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14204
59840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1420459840
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.3506869960
Short name T170
Test name
Test status
Simulation time 8357872732 ps
CPU time 7.31 seconds
Started Mar 17 01:42:26 PM PDT 24
Finished Mar 17 01:42:34 PM PDT 24
Peak memory 203556 kb
Host smart-4304b42d-80ad-473e-9d74-1502e3cdf930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35068
69960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.3506869960
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2833131735
Short name T517
Test name
Test status
Simulation time 8397443278 ps
CPU time 8.06 seconds
Started Mar 17 01:42:25 PM PDT 24
Finished Mar 17 01:42:33 PM PDT 24
Peak memory 203676 kb
Host smart-2b86ca46-7ce3-4169-94b0-fec9597e5b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28331
31735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2833131735
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.184872719
Short name T16
Test name
Test status
Simulation time 8404965718 ps
CPU time 9.28 seconds
Started Mar 17 01:42:28 PM PDT 24
Finished Mar 17 01:42:38 PM PDT 24
Peak memory 203712 kb
Host smart-54780aa7-60fa-4117-b2b8-e57eaf5ffd64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18487
2719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.184872719
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.243342805
Short name T398
Test name
Test status
Simulation time 8366697632 ps
CPU time 7.86 seconds
Started Mar 17 01:42:26 PM PDT 24
Finished Mar 17 01:42:34 PM PDT 24
Peak memory 203832 kb
Host smart-bc164349-8675-4376-ba14-5974c4c4cdc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24334
2805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.243342805
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2799731549
Short name T112
Test name
Test status
Simulation time 8400570618 ps
CPU time 7.3 seconds
Started Mar 17 01:42:28 PM PDT 24
Finished Mar 17 01:42:36 PM PDT 24
Peak memory 203676 kb
Host smart-1fb996cd-5c52-4d98-9abe-62c81f799ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27997
31549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2799731549
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2539636509
Short name T582
Test name
Test status
Simulation time 8389699801 ps
CPU time 7.29 seconds
Started Mar 17 01:42:32 PM PDT 24
Finished Mar 17 01:42:39 PM PDT 24
Peak memory 203520 kb
Host smart-af0abdf4-be8d-464b-9f79-331697b24595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25396
36509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2539636509
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.313328373
Short name T285
Test name
Test status
Simulation time 8388954554 ps
CPU time 7.02 seconds
Started Mar 17 01:42:27 PM PDT 24
Finished Mar 17 01:42:34 PM PDT 24
Peak memory 203708 kb
Host smart-40473cac-4fed-48e0-afa5-fd784ffc6930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31332
8373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.313328373
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.710163630
Short name T24
Test name
Test status
Simulation time 25487444 ps
CPU time 0.62 seconds
Started Mar 17 01:42:28 PM PDT 24
Finished Mar 17 01:42:29 PM PDT 24
Peak memory 203276 kb
Host smart-25c8c733-0171-45cb-a16d-b7ae083ae1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71016
3630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.710163630
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3974230676
Short name T638
Test name
Test status
Simulation time 8378624577 ps
CPU time 7.16 seconds
Started Mar 17 01:42:34 PM PDT 24
Finished Mar 17 01:42:41 PM PDT 24
Peak memory 203660 kb
Host smart-c0b38142-4a96-4fe8-b97d-4c9ba52fa691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39742
30676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3974230676
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.3338570872
Short name T365
Test name
Test status
Simulation time 8390847897 ps
CPU time 7.33 seconds
Started Mar 17 01:42:26 PM PDT 24
Finished Mar 17 01:42:34 PM PDT 24
Peak memory 203720 kb
Host smart-ed25da8d-fcea-4520-abc9-c39fe57a6a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33385
70872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.3338570872
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2929280933
Short name T252
Test name
Test status
Simulation time 8357241348 ps
CPU time 7.37 seconds
Started Mar 17 01:42:27 PM PDT 24
Finished Mar 17 01:42:36 PM PDT 24
Peak memory 203576 kb
Host smart-81de31f1-be42-4cbb-8147-ca0ca2d446d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29292
80933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2929280933
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3375558578
Short name T139
Test name
Test status
Simulation time 8477257973 ps
CPU time 9.87 seconds
Started Mar 17 01:42:25 PM PDT 24
Finished Mar 17 01:42:35 PM PDT 24
Peak memory 203692 kb
Host smart-118a2385-daa1-4c86-b78e-73c162dac323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33755
58578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3375558578
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2103872096
Short name T523
Test name
Test status
Simulation time 8369237093 ps
CPU time 7.81 seconds
Started Mar 17 01:42:31 PM PDT 24
Finished Mar 17 01:42:39 PM PDT 24
Peak memory 203676 kb
Host smart-61529aeb-2eb1-437d-872a-39f8efdf5d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21038
72096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2103872096
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.185262516
Short name T175
Test name
Test status
Simulation time 8360764537 ps
CPU time 7.82 seconds
Started Mar 17 01:42:35 PM PDT 24
Finished Mar 17 01:42:43 PM PDT 24
Peak memory 203484 kb
Host smart-85664a30-c1a5-4d4e-9be5-6bbad24ef4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18526
2516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.185262516
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.3530299950
Short name T121
Test name
Test status
Simulation time 8446372948 ps
CPU time 7.62 seconds
Started Mar 17 01:42:33 PM PDT 24
Finished Mar 17 01:42:41 PM PDT 24
Peak memory 203628 kb
Host smart-5fcd3526-d5c6-4b47-bf91-9f36d6f3fa2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35302
99950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.3530299950
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1425190380
Short name T401
Test name
Test status
Simulation time 8407370130 ps
CPU time 9.74 seconds
Started Mar 17 01:42:37 PM PDT 24
Finished Mar 17 01:42:47 PM PDT 24
Peak memory 203596 kb
Host smart-104f229f-5b86-4480-8555-efbbec142b90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14251
90380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1425190380
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3120053082
Short name T301
Test name
Test status
Simulation time 8366543115 ps
CPU time 7.44 seconds
Started Mar 17 01:42:33 PM PDT 24
Finished Mar 17 01:42:40 PM PDT 24
Peak memory 203668 kb
Host smart-d0250635-9d75-46bb-b661-15cd5666b6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31200
53082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3120053082
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3758777253
Short name T94
Test name
Test status
Simulation time 8447031406 ps
CPU time 9.88 seconds
Started Mar 17 01:42:34 PM PDT 24
Finished Mar 17 01:42:44 PM PDT 24
Peak memory 203684 kb
Host smart-5d3e9c4c-58d3-4eed-b28c-5aa89c994288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37587
77253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3758777253
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.4042615436
Short name T707
Test name
Test status
Simulation time 8385714460 ps
CPU time 7.56 seconds
Started Mar 17 01:42:34 PM PDT 24
Finished Mar 17 01:42:42 PM PDT 24
Peak memory 203736 kb
Host smart-62ee5152-8407-4670-9ff3-579170c5a769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40426
15436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.4042615436
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3880184904
Short name T440
Test name
Test status
Simulation time 8378535860 ps
CPU time 7.73 seconds
Started Mar 17 01:42:33 PM PDT 24
Finished Mar 17 01:42:41 PM PDT 24
Peak memory 203520 kb
Host smart-96700203-2276-4ec2-a866-72fb7a8d4824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38801
84904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3880184904
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.739532958
Short name T383
Test name
Test status
Simulation time 30902779 ps
CPU time 0.7 seconds
Started Mar 17 01:42:35 PM PDT 24
Finished Mar 17 01:42:36 PM PDT 24
Peak memory 203252 kb
Host smart-6d0016ce-e9da-4659-864d-922290be2cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73953
2958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.739532958
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.604661228
Short name T123
Test name
Test status
Simulation time 8408880942 ps
CPU time 7.65 seconds
Started Mar 17 01:42:33 PM PDT 24
Finished Mar 17 01:42:41 PM PDT 24
Peak memory 203680 kb
Host smart-d99c79a8-2693-46f9-a292-6a812f69c82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60466
1228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.604661228
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.3378475299
Short name T679
Test name
Test status
Simulation time 8391292091 ps
CPU time 7.35 seconds
Started Mar 17 01:42:33 PM PDT 24
Finished Mar 17 01:42:40 PM PDT 24
Peak memory 203708 kb
Host smart-96370d26-d4d1-459b-8574-471e7c5ca7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33784
75299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.3378475299
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3129674044
Short name T13
Test name
Test status
Simulation time 8363007498 ps
CPU time 7.51 seconds
Started Mar 17 01:42:33 PM PDT 24
Finished Mar 17 01:42:41 PM PDT 24
Peak memory 203588 kb
Host smart-8b8b549b-935f-4ae2-b5ac-3c5ca9cb16ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31296
74044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3129674044
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.4089153024
Short name T628
Test name
Test status
Simulation time 8367262163 ps
CPU time 7.26 seconds
Started Mar 17 01:42:36 PM PDT 24
Finished Mar 17 01:42:44 PM PDT 24
Peak memory 203704 kb
Host smart-e200be63-82a3-4696-b6d8-251ce95a6fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40891
53024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.4089153024
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1315874538
Short name T342
Test name
Test status
Simulation time 143749661 ps
CPU time 1.6 seconds
Started Mar 17 01:42:35 PM PDT 24
Finished Mar 17 01:42:37 PM PDT 24
Peak memory 203612 kb
Host smart-300960e3-34e5-4eed-8a7a-4d0b97818fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13158
74538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1315874538
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2396176954
Short name T153
Test name
Test status
Simulation time 8360292624 ps
CPU time 9.09 seconds
Started Mar 17 01:42:34 PM PDT 24
Finished Mar 17 01:42:43 PM PDT 24
Peak memory 203532 kb
Host smart-10ed79d9-2011-4a39-96a7-9fe1f6b28493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23961
76954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2396176954
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.473029648
Short name T130
Test name
Test status
Simulation time 8410503189 ps
CPU time 8.44 seconds
Started Mar 17 01:42:35 PM PDT 24
Finished Mar 17 01:42:44 PM PDT 24
Peak memory 203600 kb
Host smart-cf6c4968-856f-4eba-9fc9-e6a6fc542358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47302
9648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.473029648
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3083939232
Short name T590
Test name
Test status
Simulation time 8407715842 ps
CPU time 7.49 seconds
Started Mar 17 01:42:34 PM PDT 24
Finished Mar 17 01:42:42 PM PDT 24
Peak memory 203688 kb
Host smart-1517c357-3167-47e6-bb74-0c5b21d61e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30839
39232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3083939232
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3336402320
Short name T736
Test name
Test status
Simulation time 8361877659 ps
CPU time 7.08 seconds
Started Mar 17 01:42:37 PM PDT 24
Finished Mar 17 01:42:44 PM PDT 24
Peak memory 203588 kb
Host smart-dcac1cf1-f5bf-43c7-84b4-2eda8fc731c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33364
02320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3336402320
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2192797820
Short name T580
Test name
Test status
Simulation time 8377705748 ps
CPU time 8.06 seconds
Started Mar 17 01:42:34 PM PDT 24
Finished Mar 17 01:42:42 PM PDT 24
Peak memory 203720 kb
Host smart-7065a6cc-26d1-4396-84a3-829c8e628d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21927
97820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2192797820
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2044852484
Short name T313
Test name
Test status
Simulation time 8406982138 ps
CPU time 8.4 seconds
Started Mar 17 01:42:37 PM PDT 24
Finished Mar 17 01:42:45 PM PDT 24
Peak memory 203400 kb
Host smart-6f391b0a-6c7a-4e8a-b879-caa499d05b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20448
52484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2044852484
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.3811332743
Short name T635
Test name
Test status
Simulation time 27710833 ps
CPU time 0.67 seconds
Started Mar 17 01:42:33 PM PDT 24
Finished Mar 17 01:42:34 PM PDT 24
Peak memory 203208 kb
Host smart-66541aa3-28a6-4970-b540-839afecf5829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38113
32743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3811332743
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.4112540936
Short name T449
Test name
Test status
Simulation time 8455754079 ps
CPU time 7.16 seconds
Started Mar 17 01:42:32 PM PDT 24
Finished Mar 17 01:42:39 PM PDT 24
Peak memory 203684 kb
Host smart-b248c520-52ca-4517-9bef-b242445123eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41125
40936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.4112540936
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.4136646288
Short name T536
Test name
Test status
Simulation time 8396921530 ps
CPU time 8.22 seconds
Started Mar 17 01:42:35 PM PDT 24
Finished Mar 17 01:42:43 PM PDT 24
Peak memory 203724 kb
Host smart-6ff6a803-d62f-4441-83a9-e3a326d5b859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41366
46288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.4136646288
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2128106957
Short name T639
Test name
Test status
Simulation time 8360793662 ps
CPU time 9.24 seconds
Started Mar 17 01:42:34 PM PDT 24
Finished Mar 17 01:42:43 PM PDT 24
Peak memory 203720 kb
Host smart-4878bb8f-36f0-447f-9ac2-5c3a0801bbc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21281
06957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2128106957
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1327373758
Short name T224
Test name
Test status
Simulation time 8476818371 ps
CPU time 7.98 seconds
Started Mar 17 01:42:35 PM PDT 24
Finished Mar 17 01:42:43 PM PDT 24
Peak memory 203720 kb
Host smart-cea4f476-9774-43f2-8401-95f6b9141f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13273
73758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1327373758
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1475956675
Short name T434
Test name
Test status
Simulation time 8369866753 ps
CPU time 9.19 seconds
Started Mar 17 01:42:38 PM PDT 24
Finished Mar 17 01:42:47 PM PDT 24
Peak memory 203684 kb
Host smart-f1bc5dde-3ec8-4601-9c4b-5754ef6d0d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14759
56675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1475956675
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.629334213
Short name T323
Test name
Test status
Simulation time 69968552 ps
CPU time 1.86 seconds
Started Mar 17 01:42:52 PM PDT 24
Finished Mar 17 01:42:54 PM PDT 24
Peak memory 203652 kb
Host smart-e505fa24-f7cd-42ff-8547-54738c360ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62933
4213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.629334213
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.626944204
Short name T23
Test name
Test status
Simulation time 8364631672 ps
CPU time 8.32 seconds
Started Mar 17 01:42:39 PM PDT 24
Finished Mar 17 01:42:48 PM PDT 24
Peak memory 203488 kb
Host smart-44615fad-5b5e-4fe8-a75b-b1d5471fa77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62694
4204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.626944204
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.1586009939
Short name T569
Test name
Test status
Simulation time 8459653974 ps
CPU time 8.26 seconds
Started Mar 17 01:42:38 PM PDT 24
Finished Mar 17 01:42:46 PM PDT 24
Peak memory 203728 kb
Host smart-24900521-4028-4eed-af3d-b59ed4bb0076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15860
09939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.1586009939
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1284324989
Short name T677
Test name
Test status
Simulation time 8406703488 ps
CPU time 7.29 seconds
Started Mar 17 01:42:39 PM PDT 24
Finished Mar 17 01:42:47 PM PDT 24
Peak memory 203652 kb
Host smart-d7778387-b29c-4562-9f97-4808bd0c5e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12843
24989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1284324989
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.4252758604
Short name T636
Test name
Test status
Simulation time 8362059100 ps
CPU time 8.54 seconds
Started Mar 17 01:42:35 PM PDT 24
Finished Mar 17 01:42:44 PM PDT 24
Peak memory 203712 kb
Host smart-2ebad53d-d250-4c50-aab8-a3ffc70aac5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42527
58604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.4252758604
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3108428777
Short name T92
Test name
Test status
Simulation time 8430777834 ps
CPU time 7.95 seconds
Started Mar 17 01:42:52 PM PDT 24
Finished Mar 17 01:43:00 PM PDT 24
Peak memory 203648 kb
Host smart-d5ca852c-5a6d-44b3-be52-96b2beb75e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31084
28777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3108428777
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1499603130
Short name T612
Test name
Test status
Simulation time 8390479184 ps
CPU time 9.83 seconds
Started Mar 17 01:42:41 PM PDT 24
Finished Mar 17 01:42:51 PM PDT 24
Peak memory 203564 kb
Host smart-23fffb0f-2841-494c-a251-691ed79ab600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14996
03130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1499603130
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1718122606
Short name T346
Test name
Test status
Simulation time 8374191795 ps
CPU time 7.94 seconds
Started Mar 17 01:42:41 PM PDT 24
Finished Mar 17 01:42:49 PM PDT 24
Peak memory 203684 kb
Host smart-e7fb264b-9a76-45e7-a7e4-d9b357fbc3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17181
22606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1718122606
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.630690160
Short name T531
Test name
Test status
Simulation time 26505274 ps
CPU time 0.6 seconds
Started Mar 17 01:42:42 PM PDT 24
Finished Mar 17 01:42:43 PM PDT 24
Peak memory 203164 kb
Host smart-d64c1c16-5029-4979-bc4e-2c3c8b5df738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63069
0160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.630690160
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.4260159115
Short name T329
Test name
Test status
Simulation time 8389660910 ps
CPU time 8.46 seconds
Started Mar 17 01:42:37 PM PDT 24
Finished Mar 17 01:42:46 PM PDT 24
Peak memory 203820 kb
Host smart-bde20880-7e50-4bd9-b635-9acfeedbdaac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42601
59115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.4260159115
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2884467362
Short name T368
Test name
Test status
Simulation time 8355702024 ps
CPU time 9.39 seconds
Started Mar 17 01:42:41 PM PDT 24
Finished Mar 17 01:42:51 PM PDT 24
Peak memory 203648 kb
Host smart-fc2bb93f-be69-4da0-87e7-3fd43cef44bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28844
67362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2884467362
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.399964499
Short name T147
Test name
Test status
Simulation time 8479338822 ps
CPU time 8.51 seconds
Started Mar 17 01:42:41 PM PDT 24
Finished Mar 17 01:42:50 PM PDT 24
Peak memory 203652 kb
Host smart-22c77bae-bcbe-4907-9c4e-43c0f3498845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39996
4499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.399964499
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.60660133
Short name T302
Test name
Test status
Simulation time 8371639519 ps
CPU time 7.6 seconds
Started Mar 17 01:42:39 PM PDT 24
Finished Mar 17 01:42:46 PM PDT 24
Peak memory 203736 kb
Host smart-c32812fc-f711-40dc-a470-1cbf542ae075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60660
133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.60660133
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1018493818
Short name T682
Test name
Test status
Simulation time 172149541 ps
CPU time 1.63 seconds
Started Mar 17 01:42:38 PM PDT 24
Finished Mar 17 01:42:40 PM PDT 24
Peak memory 203656 kb
Host smart-a79ad669-d58a-40c6-9845-305662e085c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10184
93818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1018493818
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.876557158
Short name T164
Test name
Test status
Simulation time 8358236000 ps
CPU time 7.26 seconds
Started Mar 17 01:42:39 PM PDT 24
Finished Mar 17 01:42:46 PM PDT 24
Peak memory 203496 kb
Host smart-4855a115-a211-40a5-ac40-bffca20c1c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87655
7158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.876557158
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.597927431
Short name T626
Test name
Test status
Simulation time 8442518838 ps
CPU time 7.66 seconds
Started Mar 17 01:42:39 PM PDT 24
Finished Mar 17 01:42:48 PM PDT 24
Peak memory 203648 kb
Host smart-8a23865f-5704-4746-b7a8-2b9cdcdf82fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59792
7431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.597927431
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3335042771
Short name T257
Test name
Test status
Simulation time 8407936552 ps
CPU time 9.81 seconds
Started Mar 17 01:42:40 PM PDT 24
Finished Mar 17 01:42:50 PM PDT 24
Peak memory 203676 kb
Host smart-86ed7445-2475-4aac-b115-fd26f44ef67e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33350
42771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3335042771
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1774875193
Short name T305
Test name
Test status
Simulation time 8368905341 ps
CPU time 8.99 seconds
Started Mar 17 01:42:51 PM PDT 24
Finished Mar 17 01:43:00 PM PDT 24
Peak memory 203656 kb
Host smart-efabeccf-10f3-4509-915a-51ff4dc507df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17748
75193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1774875193
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3046210911
Short name T617
Test name
Test status
Simulation time 8382543548 ps
CPU time 9.28 seconds
Started Mar 17 01:42:38 PM PDT 24
Finished Mar 17 01:42:47 PM PDT 24
Peak memory 203528 kb
Host smart-b4cb14e3-039b-4b2c-8d54-17d51534f84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30462
10911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3046210911
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.916626513
Short name T322
Test name
Test status
Simulation time 8407643396 ps
CPU time 7.94 seconds
Started Mar 17 01:42:39 PM PDT 24
Finished Mar 17 01:42:48 PM PDT 24
Peak memory 203616 kb
Host smart-2f07ad50-53c7-49b5-ad47-cc522126ee59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91662
6513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.916626513
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3719234053
Short name T522
Test name
Test status
Simulation time 8364344829 ps
CPU time 8.68 seconds
Started Mar 17 01:42:38 PM PDT 24
Finished Mar 17 01:42:47 PM PDT 24
Peak memory 203640 kb
Host smart-425c5292-533b-4706-8e57-9efd56d141e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37192
34053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3719234053
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1896484972
Short name T495
Test name
Test status
Simulation time 25011296 ps
CPU time 0.66 seconds
Started Mar 17 01:42:39 PM PDT 24
Finished Mar 17 01:42:41 PM PDT 24
Peak memory 203208 kb
Host smart-39762a52-c100-4317-8ba0-1a121aa42253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18964
84972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1896484972
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.890959814
Short name T394
Test name
Test status
Simulation time 8445706620 ps
CPU time 7.17 seconds
Started Mar 17 01:42:39 PM PDT 24
Finished Mar 17 01:42:47 PM PDT 24
Peak memory 203668 kb
Host smart-eba899b2-ce0a-4d75-b237-37fe70face8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89095
9814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.890959814
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.1406549352
Short name T272
Test name
Test status
Simulation time 8400648758 ps
CPU time 10.12 seconds
Started Mar 17 01:42:39 PM PDT 24
Finished Mar 17 01:42:50 PM PDT 24
Peak memory 203728 kb
Host smart-cc518b69-7abe-431e-8dc3-a2cbe63437ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14065
49352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.1406549352
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.1476745827
Short name T362
Test name
Test status
Simulation time 8361579738 ps
CPU time 7.27 seconds
Started Mar 17 01:42:52 PM PDT 24
Finished Mar 17 01:42:59 PM PDT 24
Peak memory 203516 kb
Host smart-fedaff8d-e65e-43ac-b8b4-271fe50ded3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14767
45827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1476745827
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1831319639
Short name T586
Test name
Test status
Simulation time 8473113793 ps
CPU time 8.25 seconds
Started Mar 17 01:42:42 PM PDT 24
Finished Mar 17 01:42:51 PM PDT 24
Peak memory 203704 kb
Host smart-d0df502b-c17c-47ff-8910-c95f15a74663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18313
19639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1831319639
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.2408715222
Short name T695
Test name
Test status
Simulation time 8366890722 ps
CPU time 7.82 seconds
Started Mar 17 01:42:40 PM PDT 24
Finished Mar 17 01:42:48 PM PDT 24
Peak memory 203652 kb
Host smart-2a0a44ef-2c5e-47f1-b683-e0b1a30a9dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24087
15222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2408715222
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.728048517
Short name T445
Test name
Test status
Simulation time 61836036 ps
CPU time 1.84 seconds
Started Mar 17 01:42:39 PM PDT 24
Finished Mar 17 01:42:42 PM PDT 24
Peak memory 203496 kb
Host smart-0c9327a1-8908-44cc-ab0a-1433cfd129d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72804
8517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.728048517
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2532349912
Short name T169
Test name
Test status
Simulation time 8362373044 ps
CPU time 7.27 seconds
Started Mar 17 01:42:49 PM PDT 24
Finished Mar 17 01:42:56 PM PDT 24
Peak memory 203484 kb
Host smart-ac470112-c6e6-457d-a4f7-16ca0e56c3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25323
49912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2532349912
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1888923592
Short name T133
Test name
Test status
Simulation time 8376444588 ps
CPU time 7.89 seconds
Started Mar 17 01:42:38 PM PDT 24
Finished Mar 17 01:42:47 PM PDT 24
Peak memory 203712 kb
Host smart-79327848-2cd9-46d7-839c-9364837a24b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18889
23592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1888923592
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1959438007
Short name T310
Test name
Test status
Simulation time 8406161413 ps
CPU time 7.31 seconds
Started Mar 17 01:42:40 PM PDT 24
Finished Mar 17 01:42:48 PM PDT 24
Peak memory 203700 kb
Host smart-426da27c-aeb0-4a9b-a6e5-b3b015209d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19594
38007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1959438007
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1667937313
Short name T618
Test name
Test status
Simulation time 8367456125 ps
CPU time 8.68 seconds
Started Mar 17 01:42:49 PM PDT 24
Finished Mar 17 01:42:58 PM PDT 24
Peak memory 203704 kb
Host smart-6b0c396b-f9f9-49ba-b9bc-b6a7e20c546c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16679
37313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1667937313
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1202445059
Short name T566
Test name
Test status
Simulation time 8371614883 ps
CPU time 7.25 seconds
Started Mar 17 01:42:49 PM PDT 24
Finished Mar 17 01:42:57 PM PDT 24
Peak memory 203644 kb
Host smart-4ba1fbed-a948-419e-b00f-5a11bda55538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12024
45059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1202445059
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.4230283278
Short name T615
Test name
Test status
Simulation time 8382583445 ps
CPU time 7.49 seconds
Started Mar 17 01:42:45 PM PDT 24
Finished Mar 17 01:42:53 PM PDT 24
Peak memory 203512 kb
Host smart-9b830496-fc64-4b26-bb44-ee4e42fbd72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42302
83278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.4230283278
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2005245221
Short name T477
Test name
Test status
Simulation time 27249970 ps
CPU time 0.63 seconds
Started Mar 17 01:42:46 PM PDT 24
Finished Mar 17 01:42:46 PM PDT 24
Peak memory 203216 kb
Host smart-a6038de6-b636-4a8b-adb8-2a42c2af4ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20052
45221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2005245221
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.2086433190
Short name T513
Test name
Test status
Simulation time 8395224696 ps
CPU time 8.54 seconds
Started Mar 17 01:42:50 PM PDT 24
Finished Mar 17 01:42:59 PM PDT 24
Peak memory 203684 kb
Host smart-6fe099da-f65e-4bb9-8ae4-d46f0e52a346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20864
33190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2086433190
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.2963376228
Short name T656
Test name
Test status
Simulation time 8366158769 ps
CPU time 9.12 seconds
Started Mar 17 01:42:45 PM PDT 24
Finished Mar 17 01:42:54 PM PDT 24
Peak memory 203708 kb
Host smart-a93f07fa-8b6b-4892-a0f1-91c5ec7d9d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29633
76228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.2963376228
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2117685885
Short name T251
Test name
Test status
Simulation time 8360349782 ps
CPU time 7.12 seconds
Started Mar 17 01:42:46 PM PDT 24
Finished Mar 17 01:42:53 PM PDT 24
Peak memory 203504 kb
Host smart-786f4082-7588-4cd9-ab17-d1d335c760a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21176
85885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2117685885
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3404740565
Short name T698
Test name
Test status
Simulation time 8469420674 ps
CPU time 7.49 seconds
Started Mar 17 01:42:51 PM PDT 24
Finished Mar 17 01:42:59 PM PDT 24
Peak memory 203664 kb
Host smart-f35c49ac-a846-4166-8b82-9f0edc4f4683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34047
40565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3404740565
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.4277311971
Short name T39
Test name
Test status
Simulation time 8373124236 ps
CPU time 9.01 seconds
Started Mar 17 01:42:48 PM PDT 24
Finished Mar 17 01:42:57 PM PDT 24
Peak memory 203732 kb
Host smart-f6fb7f70-7eb6-4fd7-ba3f-0eebf2f334bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42773
11971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.4277311971
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.1239066494
Short name T297
Test name
Test status
Simulation time 254929831 ps
CPU time 1.92 seconds
Started Mar 17 01:42:49 PM PDT 24
Finished Mar 17 01:42:51 PM PDT 24
Peak memory 203516 kb
Host smart-9f040fb7-cac1-43a0-b678-44e4ff2263a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12390
66494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.1239066494
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.3485606692
Short name T732
Test name
Test status
Simulation time 8359019357 ps
CPU time 7.24 seconds
Started Mar 17 01:42:49 PM PDT 24
Finished Mar 17 01:42:57 PM PDT 24
Peak memory 203484 kb
Host smart-95e3a6fc-0ad7-4e4e-b297-d8d973755c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34856
06692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.3485606692
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1313003060
Short name T672
Test name
Test status
Simulation time 8406354093 ps
CPU time 8.8 seconds
Started Mar 17 01:42:47 PM PDT 24
Finished Mar 17 01:42:56 PM PDT 24
Peak memory 203676 kb
Host smart-fa0b05f8-0044-45a0-986a-e3197036a8d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13130
03060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1313003060
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3898431291
Short name T487
Test name
Test status
Simulation time 8361797144 ps
CPU time 7.61 seconds
Started Mar 17 01:42:48 PM PDT 24
Finished Mar 17 01:42:56 PM PDT 24
Peak memory 203732 kb
Host smart-cb24e6dc-f304-4678-acf6-5b406cfc00d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38984
31291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3898431291
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3342214683
Short name T97
Test name
Test status
Simulation time 8416722447 ps
CPU time 7.92 seconds
Started Mar 17 01:42:51 PM PDT 24
Finished Mar 17 01:42:59 PM PDT 24
Peak memory 203664 kb
Host smart-87ac2051-23d6-40c5-b161-eb254f42fbef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33422
14683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3342214683
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1037947768
Short name T454
Test name
Test status
Simulation time 8372592161 ps
CPU time 8.23 seconds
Started Mar 17 01:42:47 PM PDT 24
Finished Mar 17 01:42:55 PM PDT 24
Peak memory 203552 kb
Host smart-d543f202-a125-49b6-867f-676872508d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10379
47768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1037947768
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.506078663
Short name T711
Test name
Test status
Simulation time 8368942427 ps
CPU time 8.57 seconds
Started Mar 17 01:42:50 PM PDT 24
Finished Mar 17 01:42:58 PM PDT 24
Peak memory 203676 kb
Host smart-c39a853b-b8d1-4e55-a533-3039f341750e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50607
8663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.506078663
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3421678371
Short name T576
Test name
Test status
Simulation time 23829262 ps
CPU time 0.62 seconds
Started Mar 17 01:42:49 PM PDT 24
Finished Mar 17 01:42:50 PM PDT 24
Peak memory 203284 kb
Host smart-14acc253-d2e0-45cc-bcfe-8537772162d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34216
78371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3421678371
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2412518471
Short name T749
Test name
Test status
Simulation time 8455110828 ps
CPU time 8.28 seconds
Started Mar 17 01:42:48 PM PDT 24
Finished Mar 17 01:42:57 PM PDT 24
Peak memory 203744 kb
Host smart-4df7e58f-ae2a-49ba-984d-da2321e3a1a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24125
18471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2412518471
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.3786083518
Short name T620
Test name
Test status
Simulation time 8381119850 ps
CPU time 7.51 seconds
Started Mar 17 01:42:46 PM PDT 24
Finished Mar 17 01:42:53 PM PDT 24
Peak memory 203720 kb
Host smart-ff4d43b9-0519-4b9f-9e13-a98b6b11e9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37860
83518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.3786083518
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.4054437514
Short name T554
Test name
Test status
Simulation time 8354588316 ps
CPU time 7.73 seconds
Started Mar 17 01:42:49 PM PDT 24
Finished Mar 17 01:42:57 PM PDT 24
Peak memory 203624 kb
Host smart-20cfa3f1-9a4a-4e6f-ae11-47cb32ef1738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40544
37514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.4054437514
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1903482189
Short name T126
Test name
Test status
Simulation time 8472380453 ps
CPU time 7.25 seconds
Started Mar 17 01:42:47 PM PDT 24
Finished Mar 17 01:42:54 PM PDT 24
Peak memory 203704 kb
Host smart-7b23aa73-8247-45a0-b357-da718c7ba588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19034
82189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1903482189
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.24921824
Short name T550
Test name
Test status
Simulation time 8371919740 ps
CPU time 8 seconds
Started Mar 17 01:38:32 PM PDT 24
Finished Mar 17 01:38:40 PM PDT 24
Peak memory 203728 kb
Host smart-a66a1d78-d938-496a-88ad-12b6f8ae90b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24921
824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.24921824
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1423720272
Short name T227
Test name
Test status
Simulation time 227844051 ps
CPU time 2.1 seconds
Started Mar 17 01:38:30 PM PDT 24
Finished Mar 17 01:38:32 PM PDT 24
Peak memory 203688 kb
Host smart-dbaadb2d-79df-428a-8444-915255965e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14237
20272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1423720272
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3994225349
Short name T521
Test name
Test status
Simulation time 8365333127 ps
CPU time 9.17 seconds
Started Mar 17 01:38:31 PM PDT 24
Finished Mar 17 01:38:40 PM PDT 24
Peak memory 203512 kb
Host smart-1b6a78b0-39fb-455a-ae08-9bb210f45fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39942
25349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3994225349
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2147362317
Short name T212
Test name
Test status
Simulation time 8414655892 ps
CPU time 7.58 seconds
Started Mar 17 01:38:31 PM PDT 24
Finished Mar 17 01:38:39 PM PDT 24
Peak memory 203692 kb
Host smart-f9d6610e-92f3-4639-9389-a46d49deabc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21473
62317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2147362317
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.644543775
Short name T542
Test name
Test status
Simulation time 8405120479 ps
CPU time 7.69 seconds
Started Mar 17 01:38:32 PM PDT 24
Finished Mar 17 01:38:40 PM PDT 24
Peak memory 203700 kb
Host smart-02cedaab-3cda-4c47-ad71-70c0600b75c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64454
3775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.644543775
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1430096909
Short name T599
Test name
Test status
Simulation time 8361483143 ps
CPU time 7.58 seconds
Started Mar 17 01:38:31 PM PDT 24
Finished Mar 17 01:38:39 PM PDT 24
Peak memory 203716 kb
Host smart-0170f020-d8a9-44a0-acb3-df1607254ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14300
96909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1430096909
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.133333675
Short name T693
Test name
Test status
Simulation time 8416439428 ps
CPU time 7.59 seconds
Started Mar 17 01:38:31 PM PDT 24
Finished Mar 17 01:38:39 PM PDT 24
Peak memory 203672 kb
Host smart-d168d8e3-e2bf-45f7-981d-11f8083065c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13333
3675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.133333675
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.801030567
Short name T592
Test name
Test status
Simulation time 8403510529 ps
CPU time 7.35 seconds
Started Mar 17 01:38:33 PM PDT 24
Finished Mar 17 01:38:40 PM PDT 24
Peak memory 203544 kb
Host smart-93fab5f2-6f9c-4219-b483-c9463a4bd202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80103
0567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.801030567
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.127810611
Short name T709
Test name
Test status
Simulation time 8394204953 ps
CPU time 7.01 seconds
Started Mar 17 01:38:31 PM PDT 24
Finished Mar 17 01:38:38 PM PDT 24
Peak memory 203652 kb
Host smart-4aff2ebf-8e0c-4271-b9f0-3446382b2612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12781
0611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.127810611
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3342331660
Short name T400
Test name
Test status
Simulation time 25219401 ps
CPU time 0.61 seconds
Started Mar 17 01:38:32 PM PDT 24
Finished Mar 17 01:38:33 PM PDT 24
Peak memory 203276 kb
Host smart-e26dea8e-c113-4afd-9248-e06ac5ff5640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33423
31660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3342331660
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1030636344
Short name T9
Test name
Test status
Simulation time 8407165733 ps
CPU time 8.89 seconds
Started Mar 17 01:38:32 PM PDT 24
Finished Mar 17 01:38:41 PM PDT 24
Peak memory 203712 kb
Host smart-9e95e26a-36a1-488c-8336-4622e114145e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10306
36344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1030636344
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.2624692586
Short name T658
Test name
Test status
Simulation time 8370194713 ps
CPU time 7.32 seconds
Started Mar 17 01:38:32 PM PDT 24
Finished Mar 17 01:38:40 PM PDT 24
Peak memory 203748 kb
Host smart-18dec3c8-0037-43d1-8d13-ab3273062485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26246
92586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.2624692586
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.1391096792
Short name T68
Test name
Test status
Simulation time 102766330 ps
CPU time 0.9 seconds
Started Mar 17 01:38:39 PM PDT 24
Finished Mar 17 01:38:40 PM PDT 24
Peak memory 219384 kb
Host smart-06a9040a-1d2c-4da2-a20d-986e7c28ea78
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1391096792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1391096792
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.563979752
Short name T339
Test name
Test status
Simulation time 8354878210 ps
CPU time 7.51 seconds
Started Mar 17 01:38:32 PM PDT 24
Finished Mar 17 01:38:40 PM PDT 24
Peak memory 203588 kb
Host smart-a99fd671-185a-4aad-a07a-6e331871081b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56397
9752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.563979752
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1813809830
Short name T685
Test name
Test status
Simulation time 8478567127 ps
CPU time 7.41 seconds
Started Mar 17 01:38:31 PM PDT 24
Finished Mar 17 01:38:38 PM PDT 24
Peak memory 203744 kb
Host smart-3f5ffebd-939f-4afa-b2e5-0b234f16cf15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18138
09830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1813809830
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.865079821
Short name T598
Test name
Test status
Simulation time 8372548054 ps
CPU time 8.36 seconds
Started Mar 17 01:42:49 PM PDT 24
Finished Mar 17 01:42:57 PM PDT 24
Peak memory 203604 kb
Host smart-bb5e0142-20d5-43c4-a04a-8d001b34de3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86507
9821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.865079821
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1719080435
Short name T180
Test name
Test status
Simulation time 8357338988 ps
CPU time 7.08 seconds
Started Mar 17 01:42:51 PM PDT 24
Finished Mar 17 01:42:58 PM PDT 24
Peak memory 203496 kb
Host smart-bb7cc18e-9e9c-4c86-9be3-86dc932d8791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17190
80435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1719080435
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.3422035021
Short name T738
Test name
Test status
Simulation time 8405754431 ps
CPU time 7.51 seconds
Started Mar 17 01:42:48 PM PDT 24
Finished Mar 17 01:42:56 PM PDT 24
Peak memory 203720 kb
Host smart-cbd10abd-8922-42d8-b3c4-b2673ec6263f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34220
35021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3422035021
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.893712318
Short name T721
Test name
Test status
Simulation time 8404897748 ps
CPU time 8.27 seconds
Started Mar 17 01:42:50 PM PDT 24
Finished Mar 17 01:42:58 PM PDT 24
Peak memory 203704 kb
Host smart-724030d8-9ed6-4ac7-9df2-9b4d2562694c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89371
2318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.893712318
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2233551859
Short name T466
Test name
Test status
Simulation time 8363994915 ps
CPU time 8.2 seconds
Started Mar 17 01:42:49 PM PDT 24
Finished Mar 17 01:42:57 PM PDT 24
Peak memory 203692 kb
Host smart-8c09f5f1-1f49-4ac2-9461-e5ca6494ced3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22335
51859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2233551859
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1493122086
Short name T109
Test name
Test status
Simulation time 8445778667 ps
CPU time 9.43 seconds
Started Mar 17 01:42:49 PM PDT 24
Finished Mar 17 01:42:58 PM PDT 24
Peak memory 203652 kb
Host smart-b96a64a5-224b-4326-b9b9-f032c97fc70d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14931
22086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1493122086
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.973306870
Short name T281
Test name
Test status
Simulation time 8372865056 ps
CPU time 7.65 seconds
Started Mar 17 01:42:51 PM PDT 24
Finished Mar 17 01:42:59 PM PDT 24
Peak memory 203552 kb
Host smart-5ec6f85f-3595-4ee0-9fa7-b1a536c4773d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97330
6870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.973306870
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.685383510
Short name T526
Test name
Test status
Simulation time 8406362333 ps
CPU time 9.37 seconds
Started Mar 17 01:43:00 PM PDT 24
Finished Mar 17 01:43:10 PM PDT 24
Peak memory 203544 kb
Host smart-2afae741-c5c7-48d5-9d08-5e3b6873b865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68538
3510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.685383510
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3282882160
Short name T4
Test name
Test status
Simulation time 27073157 ps
CPU time 0.66 seconds
Started Mar 17 01:42:51 PM PDT 24
Finished Mar 17 01:42:52 PM PDT 24
Peak memory 203164 kb
Host smart-028125cd-66cc-4d2e-973f-df0e3c6747ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32828
82160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3282882160
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.4244403168
Short name T118
Test name
Test status
Simulation time 8405600766 ps
CPU time 7.88 seconds
Started Mar 17 01:42:52 PM PDT 24
Finished Mar 17 01:43:00 PM PDT 24
Peak memory 203624 kb
Host smart-07e8a4dc-66b3-4f4d-b05e-5b0c06a84f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42444
03168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.4244403168
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.2583539085
Short name T700
Test name
Test status
Simulation time 8393223221 ps
CPU time 7.39 seconds
Started Mar 17 01:42:54 PM PDT 24
Finished Mar 17 01:43:01 PM PDT 24
Peak memory 203736 kb
Host smart-716a037d-1988-407f-b20e-221c4f90de27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25835
39085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.2583539085
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3949198769
Short name T217
Test name
Test status
Simulation time 8357842162 ps
CPU time 7.73 seconds
Started Mar 17 01:42:52 PM PDT 24
Finished Mar 17 01:43:00 PM PDT 24
Peak memory 203692 kb
Host smart-fcd72a06-cc4d-4135-98e9-4a29f026c651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39491
98769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3949198769
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3596270367
Short name T148
Test name
Test status
Simulation time 8469963923 ps
CPU time 7.11 seconds
Started Mar 17 01:42:49 PM PDT 24
Finished Mar 17 01:42:56 PM PDT 24
Peak memory 203696 kb
Host smart-fc742a09-8ac1-4385-a6d4-15881c662c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35962
70367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3596270367
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.4076144013
Short name T337
Test name
Test status
Simulation time 8370112806 ps
CPU time 7.59 seconds
Started Mar 17 01:42:56 PM PDT 24
Finished Mar 17 01:43:03 PM PDT 24
Peak memory 203712 kb
Host smart-9e790407-9673-4384-bb3c-3016c85ca746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40761
44013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.4076144013
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1342632069
Short name T464
Test name
Test status
Simulation time 145798191 ps
CPU time 1.36 seconds
Started Mar 17 01:42:52 PM PDT 24
Finished Mar 17 01:42:54 PM PDT 24
Peak memory 203732 kb
Host smart-b8f45152-44d6-4a33-b583-079d96e50084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13426
32069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1342632069
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.313309992
Short name T446
Test name
Test status
Simulation time 8361508093 ps
CPU time 7.12 seconds
Started Mar 17 01:42:52 PM PDT 24
Finished Mar 17 01:42:59 PM PDT 24
Peak memory 203488 kb
Host smart-b50fed19-b7a1-4949-96d1-54a78693aeae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31330
9992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.313309992
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1392722488
Short name T408
Test name
Test status
Simulation time 8451346076 ps
CPU time 8.91 seconds
Started Mar 17 01:43:00 PM PDT 24
Finished Mar 17 01:43:09 PM PDT 24
Peak memory 203604 kb
Host smart-70743f78-bf99-494a-9981-81d739084d3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13927
22488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1392722488
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.779435769
Short name T724
Test name
Test status
Simulation time 8402807976 ps
CPU time 7.75 seconds
Started Mar 17 01:42:55 PM PDT 24
Finished Mar 17 01:43:03 PM PDT 24
Peak memory 203644 kb
Host smart-24873605-6372-4c80-ae75-0ca462115e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77943
5769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.779435769
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2260627282
Short name T411
Test name
Test status
Simulation time 8361316255 ps
CPU time 7.94 seconds
Started Mar 17 01:42:54 PM PDT 24
Finished Mar 17 01:43:03 PM PDT 24
Peak memory 203720 kb
Host smart-d3f9b083-6f22-4372-bb09-bcc7018e7db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22606
27282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2260627282
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.761093627
Short name T90
Test name
Test status
Simulation time 8429766485 ps
CPU time 7.88 seconds
Started Mar 17 01:42:56 PM PDT 24
Finished Mar 17 01:43:04 PM PDT 24
Peak memory 203692 kb
Host smart-8c0f6cf2-9f05-4673-9705-c3466cb40fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76109
3627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.761093627
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.867208464
Short name T666
Test name
Test status
Simulation time 8400362723 ps
CPU time 7.66 seconds
Started Mar 17 01:42:57 PM PDT 24
Finished Mar 17 01:43:05 PM PDT 24
Peak memory 203608 kb
Host smart-2431fbfb-2c5b-4977-b167-9260cd4ef528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86720
8464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.867208464
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3311877693
Short name T506
Test name
Test status
Simulation time 8407311910 ps
CPU time 7.27 seconds
Started Mar 17 01:43:00 PM PDT 24
Finished Mar 17 01:43:07 PM PDT 24
Peak memory 203436 kb
Host smart-06d70e36-c447-4e4c-952d-4124b36cb63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33118
77693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3311877693
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2908738755
Short name T684
Test name
Test status
Simulation time 26537638 ps
CPU time 0.61 seconds
Started Mar 17 01:42:58 PM PDT 24
Finished Mar 17 01:42:59 PM PDT 24
Peak memory 203220 kb
Host smart-51c9c746-f9d5-4281-a25a-5ba9ff8e10dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29087
38755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2908738755
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.736230274
Short name T655
Test name
Test status
Simulation time 8395131199 ps
CPU time 7.41 seconds
Started Mar 17 01:42:53 PM PDT 24
Finished Mar 17 01:43:01 PM PDT 24
Peak memory 203732 kb
Host smart-98740ffb-9f17-4d24-8680-175901010191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73623
0274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.736230274
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.2456505374
Short name T335
Test name
Test status
Simulation time 8386948381 ps
CPU time 7.61 seconds
Started Mar 17 01:42:52 PM PDT 24
Finished Mar 17 01:43:00 PM PDT 24
Peak memory 203676 kb
Host smart-8959c649-b52d-45db-8b68-19352ffe0870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24565
05374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.2456505374
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.788584697
Short name T591
Test name
Test status
Simulation time 8357529236 ps
CPU time 7.14 seconds
Started Mar 17 01:42:59 PM PDT 24
Finished Mar 17 01:43:06 PM PDT 24
Peak memory 203732 kb
Host smart-45ec5967-31f2-4328-8983-2006d41a1a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78858
4697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.788584697
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3708397830
Short name T37
Test name
Test status
Simulation time 8475526590 ps
CPU time 7.74 seconds
Started Mar 17 01:42:54 PM PDT 24
Finished Mar 17 01:43:02 PM PDT 24
Peak memory 203648 kb
Host smart-b6c843c9-ea01-4033-85d8-f7a9c599db14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37083
97830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3708397830
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.439395026
Short name T253
Test name
Test status
Simulation time 8373707518 ps
CPU time 7.74 seconds
Started Mar 17 01:42:51 PM PDT 24
Finished Mar 17 01:42:59 PM PDT 24
Peak memory 203644 kb
Host smart-3ffd3e31-20b2-4c41-b22e-af2e475bcbe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43939
5026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.439395026
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2883310323
Short name T220
Test name
Test status
Simulation time 160484063 ps
CPU time 1.53 seconds
Started Mar 17 01:42:51 PM PDT 24
Finished Mar 17 01:42:53 PM PDT 24
Peak memory 203812 kb
Host smart-ccb4329d-83e3-4b29-a44a-595eeefe59f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28833
10323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2883310323
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.823780551
Short name T181
Test name
Test status
Simulation time 8358215401 ps
CPU time 8.49 seconds
Started Mar 17 01:42:58 PM PDT 24
Finished Mar 17 01:43:07 PM PDT 24
Peak memory 203468 kb
Host smart-db51ae7a-39a5-47c1-bdbc-3e5f2a37cfd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82378
0551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.823780551
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.986114162
Short name T282
Test name
Test status
Simulation time 8402946117 ps
CPU time 7.29 seconds
Started Mar 17 01:42:58 PM PDT 24
Finished Mar 17 01:43:06 PM PDT 24
Peak memory 203680 kb
Host smart-f153ec0c-ff11-450a-bbf5-202a1faf81d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98611
4162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.986114162
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.983642412
Short name T504
Test name
Test status
Simulation time 8405104484 ps
CPU time 7.46 seconds
Started Mar 17 01:43:00 PM PDT 24
Finished Mar 17 01:43:08 PM PDT 24
Peak memory 203732 kb
Host smart-52922b46-2e48-4536-a1af-d8f25d23bd97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98364
2412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.983642412
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.488171840
Short name T396
Test name
Test status
Simulation time 8364180964 ps
CPU time 7.03 seconds
Started Mar 17 01:43:00 PM PDT 24
Finished Mar 17 01:43:07 PM PDT 24
Peak memory 203600 kb
Host smart-012fe2c7-f6ca-4dce-aaef-11f51f158878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48817
1840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.488171840
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.2627917934
Short name T436
Test name
Test status
Simulation time 8393792357 ps
CPU time 7.56 seconds
Started Mar 17 01:42:55 PM PDT 24
Finished Mar 17 01:43:02 PM PDT 24
Peak memory 203576 kb
Host smart-a8ac51d9-854e-41bb-b4a2-41b0bc5ca24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26279
17934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.2627917934
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3383132247
Short name T744
Test name
Test status
Simulation time 8408860954 ps
CPU time 9.65 seconds
Started Mar 17 01:42:53 PM PDT 24
Finished Mar 17 01:43:02 PM PDT 24
Peak memory 203660 kb
Host smart-0a954d93-d62f-4183-928f-8a34b0da4a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33831
32247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3383132247
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1217836809
Short name T583
Test name
Test status
Simulation time 24289789 ps
CPU time 0.69 seconds
Started Mar 17 01:42:52 PM PDT 24
Finished Mar 17 01:42:53 PM PDT 24
Peak memory 203320 kb
Host smart-03b485e8-cba1-436f-aff4-5e45270ef522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12178
36809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1217836809
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1562470810
Short name T730
Test name
Test status
Simulation time 8368837312 ps
CPU time 7.71 seconds
Started Mar 17 01:42:55 PM PDT 24
Finished Mar 17 01:43:03 PM PDT 24
Peak memory 203712 kb
Host smart-24c0ba16-83f3-4599-bc06-2cf87eb797c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15624
70810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1562470810
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.358507399
Short name T474
Test name
Test status
Simulation time 8386438584 ps
CPU time 7.44 seconds
Started Mar 17 01:42:56 PM PDT 24
Finished Mar 17 01:43:04 PM PDT 24
Peak memory 203760 kb
Host smart-945c48cb-3ccf-4bab-88a0-9916338b1160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35850
7399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.358507399
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.488944782
Short name T318
Test name
Test status
Simulation time 8362297241 ps
CPU time 7.81 seconds
Started Mar 17 01:42:52 PM PDT 24
Finished Mar 17 01:43:00 PM PDT 24
Peak memory 203536 kb
Host smart-771d6836-dec7-482d-be39-8a8d298fe327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48894
4782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.488944782
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1963101306
Short name T71
Test name
Test status
Simulation time 8479527730 ps
CPU time 8.21 seconds
Started Mar 17 01:42:59 PM PDT 24
Finished Mar 17 01:43:07 PM PDT 24
Peak memory 203744 kb
Host smart-32bf3e9f-a043-4c47-9a37-d4fd6de097d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19631
01306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1963101306
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.996022754
Short name T735
Test name
Test status
Simulation time 8363968789 ps
CPU time 7.78 seconds
Started Mar 17 01:42:54 PM PDT 24
Finished Mar 17 01:43:02 PM PDT 24
Peak memory 203684 kb
Host smart-bc1702bb-b3f3-444d-a754-37308599f365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99602
2754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.996022754
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3335720067
Short name T629
Test name
Test status
Simulation time 102181416 ps
CPU time 1.32 seconds
Started Mar 17 01:43:00 PM PDT 24
Finished Mar 17 01:43:02 PM PDT 24
Peak memory 203680 kb
Host smart-268b220d-45f2-4552-8ce7-ef6f36eb767d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33357
20067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3335720067
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.1650647499
Short name T608
Test name
Test status
Simulation time 8360185128 ps
CPU time 7.72 seconds
Started Mar 17 01:42:59 PM PDT 24
Finished Mar 17 01:43:07 PM PDT 24
Peak memory 203492 kb
Host smart-b848506a-fd77-4ed1-8b1a-5a5e4ef24477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16506
47499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.1650647499
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1773993331
Short name T120
Test name
Test status
Simulation time 8433305911 ps
CPU time 7.76 seconds
Started Mar 17 01:42:54 PM PDT 24
Finished Mar 17 01:43:02 PM PDT 24
Peak memory 203684 kb
Host smart-9c1b1e9b-89d2-4f17-8759-caf99b51908c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17739
93331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1773993331
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1680352140
Short name T433
Test name
Test status
Simulation time 8410654640 ps
CPU time 8.64 seconds
Started Mar 17 01:42:53 PM PDT 24
Finished Mar 17 01:43:02 PM PDT 24
Peak memory 203724 kb
Host smart-37377c68-0730-4dc9-beff-323b0675a7df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16803
52140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1680352140
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2609141690
Short name T209
Test name
Test status
Simulation time 8361659715 ps
CPU time 9.46 seconds
Started Mar 17 01:43:00 PM PDT 24
Finished Mar 17 01:43:10 PM PDT 24
Peak memory 203736 kb
Host smart-7d6ea83d-d2c8-48dc-b2d6-358c9a013a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26091
41690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2609141690
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3701971633
Short name T496
Test name
Test status
Simulation time 8419926365 ps
CPU time 7.46 seconds
Started Mar 17 01:42:58 PM PDT 24
Finished Mar 17 01:43:05 PM PDT 24
Peak memory 203756 kb
Host smart-6a992988-fc6a-49db-a5d8-1756f86ba34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37019
71633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3701971633
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2893124769
Short name T425
Test name
Test status
Simulation time 8373654208 ps
CPU time 8.39 seconds
Started Mar 17 01:43:00 PM PDT 24
Finished Mar 17 01:43:09 PM PDT 24
Peak memory 203456 kb
Host smart-06decc18-2acd-46c3-8608-ddfef967841b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28931
24769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2893124769
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.83719760
Short name T733
Test name
Test status
Simulation time 8367054270 ps
CPU time 7.41 seconds
Started Mar 17 01:43:01 PM PDT 24
Finished Mar 17 01:43:08 PM PDT 24
Peak memory 203692 kb
Host smart-f1003363-4ae3-4456-978f-54807cf04f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83719
760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.83719760
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.686589399
Short name T259
Test name
Test status
Simulation time 30826272 ps
CPU time 0.63 seconds
Started Mar 17 01:43:00 PM PDT 24
Finished Mar 17 01:43:01 PM PDT 24
Peak memory 203120 kb
Host smart-ce7d1639-f8d0-422b-bdeb-54d9424d7ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68658
9399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.686589399
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.1750668181
Short name T634
Test name
Test status
Simulation time 8385827092 ps
CPU time 7.69 seconds
Started Mar 17 01:43:00 PM PDT 24
Finished Mar 17 01:43:08 PM PDT 24
Peak memory 203752 kb
Host smart-69a7c3d0-c315-453c-a482-5c58edfb1228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17506
68181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.1750668181
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.26143779
Short name T377
Test name
Test status
Simulation time 8391644343 ps
CPU time 7.29 seconds
Started Mar 17 01:42:58 PM PDT 24
Finished Mar 17 01:43:06 PM PDT 24
Peak memory 203704 kb
Host smart-e0d7275f-0b8a-4ed2-ad4a-568b3d037dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26143
779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.26143779
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.142557307
Short name T622
Test name
Test status
Simulation time 8361080327 ps
CPU time 7.65 seconds
Started Mar 17 01:43:00 PM PDT 24
Finished Mar 17 01:43:08 PM PDT 24
Peak memory 203596 kb
Host smart-86333967-153f-4d8b-bfd3-c55533140d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14255
7307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.142557307
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3750585971
Short name T545
Test name
Test status
Simulation time 8372204042 ps
CPU time 8.9 seconds
Started Mar 17 01:43:00 PM PDT 24
Finished Mar 17 01:43:09 PM PDT 24
Peak memory 203688 kb
Host smart-5c381b12-433c-4d2e-8c0d-4d3433a5365f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37505
85971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3750585971
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.18043779
Short name T587
Test name
Test status
Simulation time 73644228 ps
CPU time 2.22 seconds
Started Mar 17 01:43:01 PM PDT 24
Finished Mar 17 01:43:04 PM PDT 24
Peak memory 203684 kb
Host smart-f300ddef-ca71-47e0-b46c-0888e2f8982b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18043
779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.18043779
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.1851880665
Short name T157
Test name
Test status
Simulation time 8358122506 ps
CPU time 7.67 seconds
Started Mar 17 01:42:58 PM PDT 24
Finished Mar 17 01:43:06 PM PDT 24
Peak memory 203488 kb
Host smart-61fe89e0-53db-430d-9d86-0e7443b05ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18518
80665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.1851880665
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3726681621
Short name T595
Test name
Test status
Simulation time 8376512043 ps
CPU time 7.18 seconds
Started Mar 17 01:43:00 PM PDT 24
Finished Mar 17 01:43:07 PM PDT 24
Peak memory 203708 kb
Host smart-36fbf3bf-763e-4431-9004-2754f23594f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37266
81621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3726681621
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.3038765321
Short name T699
Test name
Test status
Simulation time 8408579342 ps
CPU time 8.14 seconds
Started Mar 17 01:42:59 PM PDT 24
Finished Mar 17 01:43:07 PM PDT 24
Peak memory 203700 kb
Host smart-7867aa91-c294-4472-98ed-2fa8d8a9ff9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30387
65321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.3038765321
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.4287467320
Short name T324
Test name
Test status
Simulation time 8365809494 ps
CPU time 7.08 seconds
Started Mar 17 01:42:57 PM PDT 24
Finished Mar 17 01:43:04 PM PDT 24
Peak memory 203616 kb
Host smart-de635be8-aa60-4ae6-a6da-3ce1df7ee266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42874
67320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.4287467320
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.1799324063
Short name T8
Test name
Test status
Simulation time 8402787515 ps
CPU time 7.42 seconds
Started Mar 17 01:42:58 PM PDT 24
Finished Mar 17 01:43:06 PM PDT 24
Peak memory 203584 kb
Host smart-dfa6178e-35d8-400c-ae32-f40cd96aac80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17993
24063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.1799324063
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.818978352
Short name T274
Test name
Test status
Simulation time 8396100887 ps
CPU time 7.92 seconds
Started Mar 17 01:42:58 PM PDT 24
Finished Mar 17 01:43:06 PM PDT 24
Peak memory 203572 kb
Host smart-0a893bd7-75c3-4b24-ad84-f4b073ed722e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81897
8352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.818978352
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2564240601
Short name T416
Test name
Test status
Simulation time 24516902 ps
CPU time 0.63 seconds
Started Mar 17 01:43:00 PM PDT 24
Finished Mar 17 01:43:01 PM PDT 24
Peak memory 203216 kb
Host smart-21f88389-4507-4c2f-93d9-1968a8a6e7db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25642
40601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2564240601
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3454410493
Short name T424
Test name
Test status
Simulation time 8408520138 ps
CPU time 9.85 seconds
Started Mar 17 01:43:00 PM PDT 24
Finished Mar 17 01:43:10 PM PDT 24
Peak memory 203664 kb
Host smart-b24caaf8-b017-4da2-b43b-e0d6cf587ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34544
10493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3454410493
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.1806642509
Short name T507
Test name
Test status
Simulation time 8379839363 ps
CPU time 7.82 seconds
Started Mar 17 01:42:57 PM PDT 24
Finished Mar 17 01:43:05 PM PDT 24
Peak memory 203732 kb
Host smart-ebe33760-a66d-481e-b008-056194042074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18066
42509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.1806642509
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.4086891048
Short name T429
Test name
Test status
Simulation time 8355044345 ps
CPU time 9.73 seconds
Started Mar 17 01:42:58 PM PDT 24
Finished Mar 17 01:43:08 PM PDT 24
Peak memory 203700 kb
Host smart-1c29429d-9b73-4437-8b9c-a66139a85e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40868
91048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.4086891048
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.3362224979
Short name T143
Test name
Test status
Simulation time 8475139992 ps
CPU time 7.43 seconds
Started Mar 17 01:43:01 PM PDT 24
Finished Mar 17 01:43:08 PM PDT 24
Peak memory 203668 kb
Host smart-82648ef1-c444-494a-9765-c5f95b3e9557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33622
24979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.3362224979
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3924445525
Short name T225
Test name
Test status
Simulation time 8373574686 ps
CPU time 9.41 seconds
Started Mar 17 01:42:58 PM PDT 24
Finished Mar 17 01:43:07 PM PDT 24
Peak memory 203720 kb
Host smart-a73ef104-17e2-4d08-812e-3c93a59c4380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39244
45525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3924445525
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1411556110
Short name T686
Test name
Test status
Simulation time 56813523 ps
CPU time 1.6 seconds
Started Mar 17 01:43:04 PM PDT 24
Finished Mar 17 01:43:06 PM PDT 24
Peak memory 203716 kb
Host smart-eda799c7-70b0-4341-bcb3-eb593f8df2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14115
56110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1411556110
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1356063458
Short name T151
Test name
Test status
Simulation time 8364182216 ps
CPU time 7.34 seconds
Started Mar 17 01:43:05 PM PDT 24
Finished Mar 17 01:43:13 PM PDT 24
Peak memory 203388 kb
Host smart-62328744-bbf8-4e67-94ca-2dab0cea101a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13560
63458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1356063458
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.1589586791
Short name T648
Test name
Test status
Simulation time 8376070685 ps
CPU time 7.67 seconds
Started Mar 17 01:43:02 PM PDT 24
Finished Mar 17 01:43:10 PM PDT 24
Peak memory 203732 kb
Host smart-f8c8bfcd-c4c5-4ebb-b48f-298d4faae01f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15895
86791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.1589586791
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.3567371557
Short name T291
Test name
Test status
Simulation time 8407071716 ps
CPU time 9.25 seconds
Started Mar 17 01:43:04 PM PDT 24
Finished Mar 17 01:43:13 PM PDT 24
Peak memory 203696 kb
Host smart-acb22f36-0220-4cd9-ad1a-1f60570871f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35673
71557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.3567371557
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.700224359
Short name T641
Test name
Test status
Simulation time 8366993642 ps
CPU time 7.43 seconds
Started Mar 17 01:43:04 PM PDT 24
Finished Mar 17 01:43:11 PM PDT 24
Peak memory 203620 kb
Host smart-56ac1a9d-438c-404e-8737-74dfd127c73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70022
4359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.700224359
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.557808636
Short name T560
Test name
Test status
Simulation time 8415129275 ps
CPU time 7.28 seconds
Started Mar 17 01:43:08 PM PDT 24
Finished Mar 17 01:43:15 PM PDT 24
Peak memory 203644 kb
Host smart-f3ea7972-1b16-4905-9496-1eec41f8a2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55780
8636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.557808636
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.426774794
Short name T289
Test name
Test status
Simulation time 8384811755 ps
CPU time 9.58 seconds
Started Mar 17 01:43:05 PM PDT 24
Finished Mar 17 01:43:14 PM PDT 24
Peak memory 203528 kb
Host smart-5dd1671d-ed3d-416a-86ef-5cab2bb50a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42677
4794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.426774794
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1001323716
Short name T668
Test name
Test status
Simulation time 8398281303 ps
CPU time 8.16 seconds
Started Mar 17 01:43:05 PM PDT 24
Finished Mar 17 01:43:13 PM PDT 24
Peak memory 203568 kb
Host smart-eb5b582c-5658-4242-8163-02d54fdfa6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10013
23716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1001323716
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1760491261
Short name T720
Test name
Test status
Simulation time 25663351 ps
CPU time 0.64 seconds
Started Mar 17 01:43:05 PM PDT 24
Finished Mar 17 01:43:06 PM PDT 24
Peak memory 203124 kb
Host smart-eadbfe4c-3289-42ac-81fd-9cce3c9ed728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17604
91261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1760491261
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3016186219
Short name T696
Test name
Test status
Simulation time 8403891951 ps
CPU time 7.23 seconds
Started Mar 17 01:43:05 PM PDT 24
Finished Mar 17 01:43:13 PM PDT 24
Peak memory 203712 kb
Host smart-916d14e7-182e-4a20-bca1-1e15b36375ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30161
86219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3016186219
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.3554586152
Short name T352
Test name
Test status
Simulation time 8393893492 ps
CPU time 9.57 seconds
Started Mar 17 01:43:04 PM PDT 24
Finished Mar 17 01:43:14 PM PDT 24
Peak memory 203664 kb
Host smart-beba56b3-5b71-42ae-90e2-ff69a839fe5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35545
86152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.3554586152
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3673262994
Short name T410
Test name
Test status
Simulation time 8356625251 ps
CPU time 7.45 seconds
Started Mar 17 01:43:03 PM PDT 24
Finished Mar 17 01:43:11 PM PDT 24
Peak memory 203536 kb
Host smart-521dfdf6-6c6c-41b9-be13-ef2aa9fde38e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36732
62994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3673262994
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1066264221
Short name T659
Test name
Test status
Simulation time 8471395312 ps
CPU time 8.26 seconds
Started Mar 17 01:42:57 PM PDT 24
Finished Mar 17 01:43:06 PM PDT 24
Peak memory 203680 kb
Host smart-f630f7df-b9b4-4317-a2e1-bd5eca803160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10662
64221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1066264221
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3015209047
Short name T533
Test name
Test status
Simulation time 8366389091 ps
CPU time 7.58 seconds
Started Mar 17 01:43:05 PM PDT 24
Finished Mar 17 01:43:13 PM PDT 24
Peak memory 203644 kb
Host smart-9ca21550-7055-4b1f-91ec-cf171dff69b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30152
09047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3015209047
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.474600327
Short name T69
Test name
Test status
Simulation time 180936632 ps
CPU time 2.09 seconds
Started Mar 17 01:43:05 PM PDT 24
Finished Mar 17 01:43:08 PM PDT 24
Peak memory 203680 kb
Host smart-0433a0f1-70bd-4447-b6be-22efef06c372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47460
0327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.474600327
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3359458948
Short name T745
Test name
Test status
Simulation time 8355839191 ps
CPU time 7.56 seconds
Started Mar 17 01:43:09 PM PDT 24
Finished Mar 17 01:43:16 PM PDT 24
Peak memory 203524 kb
Host smart-20cf1d93-bf41-4185-b3e6-caad6f81aa16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33594
58948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3359458948
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1912164169
Short name T741
Test name
Test status
Simulation time 8398669068 ps
CPU time 7.4 seconds
Started Mar 17 01:43:06 PM PDT 24
Finished Mar 17 01:43:13 PM PDT 24
Peak memory 203752 kb
Host smart-e7835256-6f37-4d08-b41a-a3fc8f2e6f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19121
64169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1912164169
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2791881697
Short name T280
Test name
Test status
Simulation time 8405864829 ps
CPU time 7.61 seconds
Started Mar 17 01:43:01 PM PDT 24
Finished Mar 17 01:43:09 PM PDT 24
Peak memory 203712 kb
Host smart-967d851c-6a1e-4598-8bd8-3a23f7e3b421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27918
81697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2791881697
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2074210797
Short name T338
Test name
Test status
Simulation time 8365115080 ps
CPU time 9.06 seconds
Started Mar 17 01:43:05 PM PDT 24
Finished Mar 17 01:43:14 PM PDT 24
Peak memory 203648 kb
Host smart-19cbe145-cc88-446d-a106-0d1635abf097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20742
10797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2074210797
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3158886734
Short name T87
Test name
Test status
Simulation time 8398003373 ps
CPU time 7.46 seconds
Started Mar 17 01:43:06 PM PDT 24
Finished Mar 17 01:43:13 PM PDT 24
Peak memory 203620 kb
Host smart-e034937b-69e9-4398-b870-e0a9327f2efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31588
86734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3158886734
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2418009393
Short name T568
Test name
Test status
Simulation time 8366572127 ps
CPU time 8.94 seconds
Started Mar 17 01:43:06 PM PDT 24
Finished Mar 17 01:43:15 PM PDT 24
Peak memory 203596 kb
Host smart-d3df6acb-1111-43d5-9b6c-0c3c2aa5b8f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24180
09393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2418009393
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.361740639
Short name T399
Test name
Test status
Simulation time 8405663522 ps
CPU time 7.85 seconds
Started Mar 17 01:43:04 PM PDT 24
Finished Mar 17 01:43:12 PM PDT 24
Peak memory 203496 kb
Host smart-ada30342-2b3d-49d2-8c08-d991b11f43ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36174
0639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.361740639
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.49513233
Short name T606
Test name
Test status
Simulation time 26247188 ps
CPU time 0.63 seconds
Started Mar 17 01:43:10 PM PDT 24
Finished Mar 17 01:43:11 PM PDT 24
Peak memory 203176 kb
Host smart-cb017b7f-0f25-4f98-8424-8f272a8eb52a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49513
233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.49513233
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.1331497074
Short name T613
Test name
Test status
Simulation time 8376069718 ps
CPU time 8.88 seconds
Started Mar 17 01:43:04 PM PDT 24
Finished Mar 17 01:43:13 PM PDT 24
Peak memory 203712 kb
Host smart-175eca4c-6337-46ac-a9f0-7f3f19a023c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13314
97074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.1331497074
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.243685506
Short name T552
Test name
Test status
Simulation time 8402512129 ps
CPU time 7.41 seconds
Started Mar 17 01:43:03 PM PDT 24
Finished Mar 17 01:43:11 PM PDT 24
Peak memory 203652 kb
Host smart-ae2afa7b-b8c6-4d47-b89f-773f018beff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24368
5506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.243685506
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1611143805
Short name T593
Test name
Test status
Simulation time 8364512622 ps
CPU time 7.48 seconds
Started Mar 17 01:43:03 PM PDT 24
Finished Mar 17 01:43:10 PM PDT 24
Peak memory 203512 kb
Host smart-d76e9714-5da0-41a0-a3b9-b2de24f05cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16111
43805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1611143805
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3065140192
Short name T117
Test name
Test status
Simulation time 8481148405 ps
CPU time 8.95 seconds
Started Mar 17 01:43:05 PM PDT 24
Finished Mar 17 01:43:14 PM PDT 24
Peak memory 203656 kb
Host smart-94e69d03-a153-4aaa-a4de-764d82ce9cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30651
40192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3065140192
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2184717616
Short name T423
Test name
Test status
Simulation time 8374146002 ps
CPU time 8.03 seconds
Started Mar 17 01:43:08 PM PDT 24
Finished Mar 17 01:43:17 PM PDT 24
Peak memory 203644 kb
Host smart-e3398c23-c040-4cc3-8ba2-437c6584e22a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21847
17616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2184717616
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.512565508
Short name T298
Test name
Test status
Simulation time 78933278 ps
CPU time 2.07 seconds
Started Mar 17 01:43:10 PM PDT 24
Finished Mar 17 01:43:13 PM PDT 24
Peak memory 203768 kb
Host smart-66e758a6-8264-4dfe-89ab-44e3bbbac146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51256
5508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.512565508
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2808267787
Short name T76
Test name
Test status
Simulation time 8357215754 ps
CPU time 7.05 seconds
Started Mar 17 01:43:10 PM PDT 24
Finished Mar 17 01:43:17 PM PDT 24
Peak memory 203500 kb
Host smart-b12d45ca-0b18-4c81-98de-73c14074d89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28082
67787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2808267787
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3982986712
Short name T415
Test name
Test status
Simulation time 8456619440 ps
CPU time 8.59 seconds
Started Mar 17 01:43:09 PM PDT 24
Finished Mar 17 01:43:18 PM PDT 24
Peak memory 203712 kb
Host smart-149d6b55-391d-42d7-8e5b-cd1a7c1b4f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39829
86712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3982986712
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2860486355
Short name T729
Test name
Test status
Simulation time 8409212274 ps
CPU time 8.83 seconds
Started Mar 17 01:43:11 PM PDT 24
Finished Mar 17 01:43:20 PM PDT 24
Peak memory 203648 kb
Host smart-b3cd0b47-e6e4-4e0d-b534-f8ed8fa8e3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28604
86355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2860486355
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2714076106
Short name T559
Test name
Test status
Simulation time 8366470907 ps
CPU time 8.67 seconds
Started Mar 17 01:43:09 PM PDT 24
Finished Mar 17 01:43:17 PM PDT 24
Peak memory 203736 kb
Host smart-9e5169c4-bd52-4961-bccc-5a07ecd12103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27140
76106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2714076106
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.1461300168
Short name T688
Test name
Test status
Simulation time 8427559488 ps
CPU time 8.61 seconds
Started Mar 17 01:43:11 PM PDT 24
Finished Mar 17 01:43:19 PM PDT 24
Peak memory 203676 kb
Host smart-d2abdb67-8a19-4a20-81b7-024f8e8daf3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14613
00168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1461300168
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1899467579
Short name T650
Test name
Test status
Simulation time 8380676223 ps
CPU time 7.19 seconds
Started Mar 17 01:43:08 PM PDT 24
Finished Mar 17 01:43:16 PM PDT 24
Peak memory 203556 kb
Host smart-5b3aca94-0065-4eb5-93c1-4bcfb948b53c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18994
67579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1899467579
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1979411076
Short name T447
Test name
Test status
Simulation time 8400592623 ps
CPU time 8.16 seconds
Started Mar 17 01:43:07 PM PDT 24
Finished Mar 17 01:43:15 PM PDT 24
Peak memory 203516 kb
Host smart-9e21a7ec-65a5-4699-b1fe-17e5398e5f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19794
11076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1979411076
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2332190270
Short name T585
Test name
Test status
Simulation time 30374418 ps
CPU time 0.64 seconds
Started Mar 17 01:43:08 PM PDT 24
Finished Mar 17 01:43:09 PM PDT 24
Peak memory 203172 kb
Host smart-3be3a4c1-c7fb-46df-b609-7edf4bc78cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23321
90270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2332190270
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2216505766
Short name T654
Test name
Test status
Simulation time 8455407412 ps
CPU time 8.67 seconds
Started Mar 17 01:43:09 PM PDT 24
Finished Mar 17 01:43:18 PM PDT 24
Peak memory 203716 kb
Host smart-3c45a312-4d83-4da9-80f0-ff8a58c43aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22165
05766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2216505766
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.3779419014
Short name T643
Test name
Test status
Simulation time 8362163693 ps
CPU time 9.02 seconds
Started Mar 17 01:43:06 PM PDT 24
Finished Mar 17 01:43:15 PM PDT 24
Peak memory 203640 kb
Host smart-245e65df-0d4f-48fb-9ad4-a37cf4c2e742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37794
19014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.3779419014
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2780216560
Short name T426
Test name
Test status
Simulation time 8361532274 ps
CPU time 8.18 seconds
Started Mar 17 01:43:08 PM PDT 24
Finished Mar 17 01:43:17 PM PDT 24
Peak memory 203528 kb
Host smart-cdfe8360-f1c4-4de0-b3d7-0f319bb776e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27802
16560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2780216560
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.2938288237
Short name T381
Test name
Test status
Simulation time 8477405123 ps
CPU time 7.72 seconds
Started Mar 17 01:43:17 PM PDT 24
Finished Mar 17 01:43:24 PM PDT 24
Peak memory 203616 kb
Host smart-321170c8-888c-47ba-aef8-f424b126f9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29382
88237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2938288237
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.2075419939
Short name T456
Test name
Test status
Simulation time 8365826286 ps
CPU time 9.04 seconds
Started Mar 17 01:43:12 PM PDT 24
Finished Mar 17 01:43:21 PM PDT 24
Peak memory 203676 kb
Host smart-a9032b90-f220-44c0-bc0a-375ef0fb8cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20754
19939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2075419939
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1741694634
Short name T386
Test name
Test status
Simulation time 296753111 ps
CPU time 2.34 seconds
Started Mar 17 01:43:09 PM PDT 24
Finished Mar 17 01:43:11 PM PDT 24
Peak memory 203476 kb
Host smart-d2c606ac-b3a2-411e-a714-5004c54de2f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17416
94634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1741694634
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1195809219
Short name T152
Test name
Test status
Simulation time 8362484102 ps
CPU time 7.2 seconds
Started Mar 17 01:43:08 PM PDT 24
Finished Mar 17 01:43:16 PM PDT 24
Peak memory 203636 kb
Host smart-80b14808-7aec-40ab-8769-781d631e0a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11958
09219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1195809219
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1914920065
Short name T210
Test name
Test status
Simulation time 8432126991 ps
CPU time 7.79 seconds
Started Mar 17 01:43:06 PM PDT 24
Finished Mar 17 01:43:14 PM PDT 24
Peak memory 203680 kb
Host smart-477d0620-6797-4fcc-a999-929bc06be62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19149
20065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1914920065
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2284603908
Short name T607
Test name
Test status
Simulation time 8403302766 ps
CPU time 9.15 seconds
Started Mar 17 01:43:11 PM PDT 24
Finished Mar 17 01:43:20 PM PDT 24
Peak memory 203720 kb
Host smart-3cd772bc-6a65-480b-bfe9-2293a56a2f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22846
03908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2284603908
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.4205575901
Short name T247
Test name
Test status
Simulation time 8362621182 ps
CPU time 7.43 seconds
Started Mar 17 01:43:17 PM PDT 24
Finished Mar 17 01:43:24 PM PDT 24
Peak memory 203604 kb
Host smart-2a0cd7d6-45c3-4692-944d-75ae97a365a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42055
75901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.4205575901
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2684049253
Short name T105
Test name
Test status
Simulation time 8414607710 ps
CPU time 7.46 seconds
Started Mar 17 01:43:10 PM PDT 24
Finished Mar 17 01:43:17 PM PDT 24
Peak memory 203724 kb
Host smart-70df4b86-6067-4bfb-aeae-70f5e687c797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26840
49253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2684049253
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.1537596341
Short name T17
Test name
Test status
Simulation time 8396818105 ps
CPU time 8.4 seconds
Started Mar 17 01:43:08 PM PDT 24
Finished Mar 17 01:43:17 PM PDT 24
Peak memory 203564 kb
Host smart-3375162b-7b0a-4c29-b19c-e723d1aa6bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15375
96341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1537596341
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.3463245285
Short name T296
Test name
Test status
Simulation time 8377855110 ps
CPU time 7.84 seconds
Started Mar 17 01:43:09 PM PDT 24
Finished Mar 17 01:43:17 PM PDT 24
Peak memory 203492 kb
Host smart-3859aee7-fe10-4d3a-8a13-fd421dd8cd1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34632
45285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.3463245285
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2391102333
Short name T619
Test name
Test status
Simulation time 29044853 ps
CPU time 0.65 seconds
Started Mar 17 01:43:11 PM PDT 24
Finished Mar 17 01:43:11 PM PDT 24
Peak memory 203192 kb
Host smart-cf75e720-0d35-44d9-8341-33641abb60c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23911
02333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2391102333
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2201229521
Short name T294
Test name
Test status
Simulation time 8409879925 ps
CPU time 7.48 seconds
Started Mar 17 01:43:09 PM PDT 24
Finished Mar 17 01:43:16 PM PDT 24
Peak memory 203668 kb
Host smart-0a2d068f-4a8f-47ea-8a92-3996b6936490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22012
29521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2201229521
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.3020338000
Short name T731
Test name
Test status
Simulation time 8389900799 ps
CPU time 8.08 seconds
Started Mar 17 01:43:10 PM PDT 24
Finished Mar 17 01:43:18 PM PDT 24
Peak memory 203692 kb
Host smart-51b102ca-1ff0-4aaf-9be2-e5717cfdf228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30203
38000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.3020338000
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.897523697
Short name T276
Test name
Test status
Simulation time 8360785000 ps
CPU time 8.76 seconds
Started Mar 17 01:43:08 PM PDT 24
Finished Mar 17 01:43:17 PM PDT 24
Peak memory 203532 kb
Host smart-ac49a1a2-b15b-4737-aac0-bc559073f091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89752
3697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.897523697
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2301711035
Short name T750
Test name
Test status
Simulation time 8470729017 ps
CPU time 7.64 seconds
Started Mar 17 01:43:11 PM PDT 24
Finished Mar 17 01:43:18 PM PDT 24
Peak memory 203692 kb
Host smart-b1f8c5a5-a655-459f-a2c1-8550b65c277c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23017
11035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2301711035
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.972033537
Short name T75
Test name
Test status
Simulation time 8371518478 ps
CPU time 10.01 seconds
Started Mar 17 01:43:17 PM PDT 24
Finished Mar 17 01:43:27 PM PDT 24
Peak memory 203704 kb
Host smart-7b7bf4e0-b428-4ac4-9d38-248a2215e38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97203
3537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.972033537
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3451426936
Short name T233
Test name
Test status
Simulation time 74534126 ps
CPU time 2.14 seconds
Started Mar 17 01:43:15 PM PDT 24
Finished Mar 17 01:43:17 PM PDT 24
Peak memory 203740 kb
Host smart-65b51aff-8329-41d4-9f58-c798b1c1c29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34514
26936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3451426936
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.1797599930
Short name T414
Test name
Test status
Simulation time 8361150823 ps
CPU time 9.35 seconds
Started Mar 17 01:43:17 PM PDT 24
Finished Mar 17 01:43:27 PM PDT 24
Peak memory 203388 kb
Host smart-46e761db-8d3e-4177-be5a-a5db19dca31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17975
99930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1797599930
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.4130138359
Short name T428
Test name
Test status
Simulation time 8436225719 ps
CPU time 7.32 seconds
Started Mar 17 01:43:20 PM PDT 24
Finished Mar 17 01:43:28 PM PDT 24
Peak memory 203676 kb
Host smart-bdce8a75-9832-429f-8ced-a0d4b33094eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41301
38359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.4130138359
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3626788027
Short name T565
Test name
Test status
Simulation time 8403165336 ps
CPU time 8.23 seconds
Started Mar 17 01:43:15 PM PDT 24
Finished Mar 17 01:43:23 PM PDT 24
Peak memory 203692 kb
Host smart-6e48770a-4475-4b03-857f-ea582ee81625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36267
88027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3626788027
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.4002637747
Short name T573
Test name
Test status
Simulation time 8363208329 ps
CPU time 7.94 seconds
Started Mar 17 01:43:15 PM PDT 24
Finished Mar 17 01:43:23 PM PDT 24
Peak memory 203692 kb
Host smart-1f5415ef-843e-4741-8d9e-babe7b18b906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40026
37747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.4002637747
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2842028373
Short name T102
Test name
Test status
Simulation time 8407038130 ps
CPU time 7.84 seconds
Started Mar 17 01:43:18 PM PDT 24
Finished Mar 17 01:43:26 PM PDT 24
Peak memory 203696 kb
Host smart-6ddbf708-4687-4651-88ad-0c67d4bfd8b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28420
28373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2842028373
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3986028134
Short name T293
Test name
Test status
Simulation time 8393619221 ps
CPU time 7.35 seconds
Started Mar 17 01:43:17 PM PDT 24
Finished Mar 17 01:43:25 PM PDT 24
Peak memory 203568 kb
Host smart-d67cf4bc-4706-46eb-b4b4-ef2c691d1b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39860
28134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3986028134
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2375671348
Short name T505
Test name
Test status
Simulation time 8385781939 ps
CPU time 8.69 seconds
Started Mar 17 01:43:14 PM PDT 24
Finished Mar 17 01:43:23 PM PDT 24
Peak memory 203516 kb
Host smart-3881dab7-ccba-4884-bcef-82112866f26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23756
71348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2375671348
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.268037696
Short name T459
Test name
Test status
Simulation time 28918537 ps
CPU time 0.65 seconds
Started Mar 17 01:43:16 PM PDT 24
Finished Mar 17 01:43:17 PM PDT 24
Peak memory 203152 kb
Host smart-bee11443-59ae-4a42-89bc-7b34e0a678b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26803
7696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.268037696
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.430488192
Short name T488
Test name
Test status
Simulation time 8401221512 ps
CPU time 8.15 seconds
Started Mar 17 01:43:16 PM PDT 24
Finished Mar 17 01:43:24 PM PDT 24
Peak memory 203648 kb
Host smart-2c07183e-17f0-4be9-bf76-a87c36ee15ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43048
8192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.430488192
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.3701586198
Short name T616
Test name
Test status
Simulation time 8390866695 ps
CPU time 7.32 seconds
Started Mar 17 01:43:17 PM PDT 24
Finished Mar 17 01:43:25 PM PDT 24
Peak memory 203680 kb
Host smart-e6aacd1f-ed0e-4b39-be40-1512bcdccf43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37015
86198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.3701586198
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1222558598
Short name T645
Test name
Test status
Simulation time 8361026956 ps
CPU time 9.24 seconds
Started Mar 17 01:43:16 PM PDT 24
Finished Mar 17 01:43:26 PM PDT 24
Peak memory 203548 kb
Host smart-5292b786-14a6-44bf-894b-a5740f9eb921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12225
58598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1222558598
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.631876986
Short name T12
Test name
Test status
Simulation time 8476933608 ps
CPU time 7.57 seconds
Started Mar 17 01:43:14 PM PDT 24
Finished Mar 17 01:43:22 PM PDT 24
Peak memory 203768 kb
Host smart-82c10ba4-ffa9-4ce0-921b-34ab2a5722b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63187
6986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.631876986
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.3372643059
Short name T739
Test name
Test status
Simulation time 8371513612 ps
CPU time 7.2 seconds
Started Mar 17 01:38:40 PM PDT 24
Finished Mar 17 01:38:48 PM PDT 24
Peak memory 203692 kb
Host smart-9c616e55-845b-4ffc-8fb6-cac4d41105d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33726
43059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3372643059
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1378903539
Short name T443
Test name
Test status
Simulation time 55054031 ps
CPU time 1.57 seconds
Started Mar 17 01:38:40 PM PDT 24
Finished Mar 17 01:38:41 PM PDT 24
Peak memory 203744 kb
Host smart-1fe606cc-66ec-4e9e-bac5-26d7d5e9ba52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13789
03539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1378903539
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.3993448458
Short name T395
Test name
Test status
Simulation time 8360026253 ps
CPU time 7.34 seconds
Started Mar 17 01:38:49 PM PDT 24
Finished Mar 17 01:38:56 PM PDT 24
Peak memory 203512 kb
Host smart-632a1b31-b169-4813-aa4b-31dc847de063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39934
48458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3993448458
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.583804320
Short name T614
Test name
Test status
Simulation time 8446214303 ps
CPU time 7.21 seconds
Started Mar 17 01:38:39 PM PDT 24
Finished Mar 17 01:38:46 PM PDT 24
Peak memory 203676 kb
Host smart-e8df24f5-d625-4bb5-b5e4-3a561ed2a4e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58380
4320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.583804320
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3602692139
Short name T384
Test name
Test status
Simulation time 8403118018 ps
CPU time 7.6 seconds
Started Mar 17 01:38:42 PM PDT 24
Finished Mar 17 01:38:49 PM PDT 24
Peak memory 203696 kb
Host smart-9ab87fa9-006a-4cc1-8abc-1f64fa2b01b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36026
92139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3602692139
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3027325184
Short name T317
Test name
Test status
Simulation time 8362993659 ps
CPU time 9.34 seconds
Started Mar 17 01:38:39 PM PDT 24
Finished Mar 17 01:38:48 PM PDT 24
Peak memory 203676 kb
Host smart-6651d442-faaa-4ff3-b4da-eaed76bbb1ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30273
25184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3027325184
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2344393882
Short name T99
Test name
Test status
Simulation time 8416784715 ps
CPU time 7.9 seconds
Started Mar 17 01:38:39 PM PDT 24
Finished Mar 17 01:38:47 PM PDT 24
Peak memory 203684 kb
Host smart-47695702-5c6a-4261-acf6-07b23d95b18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23443
93882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2344393882
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.1921197276
Short name T409
Test name
Test status
Simulation time 8393922686 ps
CPU time 8.01 seconds
Started Mar 17 01:38:40 PM PDT 24
Finished Mar 17 01:38:48 PM PDT 24
Peak memory 203528 kb
Host smart-b393bcea-92dd-42cb-a3dd-4daecac4ec4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19211
97276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.1921197276
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.686064787
Short name T485
Test name
Test status
Simulation time 8382520974 ps
CPU time 8.7 seconds
Started Mar 17 01:38:39 PM PDT 24
Finished Mar 17 01:38:47 PM PDT 24
Peak memory 203584 kb
Host smart-ce4759db-4ca2-4574-ba8e-2d990998422a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68606
4787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.686064787
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.4224128281
Short name T31
Test name
Test status
Simulation time 26116546 ps
CPU time 0.64 seconds
Started Mar 17 01:38:48 PM PDT 24
Finished Mar 17 01:38:49 PM PDT 24
Peak memory 203140 kb
Host smart-6856422a-84f4-4d84-9433-2682612f57b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42241
28281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.4224128281
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1206124949
Short name T670
Test name
Test status
Simulation time 8446073490 ps
CPU time 8.32 seconds
Started Mar 17 01:38:39 PM PDT 24
Finished Mar 17 01:38:47 PM PDT 24
Peak memory 203624 kb
Host smart-cf8c3b39-74ee-4a58-abc6-01399cc71f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12061
24949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1206124949
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.1086068209
Short name T304
Test name
Test status
Simulation time 8392352918 ps
CPU time 8.03 seconds
Started Mar 17 01:38:47 PM PDT 24
Finished Mar 17 01:38:55 PM PDT 24
Peak memory 203748 kb
Host smart-d14441a5-cc87-4fdd-a354-5445bd6d6d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10860
68209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.1086068209
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1645965167
Short name T564
Test name
Test status
Simulation time 8358574096 ps
CPU time 7.18 seconds
Started Mar 17 01:38:48 PM PDT 24
Finished Mar 17 01:38:56 PM PDT 24
Peak memory 203664 kb
Host smart-1375c061-0beb-4181-bb2d-707ddd5f299b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16459
65167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1645965167
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3275947358
Short name T142
Test name
Test status
Simulation time 8475952808 ps
CPU time 8.68 seconds
Started Mar 17 01:38:39 PM PDT 24
Finished Mar 17 01:38:47 PM PDT 24
Peak memory 203720 kb
Host smart-a08f41ee-7397-4003-86fe-ebb599deaa65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32759
47358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3275947358
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1009739167
Short name T653
Test name
Test status
Simulation time 8371202824 ps
CPU time 7.66 seconds
Started Mar 17 01:38:49 PM PDT 24
Finished Mar 17 01:38:57 PM PDT 24
Peak memory 203736 kb
Host smart-9c61e220-736a-46de-b10d-34cc2cf076b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10097
39167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1009739167
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1702194976
Short name T353
Test name
Test status
Simulation time 278201540 ps
CPU time 2.25 seconds
Started Mar 17 01:38:49 PM PDT 24
Finished Mar 17 01:38:51 PM PDT 24
Peak memory 203712 kb
Host smart-51e41b2d-e07f-4f20-9f43-6fe1d08803d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17021
94976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1702194976
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2793987843
Short name T156
Test name
Test status
Simulation time 8355978505 ps
CPU time 7.05 seconds
Started Mar 17 01:38:58 PM PDT 24
Finished Mar 17 01:39:05 PM PDT 24
Peak memory 203488 kb
Host smart-1b78548a-c37f-407a-8d55-ef7b53a9ba18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27939
87843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2793987843
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1002229618
Short name T128
Test name
Test status
Simulation time 8419468291 ps
CPU time 7.72 seconds
Started Mar 17 01:38:48 PM PDT 24
Finished Mar 17 01:38:57 PM PDT 24
Peak memory 203716 kb
Host smart-f86deeb7-bed3-47cc-937b-9760836ca6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10022
29618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1002229618
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.436162582
Short name T77
Test name
Test status
Simulation time 8406199831 ps
CPU time 9.21 seconds
Started Mar 17 01:38:48 PM PDT 24
Finished Mar 17 01:38:57 PM PDT 24
Peak memory 203664 kb
Host smart-aa5d6e6b-fbda-4f98-bf2e-d074fefa8e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43616
2582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.436162582
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2197894170
Short name T723
Test name
Test status
Simulation time 8368032035 ps
CPU time 7.11 seconds
Started Mar 17 01:38:50 PM PDT 24
Finished Mar 17 01:38:58 PM PDT 24
Peak memory 203656 kb
Host smart-be724d4e-2a53-4dd4-b47d-d87b1a6c3b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21978
94170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2197894170
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.442969180
Short name T108
Test name
Test status
Simulation time 8456086114 ps
CPU time 8.86 seconds
Started Mar 17 01:38:46 PM PDT 24
Finished Mar 17 01:38:55 PM PDT 24
Peak memory 203752 kb
Host smart-e189906f-10ff-41d9-94f7-2f2d3d99089c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44296
9180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.442969180
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3993735806
Short name T311
Test name
Test status
Simulation time 8362219762 ps
CPU time 7.38 seconds
Started Mar 17 01:38:59 PM PDT 24
Finished Mar 17 01:39:06 PM PDT 24
Peak memory 203516 kb
Host smart-76957ced-a7b0-4b47-ab48-32badc004ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39937
35806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3993735806
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.90250010
Short name T427
Test name
Test status
Simulation time 8401315827 ps
CPU time 8.23 seconds
Started Mar 17 01:38:57 PM PDT 24
Finished Mar 17 01:39:06 PM PDT 24
Peak memory 203436 kb
Host smart-775c4aa0-2070-47e0-aba4-185c1e8d65d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90250
010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.90250010
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.737145715
Short name T25
Test name
Test status
Simulation time 25693005 ps
CPU time 0.64 seconds
Started Mar 17 01:38:57 PM PDT 24
Finished Mar 17 01:38:58 PM PDT 24
Peak memory 203128 kb
Host smart-8e87c7f8-f66f-4003-b024-7dd69ed76750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73714
5715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.737145715
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2259408192
Short name T299
Test name
Test status
Simulation time 8442278052 ps
CPU time 9.97 seconds
Started Mar 17 01:38:56 PM PDT 24
Finished Mar 17 01:39:07 PM PDT 24
Peak memory 203676 kb
Host smart-677501cc-ebff-44bc-b367-b02e9bd05b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22594
08192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2259408192
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.3819902419
Short name T300
Test name
Test status
Simulation time 8371401102 ps
CPU time 9.8 seconds
Started Mar 17 01:38:55 PM PDT 24
Finished Mar 17 01:39:06 PM PDT 24
Peak memory 203736 kb
Host smart-df27548c-ade0-4ca9-8717-2b3fe9208451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38199
02419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.3819902419
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.3062363899
Short name T273
Test name
Test status
Simulation time 8356496316 ps
CPU time 7.66 seconds
Started Mar 17 01:38:57 PM PDT 24
Finished Mar 17 01:39:05 PM PDT 24
Peak memory 203572 kb
Host smart-fcc7a9f7-2f87-41db-b621-3a7d7a60ddf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30623
63899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.3062363899
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.4008012217
Short name T28
Test name
Test status
Simulation time 8472977488 ps
CPU time 7.66 seconds
Started Mar 17 01:38:46 PM PDT 24
Finished Mar 17 01:38:54 PM PDT 24
Peak memory 203700 kb
Host smart-6a887f65-045e-44bd-9eb9-90780ae6e218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40080
12217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.4008012217
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.208243971
Short name T202
Test name
Test status
Simulation time 8368646149 ps
CPU time 7.71 seconds
Started Mar 17 01:38:56 PM PDT 24
Finished Mar 17 01:39:05 PM PDT 24
Peak memory 203704 kb
Host smart-74ce4e9a-dfe5-4d43-9e93-f30880fdc6e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20824
3971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.208243971
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2097218431
Short name T548
Test name
Test status
Simulation time 105509492 ps
CPU time 1.42 seconds
Started Mar 17 01:39:07 PM PDT 24
Finished Mar 17 01:39:09 PM PDT 24
Peak memory 203788 kb
Host smart-695d84d9-ca61-4fe8-a26a-2733140c4504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20972
18431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2097218431
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3405150470
Short name T162
Test name
Test status
Simulation time 8363029057 ps
CPU time 7.61 seconds
Started Mar 17 01:39:04 PM PDT 24
Finished Mar 17 01:39:12 PM PDT 24
Peak memory 203476 kb
Host smart-05555846-d5d8-4f0e-afa2-6b05ae874689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34051
50470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3405150470
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2928023853
Short name T387
Test name
Test status
Simulation time 8394865188 ps
CPU time 7.19 seconds
Started Mar 17 01:39:05 PM PDT 24
Finished Mar 17 01:39:13 PM PDT 24
Peak memory 203688 kb
Host smart-7d96289d-f3bb-4796-8e0a-260a3be81c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29280
23853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2928023853
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3291311383
Short name T631
Test name
Test status
Simulation time 8407337204 ps
CPU time 8.2 seconds
Started Mar 17 01:39:05 PM PDT 24
Finished Mar 17 01:39:13 PM PDT 24
Peak memory 203668 kb
Host smart-7b0f55ce-f3b7-41b7-8141-fcff2b50e7d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32913
11383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3291311383
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.4095254992
Short name T316
Test name
Test status
Simulation time 8363656344 ps
CPU time 8.52 seconds
Started Mar 17 01:39:06 PM PDT 24
Finished Mar 17 01:39:15 PM PDT 24
Peak memory 203708 kb
Host smart-333934a4-2060-4112-888a-5a4222774b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40952
54992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.4095254992
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.2112877317
Short name T103
Test name
Test status
Simulation time 8421473777 ps
CPU time 10.04 seconds
Started Mar 17 01:39:05 PM PDT 24
Finished Mar 17 01:39:16 PM PDT 24
Peak memory 203716 kb
Host smart-4c0b68ed-6095-4a8d-bdf1-47443c5537b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21128
77317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.2112877317
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.1014185449
Short name T430
Test name
Test status
Simulation time 8399085823 ps
CPU time 7.84 seconds
Started Mar 17 01:39:06 PM PDT 24
Finished Mar 17 01:39:14 PM PDT 24
Peak memory 203584 kb
Host smart-727ab7a0-7dad-4b65-8919-959f07cf1551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10141
85449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.1014185449
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.4030292927
Short name T597
Test name
Test status
Simulation time 8378118507 ps
CPU time 7.09 seconds
Started Mar 17 01:39:05 PM PDT 24
Finished Mar 17 01:39:12 PM PDT 24
Peak memory 203528 kb
Host smart-322659eb-aa30-49b1-bc7f-fb64d8a8bfcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40302
92927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.4030292927
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2227392782
Short name T574
Test name
Test status
Simulation time 27176170 ps
CPU time 0.66 seconds
Started Mar 17 01:39:06 PM PDT 24
Finished Mar 17 01:39:07 PM PDT 24
Peak memory 203252 kb
Host smart-c1aaf4f0-951a-48d6-a8eb-07ef85a85ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22273
92782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2227392782
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.493999446
Short name T223
Test name
Test status
Simulation time 8412782146 ps
CPU time 7.82 seconds
Started Mar 17 01:39:06 PM PDT 24
Finished Mar 17 01:39:14 PM PDT 24
Peak memory 203712 kb
Host smart-271d0137-e4f3-4360-8792-60bf972a2bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49399
9446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.493999446
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.1612237575
Short name T230
Test name
Test status
Simulation time 8396044983 ps
CPU time 8.3 seconds
Started Mar 17 01:39:07 PM PDT 24
Finished Mar 17 01:39:15 PM PDT 24
Peak memory 203680 kb
Host smart-b8fb7e64-a153-47f8-9c2e-220c4adb1a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16122
37575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.1612237575
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2277814523
Short name T491
Test name
Test status
Simulation time 8358341262 ps
CPU time 7.06 seconds
Started Mar 17 01:39:07 PM PDT 24
Finished Mar 17 01:39:15 PM PDT 24
Peak memory 203588 kb
Host smart-2fbf541e-b29e-4acf-a2df-1bb884bd2ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22778
14523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2277814523
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2867758498
Short name T34
Test name
Test status
Simulation time 8480022493 ps
CPU time 7.72 seconds
Started Mar 17 01:38:58 PM PDT 24
Finished Mar 17 01:39:06 PM PDT 24
Peak memory 203688 kb
Host smart-c7e07d42-68f5-4d4d-b1e9-efe7d4343cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28677
58498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2867758498
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1591552400
Short name T637
Test name
Test status
Simulation time 8372768494 ps
CPU time 7.43 seconds
Started Mar 17 01:39:12 PM PDT 24
Finished Mar 17 01:39:20 PM PDT 24
Peak memory 203700 kb
Host smart-23f34d74-5c8e-497f-a278-6f1ea7bc4417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15915
52400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1591552400
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.4173882544
Short name T529
Test name
Test status
Simulation time 107425137 ps
CPU time 1.21 seconds
Started Mar 17 01:39:15 PM PDT 24
Finished Mar 17 01:39:16 PM PDT 24
Peak memory 203764 kb
Host smart-c9363415-a3cc-401e-84b3-99bb4b3801ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41738
82544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.4173882544
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1537998211
Short name T182
Test name
Test status
Simulation time 8360903872 ps
CPU time 6.9 seconds
Started Mar 17 01:39:12 PM PDT 24
Finished Mar 17 01:39:19 PM PDT 24
Peak memory 203456 kb
Host smart-6521b3a8-de62-4bdb-94d9-ab8fb87ac574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15379
98211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1537998211
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.61538058
Short name T691
Test name
Test status
Simulation time 8447564993 ps
CPU time 9.64 seconds
Started Mar 17 01:39:14 PM PDT 24
Finished Mar 17 01:39:24 PM PDT 24
Peak memory 203700 kb
Host smart-456b8335-68ff-4e0b-bcd0-d8202404a0ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61538
058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.61538058
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.242003552
Short name T577
Test name
Test status
Simulation time 8408426137 ps
CPU time 7.14 seconds
Started Mar 17 01:39:13 PM PDT 24
Finished Mar 17 01:39:20 PM PDT 24
Peak memory 203652 kb
Host smart-1304aeef-92b5-4420-8fcd-4f69a4cf5756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24200
3552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.242003552
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.4167979599
Short name T269
Test name
Test status
Simulation time 8363170039 ps
CPU time 7.02 seconds
Started Mar 17 01:39:14 PM PDT 24
Finished Mar 17 01:39:21 PM PDT 24
Peak memory 203704 kb
Host smart-b3e05917-79f3-44b9-a1c1-19999c83dca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41679
79599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.4167979599
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2084944435
Short name T743
Test name
Test status
Simulation time 8412122973 ps
CPU time 7.48 seconds
Started Mar 17 01:39:12 PM PDT 24
Finished Mar 17 01:39:19 PM PDT 24
Peak memory 203716 kb
Host smart-26dec057-174c-478a-bdf2-e255291c8022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20849
44435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2084944435
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3466895221
Short name T702
Test name
Test status
Simulation time 8373959201 ps
CPU time 8.51 seconds
Started Mar 17 01:39:11 PM PDT 24
Finished Mar 17 01:39:20 PM PDT 24
Peak memory 203684 kb
Host smart-285665c0-fa60-4b69-b614-acb3a3693028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34668
95221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3466895221
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3316283383
Short name T255
Test name
Test status
Simulation time 8394686241 ps
CPU time 7.79 seconds
Started Mar 17 01:39:11 PM PDT 24
Finished Mar 17 01:39:20 PM PDT 24
Peak memory 203568 kb
Host smart-00a481d6-60ba-4cfb-a7bf-e8a8c6bea4d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33162
83383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3316283383
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2285203616
Short name T600
Test name
Test status
Simulation time 30339988 ps
CPU time 0.64 seconds
Started Mar 17 01:39:14 PM PDT 24
Finished Mar 17 01:39:14 PM PDT 24
Peak memory 203212 kb
Host smart-6253d6d2-a7c8-44bc-9206-e9eb9067d906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22852
03616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2285203616
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3044475506
Short name T556
Test name
Test status
Simulation time 8440629109 ps
CPU time 7.92 seconds
Started Mar 17 01:39:12 PM PDT 24
Finished Mar 17 01:39:20 PM PDT 24
Peak memory 203712 kb
Host smart-d24f246a-ac0d-4eb4-9a51-d5aeb510d968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30444
75506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3044475506
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.1832765877
Short name T307
Test name
Test status
Simulation time 8378981420 ps
CPU time 9.43 seconds
Started Mar 17 01:39:13 PM PDT 24
Finished Mar 17 01:39:22 PM PDT 24
Peak memory 203632 kb
Host smart-7ccdd230-3ab4-48dd-a707-d1e1250fd5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18327
65877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.1832765877
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.3359794597
Short name T480
Test name
Test status
Simulation time 8362285710 ps
CPU time 8.57 seconds
Started Mar 17 01:39:12 PM PDT 24
Finished Mar 17 01:39:21 PM PDT 24
Peak memory 203612 kb
Host smart-9e1c37b0-4a0d-4c92-b92f-23ba35cdf360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33597
94597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.3359794597
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2366088067
Short name T116
Test name
Test status
Simulation time 8475760980 ps
CPU time 8.18 seconds
Started Mar 17 01:39:05 PM PDT 24
Finished Mar 17 01:39:14 PM PDT 24
Peak memory 203692 kb
Host smart-aafcf881-51ae-43c9-a52f-b07719a5803e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23660
88067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2366088067
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1001496977
Short name T312
Test name
Test status
Simulation time 8368820096 ps
CPU time 8 seconds
Started Mar 17 01:39:09 PM PDT 24
Finished Mar 17 01:39:19 PM PDT 24
Peak memory 203676 kb
Host smart-184961b0-6c0d-44bf-8e44-92b5808f748f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10014
96977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1001496977
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.2278366680
Short name T279
Test name
Test status
Simulation time 114649143 ps
CPU time 1.12 seconds
Started Mar 17 01:39:13 PM PDT 24
Finished Mar 17 01:39:14 PM PDT 24
Peak memory 203604 kb
Host smart-284f2dfe-4446-45db-8c94-b740b03ed959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22783
66680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.2278366680
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.585417373
Short name T482
Test name
Test status
Simulation time 8362648294 ps
CPU time 7.94 seconds
Started Mar 17 01:39:16 PM PDT 24
Finished Mar 17 01:39:24 PM PDT 24
Peak memory 203480 kb
Host smart-c544795e-442d-4910-b058-d09ef3fe6d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58541
7373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.585417373
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1482420232
Short name T131
Test name
Test status
Simulation time 8456806141 ps
CPU time 8.04 seconds
Started Mar 17 01:39:13 PM PDT 24
Finished Mar 17 01:39:21 PM PDT 24
Peak memory 203740 kb
Host smart-0f55fe03-8b6d-4ae0-b8d9-97966528ea5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14824
20232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1482420232
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.2230597294
Short name T581
Test name
Test status
Simulation time 8411101179 ps
CPU time 9.06 seconds
Started Mar 17 01:39:12 PM PDT 24
Finished Mar 17 01:39:21 PM PDT 24
Peak memory 203696 kb
Host smart-03d29805-743f-4b01-9a70-f9dea6530009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22305
97294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.2230597294
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3315778399
Short name T539
Test name
Test status
Simulation time 8365791563 ps
CPU time 8.43 seconds
Started Mar 17 01:39:13 PM PDT 24
Finished Mar 17 01:39:22 PM PDT 24
Peak memory 203700 kb
Host smart-4c596b3a-2432-47c2-9959-26c7f7331e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33157
78399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3315778399
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.789342002
Short name T95
Test name
Test status
Simulation time 8422963719 ps
CPU time 7.48 seconds
Started Mar 17 01:39:11 PM PDT 24
Finished Mar 17 01:39:19 PM PDT 24
Peak memory 203672 kb
Host smart-bfaaca77-ae83-49ee-a036-6a3f63fdd70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78934
2002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.789342002
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.642029690
Short name T535
Test name
Test status
Simulation time 8374923004 ps
CPU time 7.88 seconds
Started Mar 17 01:39:15 PM PDT 24
Finished Mar 17 01:39:24 PM PDT 24
Peak memory 203600 kb
Host smart-a41d79bb-ffc7-406d-b681-9f62204372e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64202
9690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.642029690
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.856174875
Short name T623
Test name
Test status
Simulation time 8386223307 ps
CPU time 7.42 seconds
Started Mar 17 01:39:18 PM PDT 24
Finished Mar 17 01:39:25 PM PDT 24
Peak memory 203664 kb
Host smart-437a9216-9659-45d4-ba6f-1d0e86881229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85617
4875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.856174875
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3107073481
Short name T30
Test name
Test status
Simulation time 30251980 ps
CPU time 0.64 seconds
Started Mar 17 01:39:19 PM PDT 24
Finished Mar 17 01:39:20 PM PDT 24
Peak memory 203164 kb
Host smart-7346c7b7-1333-48ec-badc-e1caa2dd13c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31070
73481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3107073481
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2617819516
Short name T469
Test name
Test status
Simulation time 8462606471 ps
CPU time 8.07 seconds
Started Mar 17 01:39:16 PM PDT 24
Finished Mar 17 01:39:24 PM PDT 24
Peak memory 203712 kb
Host smart-2ca574aa-538e-4193-b4c8-94d6e2b11364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26178
19516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2617819516
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.2371590051
Short name T404
Test name
Test status
Simulation time 8403754498 ps
CPU time 8.25 seconds
Started Mar 17 01:39:16 PM PDT 24
Finished Mar 17 01:39:25 PM PDT 24
Peak memory 203696 kb
Host smart-c8a26d6e-9857-417e-8774-181accc058bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23715
90051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.2371590051
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2735774281
Short name T348
Test name
Test status
Simulation time 8360913591 ps
CPU time 8.44 seconds
Started Mar 17 01:39:18 PM PDT 24
Finished Mar 17 01:39:26 PM PDT 24
Peak memory 203532 kb
Host smart-6ee58eba-ab23-4875-8e8a-f525a07478fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27357
74281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2735774281
Directory /workspace/9.usbdev_setup_trans_ignored/latest
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