Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43702	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	55765	1		T1	6		T2	208		T3	8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37288	1		T1	6		T2	153		T3	4
values[0x0]	30963	1		T1	3		T2	325		T3	3
values[0x1]	31216	1		T1	7		T2	298		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34852	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	64615	1		T1	8		T2	268		T3	10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	344	1		T38	1		T91	10		T213	9
valid_sources[0x01]	351	1		T38	4		T52	6		T213	2
valid_sources[0x02]	319	1		T38	3		T52	4		T91	9
valid_sources[0x03]	333	1		T38	5		T12	1		T14	1
valid_sources[0x04]	269	1		T38	2		T28	1		T52	7
valid_sources[0x05]	296	1		T38	3		T52	2		T91	15
valid_sources[0x06]	403	1		T38	3		T12	1		T52	1
valid_sources[0x07]	411	1		T38	2		T28	1		T219	3
valid_sources[0x08]	627	1		T1	2		T38	1		T52	2
valid_sources[0x09]	341	1		T38	1		T30	2		T52	3
valid_sources[0x0a]	1277	1		T38	2		T52	3		T213	8
valid_sources[0x0b]	337	1		T127	5		T52	1		T213	8
valid_sources[0x0c]	1231	1		T38	2		T12	1		T30	1
valid_sources[0x0d]	334	1		T38	2		T28	1		T52	5
valid_sources[0x0e]	341	1		T38	2		T28	1		T52	2
valid_sources[0x0f]	330	1		T38	2		T11	1		T52	7
valid_sources[0x10]	318	1		T38	1		T52	2		T91	32
valid_sources[0x11]	264	1		T38	3		T52	3		T91	3
valid_sources[0x12]	303	1		T38	1		T14	1		T52	2
valid_sources[0x13]	289	1		T38	3		T52	4		T91	19
valid_sources[0x14]	327	1		T38	5		T11	1		T20	2
valid_sources[0x15]	294	1		T38	4		T52	7		T267	1
valid_sources[0x16]	289	1		T38	3		T52	1		T91	3
valid_sources[0x17]	414	1		T38	2		T52	1		T91	9
valid_sources[0x18]	436	1		T9	5		T38	3		T268	1
valid_sources[0x19]	352	1		T38	1		T20	1		T267	1
valid_sources[0x1a]	1554	1		T2	776		T38	2		T11	3
valid_sources[0x1b]	316	1		T38	5		T12	1		T52	2
valid_sources[0x1c]	322	1		T3	12		T38	3		T39	3
valid_sources[0x1d]	297	1		T38	5		T14	3		T52	5
valid_sources[0x1e]	288	1		T38	3		T52	1		T213	5
valid_sources[0x1f]	275	1		T38	3		T52	1		T128	2
valid_sources[0x20]	324	1		T38	1		T21	1		T52	1
valid_sources[0x21]	375	1		T11	1		T213	10		T269	4
valid_sources[0x22]	314	1		T270	1		T213	2		T269	1
valid_sources[0x23]	298	1		T38	1		T52	4		T26	1
valid_sources[0x24]	320	1		T9	5		T38	5		T52	1
valid_sources[0x25]	283	1		T5	1		T38	6		T271	2
valid_sources[0x26]	342	1		T38	1		T139	1		T128	1
valid_sources[0x27]	345	1		T8	1		T38	2		T52	5
valid_sources[0x28]	405	1		T5	1		T8	3		T38	3
valid_sources[0x29]	313	1		T38	1		T39	2		T20	2
valid_sources[0x2a]	358	1		T38	3		T52	1		T213	10
valid_sources[0x2b]	337	1		T38	4		T219	2		T52	3
valid_sources[0x2c]	310	1		T38	2		T139	1		T52	6
valid_sources[0x2d]	274	1		T38	1		T52	4		T91	3
valid_sources[0x2e]	327	1		T38	2		T52	3		T213	4
valid_sources[0x2f]	351	1		T38	3		T127	1		T52	7
valid_sources[0x30]	310	1		T38	4		T39	1		T52	4
valid_sources[0x31]	264	1		T1	2		T38	3		T30	1
valid_sources[0x32]	357	1		T38	4		T52	1		T91	5
valid_sources[0x33]	354	1		T5	1		T38	4		T12	1
valid_sources[0x34]	325	1		T38	4		T210	1		T52	2
valid_sources[0x35]	732	1		T38	3		T47	3		T52	5
valid_sources[0x36]	250	1		T38	4		T52	3		T272	1
valid_sources[0x37]	346	1		T50	1		T52	3		T91	36
valid_sources[0x38]	409	1		T38	2		T52	3		T91	56
valid_sources[0x39]	396	1		T1	1		T38	4		T52	5
valid_sources[0x3a]	367	1		T38	1		T52	1		T95	1
valid_sources[0x3b]	470	1		T38	1		T271	1		T52	3
valid_sources[0x3c]	475	1		T38	1		T52	1		T91	11
valid_sources[0x3d]	419	1		T11	1		T41	10		T45	1
valid_sources[0x3e]	293	1		T38	2		T51	3		T39	1
valid_sources[0x3f]	393	1		T38	4		T15	20		T52	1
valid_sources[0x40]	268	1		T38	2		T52	5		T213	2
valid_sources[0x41]	284	1		T38	3		T47	2		T52	2
valid_sources[0x42]	480	1		T38	6		T30	1		T52	2
valid_sources[0x43]	397	1		T38	3		T127	2		T52	1
valid_sources[0x44]	255	1		T38	4		T213	1		T269	1
valid_sources[0x45]	295	1		T38	2		T52	3		T143	1
valid_sources[0x46]	249	1		T5	1		T38	2		T52	1
valid_sources[0x47]	327	1		T38	2		T52	2		T27	1
valid_sources[0x48]	354	1		T38	6		T52	3		T213	1
valid_sources[0x49]	515	1		T38	1		T52	1		T273	1
valid_sources[0x4a]	295	1		T1	1		T8	1		T38	1
valid_sources[0x4b]	281	1		T38	1		T11	1		T17	2
valid_sources[0x4c]	360	1		T38	3		T52	2		T16	4
valid_sources[0x4d]	374	1		T38	4		T52	6		T128	1
valid_sources[0x4e]	395	1		T38	3		T11	2		T23	7
valid_sources[0x4f]	338	1		T38	2		T52	2		T274	8
valid_sources[0x50]	342	1		T38	2		T210	1		T52	3
valid_sources[0x51]	367	1		T10	3		T139	2		T52	1
valid_sources[0x52]	375	1		T38	3		T30	1		T139	2
valid_sources[0x53]	290	1		T1	1		T38	1		T213	5
valid_sources[0x54]	297	1		T38	3		T52	3		T25	1
valid_sources[0x55]	270	1		T10	5		T38	1		T52	4
valid_sources[0x56]	298	1		T38	4		T30	1		T52	2
valid_sources[0x57]	282	1		T38	1		T52	5		T128	1
valid_sources[0x58]	317	1		T38	1		T11	1		T46	2
valid_sources[0x59]	301	1		T38	2		T52	3		T213	3
valid_sources[0x5a]	338	1		T6	8		T38	1		T11	1
valid_sources[0x5b]	268	1		T38	5		T52	1		T213	3
valid_sources[0x5c]	384	1		T38	4		T12	1		T52	1
valid_sources[0x5d]	729	1		T38	1		T11	2		T20	2
valid_sources[0x5e]	314	1		T38	2		T52	4		T275	1
valid_sources[0x5f]	252	1		T38	2		T46	1		T52	1
valid_sources[0x60]	302	1		T38	6		T52	2		T91	11
valid_sources[0x61]	295	1		T38	4		T39	1		T52	1
valid_sources[0x62]	312	1		T12	1		T52	3		T91	3
valid_sources[0x63]	294	1		T38	2		T52	1		T213	7
valid_sources[0x64]	253	1		T38	3		T11	2		T52	6
valid_sources[0x65]	321	1		T5	1		T38	3		T52	1
valid_sources[0x66]	324	1		T38	1		T271	1		T47	4
valid_sources[0x67]	305	1		T38	2		T52	4		T213	6
valid_sources[0x68]	342	1		T5	1		T38	2		T52	2
valid_sources[0x69]	336	1		T38	2		T14	1		T52	2
valid_sources[0x6a]	304	1		T1	1		T38	3		T30	1
valid_sources[0x6b]	312	1		T38	4		T11	2		T52	4
valid_sources[0x6c]	413	1		T210	1		T28	1		T52	4
valid_sources[0x6d]	308	1		T210	1		T139	2		T276	1
valid_sources[0x6e]	366	1		T38	1		T51	1		T52	2
valid_sources[0x6f]	316	1		T9	2		T38	2		T45	1
valid_sources[0x70]	306	1		T5	1		T38	3		T14	1
valid_sources[0x71]	326	1		T38	4		T49	1		T52	1
valid_sources[0x72]	408	1		T38	2		T52	1		T213	3
valid_sources[0x73]	400	1		T38	2		T52	2		T26	1
valid_sources[0x74]	304	1		T18	10		T38	2		T52	5
valid_sources[0x75]	232	1		T38	2		T275	1		T213	5
valid_sources[0x76]	301	1		T38	1		T49	3		T210	1
valid_sources[0x77]	343	1		T1	2		T38	1		T52	1
valid_sources[0x78]	329	1		T38	1		T39	1		T52	3
valid_sources[0x79]	399	1		T38	1		T51	1		T45	1
valid_sources[0x7a]	288	1		T38	4		T139	2		T52	2
valid_sources[0x7b]	441	1		T7	20		T38	2		T11	4
valid_sources[0x7c]	928	1		T38	1		T52	2		T213	2
valid_sources[0x7d]	514	1		T38	1		T49	1		T210	1
valid_sources[0x7e]	476	1		T38	4		T11	2		T45	1
valid_sources[0x7f]	382	1		T38	3		T26	1		T213	3
valid_sources[0x80]	328	1		T38	2		T22	5		T52	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

20921

1

T1

2

T2

68

T3

4

values[0x0]

all_enables

biggest_size

19436

1

T1

1

T2

97

T3

2

values[0x1]

all_enables

biggest_size

15408

1

T1

3

T2

43

T3

2