Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.25	96.75	68.07	93.93		87.50	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	278706412	9134	0	0
ep_in_enable_rd_A	278706412	529	0	0
ep_out_enable_rd_A	278706412	444	0	0
in_iso_rd_A	278706412	544	0	0
intr_enable_rd_A	278706412	756	0	0
out_iso_rd_A	278706412	669	0	0
phy_config_rd_A	278706412	253	0	0
phy_pins_drive_rd_A	278706412	668	0	0
rxenable_setup_rd_A	278706412	632	0	0
set_nak_out_rd_A	278706412	452	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278706412	9134	0	0
T54	4863	198	0	0
T55	4991	262	0	0
T56	4530	314	0	0
T192	11842	724	0	0
T193	4700	310	0	0
T194	6015	353	0	0
T195	3057	503	0	0
T196	7066	14	0	0
T197	3696	9	0	0
T198	3424	592	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278706412	529	0	0
T60	2625	6	0	0
T70	3195	46	0	0
T94	3666	78	0	0
T177	7263	41	0	0
T196	7066	43	0	0
T197	3696	53	0	0
T204	3308	41	0	0
T205	9588	39	0	0
T253	3683	56	0	0
T254	6751	36	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278706412	444	0	0
T54	4863	1	0	0
T60	2625	3	0	0
T70	3195	31	0	0
T94	3666	68	0	0
T196	7066	14	0	0
T197	3696	51	0	0
T204	3308	32	0	0
T205	9588	52	0	0
T253	3683	12	0	0
T254	6751	71	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278706412	544	0	0
T60	2625	11	0	0
T61	2420	9	0	0
T70	3195	7	0	0
T94	3666	36	0	0
T196	7066	46	0	0
T197	3696	68	0	0
T204	3308	41	0	0
T205	9588	40	0	0
T253	3683	12	0	0
T254	6751	62	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278706412	756	0	0
T61	2420	7	0	0
T70	3195	3	0	0
T78	1223	13	0	0
T79	1436	14	0	0
T80	1426	18	0	0
T94	3666	93	0	0
T196	7066	139	0	0
T204	3308	76	0	0
T255	1206	11	0	0
T256	1097	9	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278706412	669	0	0
T60	2625	14	0	0
T61	2420	6	0	0
T70	3195	49	0	0
T94	3666	83	0	0
T196	7066	37	0	0
T197	3696	59	0	0
T204	3308	48	0	0
T205	9588	89	0	0
T253	3683	11	0	0
T254	6751	46	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278706412	253	0	0
T60	2625	7	0	0
T61	2420	8	0	0
T70	3195	16	0	0
T94	3666	9	0	0
T196	7066	5	0	0
T197	3696	5	0	0
T204	3308	20	0	0
T205	9588	68	0	0
T253	3683	4	0	0
T254	6751	37	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278706412	668	0	0
T60	2625	2	0	0
T70	3195	14	0	0
T94	3666	82	0	0
T177	7263	59	0	0
T196	7066	71	0	0
T197	3696	10	0	0
T204	3308	71	0	0
T205	9588	106	0	0
T253	3683	26	0	0
T254	6751	68	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278706412	632	0	0
T60	2625	7	0	0
T70	3195	70	0	0
T94	3666	54	0	0
T177	7263	53	0	0
T196	7066	25	0	0
T197	3696	52	0	0
T204	3308	35	0	0
T205	9588	80	0	0
T253	3683	7	0	0
T254	6751	16	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278706412	452	0	0
T60	2625	6	0	0
T61	2420	3	0	0
T70	3195	55	0	0
T94	3666	5	0	0
T196	7066	67	0	0
T197	3696	51	0	0
T204	3308	6	0	0
T205	9588	69	0	0
T253	3683	6	0	0
T254	6751	39	0	0