Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T25,T26,T27 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T25,T26,T27 |
1 | 0 | Covered | T25,T26,T27 |
1 | 1 | Covered | T25,T26,T27 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T25,T26,T27 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
58918 |
55279 |
0 |
0 |
selKnown1 |
106 |
0 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
58918 |
55279 |
0 |
0 |
T1 |
45 |
40 |
0 |
0 |
T2 |
3 |
0 |
0 |
0 |
T3 |
25 |
20 |
0 |
0 |
T4 |
25 |
20 |
0 |
0 |
T5 |
188 |
183 |
0 |
0 |
T6 |
25 |
20 |
0 |
0 |
T7 |
84 |
79 |
0 |
0 |
T8 |
25 |
20 |
0 |
0 |
T9 |
45 |
40 |
0 |
0 |
T10 |
25 |
20 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T14 |
0 |
4 |
0 |
0 |
T18 |
2 |
20 |
0 |
0 |
T22 |
0 |
2 |
0 |
0 |
T28 |
0 |
2 |
0 |
0 |
T29 |
0 |
2 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
106 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T25,T26,T27 |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
880 |
240 |
0 |
0 |
selKnown1 |
0 |
0 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
880 |
240 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
2 |
1 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T22 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
1 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 6 | 66.67 |
Logical | 9 | 6 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T25,T26,T27 |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T25,T27,T31 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
19301 |
18506 |
0 |
0 |
selKnown1 |
0 |
0 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19301 |
18506 |
0 |
0 |
T1 |
14 |
13 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
8 |
7 |
0 |
0 |
T4 |
8 |
7 |
0 |
0 |
T5 |
62 |
61 |
0 |
0 |
T6 |
8 |
7 |
0 |
0 |
T7 |
27 |
26 |
0 |
0 |
T8 |
8 |
7 |
0 |
0 |
T9 |
14 |
13 |
0 |
0 |
T10 |
8 |
7 |
0 |
0 |
T18 |
0 |
7 |
0 |
0 |
Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 7 | 77.78 |
Logical | 9 | 7 | 77.78 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T25,T26,T27 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T25,T26,T27 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T25,T26,T27 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
880 |
240 |
0 |
0 |
T1 |
2 |
1 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
2 |
1 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
2 |
1 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T22 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T29 |
0 |
1 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
50 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T26,T27,T31 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T26,T27,T31 |
1 | 0 | Covered | T25,T32,T33 |
1 | 1 | Covered | T26,T27,T31 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T25,T27,T31 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
19301 |
18506 |
0 |
0 |
T1 |
14 |
13 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
8 |
7 |
0 |
0 |
T4 |
8 |
7 |
0 |
0 |
T5 |
62 |
61 |
0 |
0 |
T6 |
8 |
7 |
0 |
0 |
T7 |
27 |
26 |
0 |
0 |
T8 |
8 |
7 |
0 |
0 |
T9 |
14 |
13 |
0 |
0 |
T10 |
8 |
7 |
0 |
0 |
T18 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
26 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T25,T26,T27 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T25,T26,T27 |
1 | 0 | Covered | T34,T35,T36 |
1 | 1 | Covered | T25,T26,T27 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T26,T34,T37 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
18556 |
17787 |
0 |
0 |
T1 |
13 |
12 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
7 |
6 |
0 |
0 |
T4 |
7 |
6 |
0 |
0 |
T5 |
60 |
59 |
0 |
0 |
T6 |
7 |
6 |
0 |
0 |
T7 |
26 |
25 |
0 |
0 |
T8 |
7 |
6 |
0 |
0 |
T9 |
13 |
12 |
0 |
0 |
T10 |
7 |
6 |
0 |
0 |
T18 |
0 |
6 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
30 |
0 |
0 |
0 |