Unified Coverage Report :: Module :: usbdev_usbif

Module : usbdev_usbif

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.61	97.06	94.20			91.18	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl	95.61	97.06	94.20			91.18	100.00

---

Module Instance : tb.dut.usbdev_impl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.61	97.06	94.20			91.18	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.98	91.70	82.08		46.88	84.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.25	96.75	68.07	93.93		87.50	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_usb_fs_nb_pe	84.15	93.54	82.59		56.76	87.87	100.00
u_usbdev_linkstate	69.72	79.69	69.41		33.33	66.18	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev_usbif

	Line No.	Total	Covered	Percent
TOTAL		68	66	97.06
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	142	0	0
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
ALWAYS	150	6	6	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	176	6	6	100.00
ALWAYS	188	8	8	100.00
CONT_ASSIGN	205	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	219	1	1	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	227	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
ALWAYS	236	5	5	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	266	0	0
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
ALWAYS	273	2	2	100.00
ALWAYS	280	3	3	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	384	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
ALWAYS	388	5	3	60.00
ALWAYS	397	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
142		unreachable
143	1	1
145	1	1
146	1	1
147	1	1
150	1	1
151	1	1
153	1	1
157	1	1
158	1	1
159		unreachable
160		unreachable
162		unreachable
166	1	1
172	1	1
176	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
196	1	1
197	1	1
			MISSING_ELSE
205	1	1
206	1	1
211	1	1
214	1	1
216	1	1
217	1	1
218	1	1
219	1	1
221	1	1
225	1	1
227	1	1
233	1	1
236	1	1
237	1	1
238	1	1
240	1	1
241	1	1
246	1	1
248	1	1
250	1	1
251	1	1
256	1	1
266		unreachable
267	1	1
271	1	1
273	1	1
274	1	1
280	1	1
281	1	1
283	1	1
287	1	1
288	1	1
290	1	1
384	1	1
385	1	1
388	1	1
389	1	1
390	0	1
391	1	1
392	0	1
			MISSING_ELSE
397	1	1
398	1	1
400	1	1

---

Cond Coverage for Module : usbdev_usbif

	Total	Covered	Percent
Conditions	69	65	94.20
Logical	69	65	94.20
Non-Logical	0	0
Event	0	0

 LINE       124
 EXPRESSION (connect_en_i & usb_sense_i)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       143
 EXPRESSION (out_endpoint_val_o ? out_ep_current : '0)
             ---------1--------

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (((~connect_en_i)) | link_reset)
             --------1--------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       150
 EXPRESSION (out_ep_acked || out_ep_rollback)
             ------1-----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T4,T6

 LINE       172
 EXPRESSION (out_ep_data_put & (int'(out_max_used_q) < (MaxPktSizeByte - 1)) & (out_ep_put_addr[1:0] == 2'b11))
             -------1-------   ----------------------2----------------------   ---------------3---------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T6
1	0	1	Unreachable	T6,T11,T17
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T1,T4,T6

 LINE       172
 SUB-EXPRESSION (out_ep_put_addr[1:0] == 2'b11)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       205
 EXPRESSION (current_setup ? avsetup_rvalid_i : avout_rvalid_i)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T14,T15

 LINE       206
 EXPRESSION (current_setup ? avsetup_rdata_i : avout_rdata_i)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T14,T15

 LINE       211
 EXPRESSION (current_setup ? rx_wready_setup_i : rx_wready_out_i)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T14,T15

 LINE       214
 EXPRESSION (av_rvalid & (std_write_q | (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked)))
             ----1----   ---------------------------------------------2---------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

 LINE       214
 SUB-EXPRESSION (std_write_q | (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked))
                 -----1-----   -------------------------------------2-------------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T4,T6

 LINE       214
 SUB-EXPRESSION (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked)
                 ------------1------------   ---------------2--------------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T11,T17
1	0	1	Covered	T1,T4,T210
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T5,T7,T8

 LINE       214
 SUB-EXPRESSION (out_max_used_q[1:0] != 2'b11)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       218
 EXPRESSION (mem_write_o ? mem_waddr : mem_raddr)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       219
 EXPRESSION (mem_read | mem_write_o)
             ----1---   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T6
1	0	Covered	T5,T7,T11

 LINE       240
 EXPRESSION (rx_wvalid_o & current_setup)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T11,T14,T15
1	0	Covered	T1,T4,T6
1	1	Covered	T11,T14,T15

 LINE       241
 EXPRESSION (rx_wvalid_o & ((~current_setup)))
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T14,T15
1	1	Covered	T1,T4,T6

 LINE       248
 EXPRESSION (((~rx_wready)) | ((~av_rvalid)))
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       256
 EXPRESSION (current_setup & rx_wvalid_o)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T11,T14,T15
1	1	Covered	T11,T14,T15

 LINE       267
 EXPRESSION (in_endpoint_val_o ? in_ep_current : '0)
             --------1--------

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       271
 EXPRESSION ({1'b0, in_ep_get_addr} == in_size_i)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       288
 EXPRESSION (pkt_start_rd | (in_ep_data_get & (in_ep_get_addr[1:0] == 2'b0)))
             ------1-----   ------------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T11
1	0	Covered	T5,T7,T11

 LINE       288
 SUB-EXPRESSION (in_ep_data_get & (in_ep_get_addr[1:0] == 2'b0))
                 -------1------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T11
1	1	Covered	T5,T7,T11

 LINE       288
 SUB-EXPRESSION (in_ep_get_addr[1:0] == 2'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (in_ep_get_addr[1] ? (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16]) : (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0]))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T11

 LINE       290
 SUB-EXPRESSION (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16])
                 --------1--------

-1-	Status	Tests
0	Covered	T5,T7,T11
1	Covered	T5,T7,T11

 LINE       290
 SUB-EXPRESSION (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0])
                 --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T11

 LINE       385
 EXPRESSION (frame_q != frame_d)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Module : usbdev_usbif

	Line No.	Total	Covered	Percent
Branches		34	31	91.18
TERNARY	143	1	1	100.00
TERNARY	205	2	2	100.00
TERNARY	206	2	2	100.00
TERNARY	211	2	2	100.00
TERNARY	218	2	2	100.00
TERNARY	267	1	1	100.00
TERNARY	290	4	4	100.00
IF	150	3	3	100.00
CASE	178	5	4	80.00
IF	188	3	3	100.00
IF	236	2	2	100.00
IF	280	2	2	100.00
IF	389	3	1	33.33
IF	397	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	143	(out_endpoint_val_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	205	(current_setup) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	206	(current_setup) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	211	(current_setup) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	218	(mem_write_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	267	(in_endpoint_val_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	290	(in_ep_get_addr[1]) ? 
-2-:	290	(in_ep_get_addr[0]) ? 
-3-:	290	(in_ep_get_addr[0]) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T5,T7,T11
1	0	-	Covered	T5,T7,T11
0	-	1	Covered	T5,T7,T11
0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	150	if ((out_ep_acked || out_ep_rollback))
-2-:	153	if (out_ep_data_put)
-3-:	157	if ((int'(out_max_used_q) < (MaxPktSizeByte - 1)))
-4-:	159	if ((int'(out_max_used_q) < (MaxPktSizeByte + 1)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T3,T4
0	1	1	-	Covered	T1,T3,T4
0	1	0	1	Unreachable	T6,T11,T17
0	1	0	0	Unreachable
0	0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	case (out_ep_put_addr[1:0])

Branches:

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4
2	Covered	T1,T4,T6
3	Covered	T1,T4,T6
default	Not Covered

	LineNo.	Expression
-1-:	188	if ((!rst_ni))
-2-:	196	if (out_ep_data_put)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	236	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	280	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	389	if (sof_valid_o)
-2-:	391	if (do_internal_sof)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev_usbif

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ParamAVFifoWidthValid	795	795	0	0
ParamMaxPktSizeByteValid	795	795	0	0
ParamNBufValid	795	795	0	0
ParamNEndpointsValid	795	795	0	0
ParamRXFifoWidthValid	795	795	0	0
ParamSramAwValid	795	795	0	0

ParamAVFifoWidthValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ParamMaxPktSizeByteValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ParamNBufValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ParamNEndpointsValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ParamRXFifoWidthValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

ParamSramAwValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	795	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0