Unified Coverage Report :: Module :: usb_fs_nb_in_pe

Module : usb_fs_nb_in_pe

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.84	87.61	81.18		58.33	77.08	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe	80.84	87.61	81.18		58.33	77.08	100.00

---

Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.84	87.61	81.18		58.33	77.08	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.84	87.61	81.18		58.33	77.08	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	50.00				100.00	u_usb_fs_nb_pe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usb_fs_nb_in_pe

	Line No.	Total	Covered	Percent
TOTAL		113	99	87.61
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
ALWAYS	187	49	36	73.47
ALWAYS	289	3	3	100.00
ALWAYS	297	3	3	100.00
ALWAYS	305	8	8	100.00
ALWAYS	318	6	6	100.00
ALWAYS	330	9	9	100.00
ALWAYS	347	7	6	85.71
CONT_ASSIGN	361	1	1	100.00
ALWAYS	364	5	5	100.00
ALWAYS	374	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
125	1	1
126	1	1
128	1	1
134	1	1
138	1	1
142	1	1
148	1	1
149	1	1
156	1	1
157	1	1
160	1	1
166	1	1
168	1	1
174	1	1
176	1	1
177	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
195	1	1
196	1	1
199	1	1
204	1	1
206	1	1
211	0	1
212	0	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
220	0	1
221	0	1
227	1	1
228	1	1
229	0	1
230	0	1
232	1	1
233	0	1
235	1	1
239	1	1
244	1	1
245	1	1
			MISSING_ELSE
253	1	1
255	1	1
256	1	1
257	1	1
258	0	1
259	0	1
261	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	0	1
271	0	1
272	1	1
273	0	1
274	0	1
276	1	1
289	1	1
290	1	1
292	1	1
297	1	1
298	1	1
300	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
312	1	1
313	1	1
318	1	1
319	1	1
321	1	1
322	1	1
323	1	1
324	1	1
			MISSING_ELSE
330	1	1
331	1	1
332	1	1
333	1	1
335	1	1
336	1	1
337	1	1
338	1	1
340	1	1
347	1	1
349	1	1
350	1	1
351	1	1
352	1	1
			MISSING_ELSE
355	1	1
356	0	1
			MISSING_ELSE
361	1	1
364	1	1
365	1	1
366	1	1
367	1	1
369	1	1
374	1	1
375	1	1
377	1	1
378	1	1
380	1	1

---

Cond Coverage for Module : usb_fs_nb_in_pe

	Total	Covered	Percent
Conditions	85	69	81.18
Logical	85	69	81.18
Non-Logical	0	0
Event	0	0

 LINE       128
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T3,T4
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T3,T4
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T3,T4

 LINE       128
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       128
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       134
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4
1	1	Covered	T11,T12,T13

 LINE       134
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T12,T13

 LINE       138
 EXPRESSION (token_received && (rx_pid == UsbPidIn))
             -------1------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T11
1	0	Covered	T1,T3,T4
1	1	Covered	T5,T7,T11

 LINE       138
 SUB-EXPRESSION (rx_pid == UsbPidIn)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T11

 LINE       142
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid == UsbPidAck))
             ------1-----    -------2------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T7,T11
1	0	1	Not Covered
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T5,T7,T11

 LINE       142
 SUB-EXPRESSION (rx_pid == UsbPidAck)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T11

 LINE       149
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (in_ep_enabled_i[in_ep_index_d] & ep_in_hw)
             ---------------1--------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T7,T11

 LINE       166
 EXPRESSION (has_data_q & ((~in_ep_data_done_i[in_ep_index])))
             -----1----   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T21
1	1	Covered	T5,T7,T11

 LINE       168
 EXPRESSION ((logic'((in_xact_state == StSendData))) & more_data_to_send)
             -------------------1-------------------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T11
1	0	Covered	T5,T7,T22
1	1	Covered	T5,T7,T11

 LINE       174
 EXPRESSION (((in_xact_state == StIdle) || (in_xact_state == StWaitAck)) && in_token_received)
             -----------------------------1-----------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T11

 LINE       174
 SUB-EXPRESSION ((in_xact_state == StIdle) || (in_xact_state == StWaitAck))
                 ------------1------------    --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T11
0	1	Covered	T5,T7,T11
1	0	Covered	T1,T2,T3

 LINE       174
 SUB-EXPRESSION (in_xact_state == StIdle)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       174
 SUB-EXPRESSION (in_xact_state == StWaitAck)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T11

 LINE       176
 EXPRESSION (in_starting & ep_active)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T11
1	0	Not Covered
1	1	Covered	T5,T7,T11

 LINE       195
 EXPRESSION (ep_active && in_token_received)
             ----1----    --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T11
1	1	Covered	T5,T7,T11

 LINE       227
 EXPRESSION (((!more_data_to_send)) || (((&in_ep_get_addr_o)) && tx_data_get_i))
             -----------1----------    --------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T11
0	1	Covered	T11,T14,T15
1	0	Covered	T5,T7,T22

 LINE       227
 SUB-EXPRESSION (((&in_ep_get_addr_o)) && tx_data_get_i)
                 ----------1----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T11
1	0	Covered	T11,T14,T15
1	1	Covered	T11,T14,T15

 LINE       257
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------

-1-	Status	Tests
0	Covered	T5,T7,T11
1	Not Covered

 LINE       270
 EXPRESSION (ep_active ? StRcvdIn : StIdle)
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       308
 EXPRESSION (link_reset_i || ((!link_active_i)))
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       321
 EXPRESSION (in_xact_state == StIdle)
            ------------1------------

-1-	Status	Tests
0	Covered	T5,T7,T11
1	Covered	T1,T2,T3

 LINE       323
 EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
             --------------1--------------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T11
1	1	Covered	T5,T7,T11

 LINE       323
 SUB-EXPRESSION (in_xact_state == StSendData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T5,T7,T11
1	Covered	T5,T7,T11

 LINE       349
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T11
1	0	Covered	T12,T13,T16
1	1	Covered	T11,T14,T15

 LINE       351
 EXPRESSION ((in_xact_state == StWaitAck) && ack_received)
             --------------1-------------    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T11
1	1	Covered	T5,T7,T11

 LINE       351
 SUB-EXPRESSION (in_xact_state == StWaitAck)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T11

 LINE       377
 EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
             --------------1--------------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T11
1	1	Covered	T5,T7,T11

 LINE       377
 SUB-EXPRESSION (in_xact_state == StSendData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T11

---

FSM Coverage for Module : usb_fs_nb_in_pe

Summary for FSM :: in_xact_state

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	12	7	58.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: in_xact_state

---

states	Line No.	Covered	Tests
StIdle	309	Covered	T1,T2,T3
StRcvdIn	196	Covered	T5,T7,T11
StSendData	211	Covered	T5,T7,T11
StWaitAck	256	Covered	T5,T7,T11
StWaitAckStart	233	Covered	T5,T7,T11
StWaitTxEnd	235	Covered	T5,T7,T11

transitions	Line No.	Covered	Tests
StIdle->StRcvdIn	196	Covered	T5,T7,T11
StRcvdIn->StIdle	309	Covered	T21,T23,T24
StRcvdIn->StSendData	211	Covered	T5,T7,T11
StSendData->StIdle	309	Not Covered
StSendData->StWaitAckStart	233	Not Covered
StSendData->StWaitTxEnd	235	Covered	T5,T7,T11
StWaitAck->StIdle	309	Covered	T5,T7,T11
StWaitAck->StRcvdIn	270	Not Covered
StWaitAckStart->StIdle	309	Not Covered
StWaitAckStart->StWaitAck	256	Covered	T5,T7,T11
StWaitTxEnd->StIdle	309	Not Covered
StWaitTxEnd->StWaitAckStart	245	Covered	T5,T7,T11

---

Branch Coverage for Module : usb_fs_nb_in_pe

	Line No.	Total	Covered	Percent
Branches		48	37	77.08
TERNARY	149	2	1	50.00
CASE	193	21	12	57.14
IF	289	2	2	100.00
IF	297	2	2	100.00
IF	305	3	3	100.00
IF	318	4	4	100.00
IF	330	3	3	100.00
IF	349	3	3	100.00
IF	355	2	1	50.00
IF	364	3	3	100.00
IF	374	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	149	(ep_in_hw) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	193	case (in_xact_state)
-2-:	195	if ((ep_active && in_token_received))
-3-:	206	if (in_ep_iso_i[in_ep_index])
-4-:	213	if (in_ep_stall_i[in_ep_index])
-5-:	216	if (has_data_q)
-6-:	227	if (((!more_data_to_send) || ((&in_ep_get_addr_o) && tx_data_get_i)))
-7-:	228	if (in_ep_iso_i[in_ep_index])
-8-:	232	if (tx_pkt_end_i)
-9-:	244	if (tx_pkt_end_i)
-10-:	255	if (rx_pkt_start_i)
-11-:	257	if ((timeout_cntdown_q == '0))
-12-:	266	if (ack_received)
-13-:	269	if (in_token_received)
-14-:	270	(ep_active) ? 
-15-:	272	if (rx_pkt_end_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T11
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRcvdIn	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StRcvdIn	-	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T23,T24
StRcvdIn	-	0	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T11
StRcvdIn	-	0	0	0	-	-	-	-	-	-	-	-	-	-	Not Covered
StSendData	-	-	-	-	1	1	-	-	-	-	-	-	-	-	Not Covered
StSendData	-	-	-	-	1	0	1	-	-	-	-	-	-	-	Not Covered
StSendData	-	-	-	-	1	0	0	-	-	-	-	-	-	-	Covered	T5,T7,T11
StSendData	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T11
StWaitTxEnd	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T7,T11
StWaitTxEnd	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T5,T7,T11
StWaitAckStart	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T5,T7,T11
StWaitAckStart	-	-	-	-	-	-	-	-	0	1	-	-	-	-	Not Covered
StWaitAckStart	-	-	-	-	-	-	-	-	0	0	-	-	-	-	Covered	T5,T7,T11
StWaitAck	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T5,T7,T11
StWaitAck	-	-	-	-	-	-	-	-	-	-	0	1	1	-	Not Covered
StWaitAck	-	-	-	-	-	-	-	-	-	-	0	1	0	-	Not Covered
StWaitAck	-	-	-	-	-	-	-	-	-	-	0	0	-	1	Not Covered
StWaitAck	-	-	-	-	-	-	-	-	-	-	0	0	-	0	Covered	T5,T7,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	289	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	297	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))
-2-:	308	if ((link_reset_i || (!link_active_i)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	318	if ((!rst_ni))
-2-:	321	if ((in_xact_state == StIdle))
-3-:	323	if (((in_xact_state == StSendData) && tx_data_get_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T5,T7,T11
0	0	0	Covered	T5,T7,T11

	LineNo.	Expression
-1-:	330	if ((!rst_ni))
-2-:	335	if (in_token_received)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T7,T11
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	if ((setup_token_received && ep_active))
-2-:	351	if (((in_xact_state == StWaitAck) && ack_received))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T14,T15
0	1	Covered	T5,T7,T11
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	if (in_datatog_we_i)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	364	if ((!rst_ni))
-2-:	366	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	374	if ((!rst_ni))
-2-:	377	if (((in_xact_state == StSendData) && tx_data_get_i))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T7,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : usb_fs_nb_in_pe

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
InXactStateValid_A	278320685	278216086	0	0

InXactStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278320685	278216086	0	0
T1	403031	402899	0	0
T2	9208	9143	0	0
T3	401844	401675	0	0
T4	402399	402302	0	0
T5	403381	403220	0	0
T6	403326	403260	0	0
T7	402230	402073	0	0
T8	401848	401765	0	0
T9	403231	403046	0	0
T10	401458	401385	0	0