Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	73404	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	60445	1		T1	17		T2	7		T3	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	63714	1		T1	18		T2	5		T3	4
values[0x0]	34613	1		T1	3		T2	4		T3	4
values[0x1]	35522	1		T1	3		T2	2		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55535	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	78314	1		T1	19		T2	7		T3	10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	389	1		T263	1		T264	1		T212	3
valid_sources[0x01]	446	1		T3	1		T265	1		T212	1
valid_sources[0x02]	508	1		T266	1		T212	13		T208	2
valid_sources[0x03]	505	1		T212	7		T208	3		T267	1
valid_sources[0x04]	397	1		T45	8		T212	6		T208	2
valid_sources[0x05]	531	1		T268	1		T121	1		T33	1
valid_sources[0x06]	547	1		T43	8		T269	1		T266	3
valid_sources[0x07]	408	1		T8	1		T11	1		T270	1
valid_sources[0x08]	457	1		T266	1		T15	1		T127	1
valid_sources[0x09]	613	1		T21	1		T271	1		T212	4
valid_sources[0x0a]	455	1		T272	3		T263	1		T212	4
valid_sources[0x0b]	456	1		T121	1		T212	1		T208	2
valid_sources[0x0c]	382	1		T42	1		T205	1		T45	1
valid_sources[0x0d]	332	1		T272	4		T270	1		T75	3
valid_sources[0x0e]	340	1		T266	2		T135	1		T212	2
valid_sources[0x0f]	459	1		T27	1		T40	1		T45	7
valid_sources[0x10]	528	1		T21	1		T11	1		T273	3
valid_sources[0x11]	371	1		T38	1		T45	12		T212	4
valid_sources[0x12]	715	1		T31	1		T45	3		T274	1
valid_sources[0x13]	562	1		T9	1		T28	3		T21	1
valid_sources[0x14]	412	1		T42	4		T40	1		T271	2
valid_sources[0x15]	585	1		T29	2		T212	4		T208	1
valid_sources[0x16]	530	1		T20	1		T269	1		T22	10
valid_sources[0x17]	661	1		T14	39		T127	1		T104	2
valid_sources[0x18]	815	1		T134	1		T212	1		T208	1
valid_sources[0x19]	429	1		T266	1		T218	2		T275	1
valid_sources[0x1a]	545	1		T6	13		T38	1		T29	1
valid_sources[0x1b]	403	1		T276	3		T134	1		T265	1
valid_sources[0x1c]	445	1		T11	1		T39	1		T45	35
valid_sources[0x1d]	385	1		T29	1		T212	6		T208	7
valid_sources[0x1e]	345	1		T20	1		T75	1		T271	1
valid_sources[0x1f]	483	1		T31	1		T45	4		T212	2
valid_sources[0x20]	671	1		T45	29		T134	1		T212	8
valid_sources[0x21]	377	1		T270	1		T45	1		T212	7
valid_sources[0x22]	537	1		T21	1		T31	1		T20	1
valid_sources[0x23]	492	1		T20	1		T23	17		T45	14
valid_sources[0x24]	455	1		T266	1		T271	2		T265	1
valid_sources[0x25]	600	1		T269	1		T75	1		T274	1
valid_sources[0x26]	1299	1		T28	5		T11	1		T45	10
valid_sources[0x27]	412	1		T4	1		T212	7		T208	4
valid_sources[0x28]	454	1		T3	6		T269	1		T45	16
valid_sources[0x29]	679	1		T3	2		T38	1		T266	1
valid_sources[0x2a]	447	1		T11	1		T117	1		T277	1
valid_sources[0x2b]	532	1		T21	1		T269	1		T266	1
valid_sources[0x2c]	416	1		T20	1		T271	1		T278	2
valid_sources[0x2d]	439	1		T11	1		T45	3		T263	1
valid_sources[0x2e]	386	1		T75	1		T265	1		T212	3
valid_sources[0x2f]	505	1		T30	2		T39	1		T45	10
valid_sources[0x30]	558	1		T269	1		T75	1		T127	1
valid_sources[0x31]	1161	1		T266	1		T44	765		T117	1
valid_sources[0x32]	384	1		T212	4		T208	1		T267	1
valid_sources[0x33]	506	1		T279	1		T212	5		T208	4
valid_sources[0x34]	407	1		T11	1		T27	1		T45	6
valid_sources[0x35]	668	1		T20	1		T29	2		T212	4
valid_sources[0x36]	480	1		T20	1		T40	1		T16	1
valid_sources[0x37]	420	1		T266	2		T45	6		T29	1
valid_sources[0x38]	418	1		T266	1		T271	1		T212	4
valid_sources[0x39]	494	1		T45	7		T263	1		T265	1
valid_sources[0x3a]	412	1		T266	1		T40	1		T280	1
valid_sources[0x3b]	435	1		T8	1		T45	11		T208	3
valid_sources[0x3c]	441	1		T28	1		T11	2		T222	1
valid_sources[0x3d]	416	1		T8	1		T45	12		T271	1
valid_sources[0x3e]	356	1		T27	2		T45	5		T117	1
valid_sources[0x3f]	330	1		T28	1		T21	2		T20	1
valid_sources[0x40]	410	1		T281	13		T45	1		T121	1
valid_sources[0x41]	417	1		T218	1		T210	1		T212	5
valid_sources[0x42]	717	1		T27	1		T275	1		T271	1
valid_sources[0x43]	427	1		T21	1		T27	1		T266	1
valid_sources[0x44]	514	1		T20	1		T45	1		T212	5
valid_sources[0x45]	484	1		T266	1		T45	12		T271	1
valid_sources[0x46]	434	1		T7	1		T20	1		T154	1
valid_sources[0x47]	504	1		T45	6		T212	6		T208	2
valid_sources[0x48]	417	1		T212	1		T282	1		T283	1
valid_sources[0x49]	485	1		T207	1		T210	1		T277	1
valid_sources[0x4a]	436	1		T212	11		T208	3		T284	3
valid_sources[0x4b]	426	1		T30	1		T270	2		T45	9
valid_sources[0x4c]	611	1		T174	1		T117	2		T134	1
valid_sources[0x4d]	409	1		T279	2		T212	3		T208	5
valid_sources[0x4e]	392	1		T278	1		T263	1		T212	6
valid_sources[0x4f]	495	1		T19	3		T212	2		T208	4
valid_sources[0x50]	939	1		T28	2		T276	2		T46	541
valid_sources[0x51]	467	1		T271	2		T76	5		T285	2
valid_sources[0x52]	474	1		T29	3		T154	1		T263	1
valid_sources[0x53]	377	1		T11	1		T27	1		T174	2
valid_sources[0x54]	456	1		T269	1		T45	27		T29	1
valid_sources[0x55]	532	1		T42	6		T45	7		T29	1
valid_sources[0x56]	1328	1		T38	1		T205	1		T36	1
valid_sources[0x57]	1251	1		T4	1		T38	1		T45	3
valid_sources[0x58]	468	1		T117	1		T75	2		T279	6
valid_sources[0x59]	520	1		T28	1		T20	1		T38	1
valid_sources[0x5a]	1050	1		T212	5		T208	1		T282	5
valid_sources[0x5b]	400	1		T7	1		T29	1		T117	1
valid_sources[0x5c]	511	1		T274	1		T212	9		T208	3
valid_sources[0x5d]	394	1		T11	1		T29	2		T212	4
valid_sources[0x5e]	449	1		T45	16		T212	5		T208	2
valid_sources[0x5f]	465	1		T117	1		T286	6		T135	1
valid_sources[0x60]	386	1		T287	1		T212	6		T208	2
valid_sources[0x61]	1031	1		T9	1		T11	1		T265	1
valid_sources[0x62]	400	1		T4	3		T11	1		T263	1
valid_sources[0x63]	610	1		T45	9		T29	1		T117	1
valid_sources[0x64]	465	1		T11	1		T30	1		T272	3
valid_sources[0x65]	734	1		T273	2		T276	1		T33	1
valid_sources[0x66]	499	1		T8	1		T45	2		T212	1
valid_sources[0x67]	532	1		T212	4		T208	3		T34	8
valid_sources[0x68]	381	1		T121	1		T212	1		T115	1
valid_sources[0x69]	759	1		T20	1		T42	6		T45	1
valid_sources[0x6a]	431	1		T205	1		T271	1		T274	1
valid_sources[0x6b]	368	1		T9	2		T208	5		T180	1
valid_sources[0x6c]	514	1		T278	2		T135	1		T288	8
valid_sources[0x6d]	474	1		T45	5		T121	1		T289	11
valid_sources[0x6e]	407	1		T24	17		T212	3		T208	3
valid_sources[0x6f]	463	1		T45	7		T263	1		T290	1
valid_sources[0x70]	368	1		T45	5		T29	2		T16	1
valid_sources[0x71]	403	1		T30	1		T20	1		T43	1
valid_sources[0x72]	427	1		T1	1		T20	1		T26	7
valid_sources[0x73]	1670	1		T1	3		T20	1		T15	1
valid_sources[0x74]	574	1		T28	2		T38	1		T273	2
valid_sources[0x75]	357	1		T270	1		T29	1		T275	1
valid_sources[0x76]	457	1		T8	1		T9	1		T28	6
valid_sources[0x77]	358	1		T10	11		T45	5		T127	1
valid_sources[0x78]	400	1		T31	1		T218	3		T40	1
valid_sources[0x79]	367	1		T212	7		T208	3		T291	1
valid_sources[0x7a]	511	1		T20	1		T117	2		T210	1
valid_sources[0x7b]	404	1		T269	1		T212	9		T292	2
valid_sources[0x7c]	325	1		T271	1		T265	1		T212	4
valid_sources[0x7d]	388	1		T274	1		T212	3		T208	4
valid_sources[0x7e]	674	1		T45	1		T174	1		T121	1
valid_sources[0x7f]	403	1		T29	2		T127	1		T278	2
valid_sources[0x80]	432	1		T212	8		T208	4		T267	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23937

1

T1

14

T2

4

T3

2

values[0x0]

all_enables

biggest_size

20791

1

T1

1

T2

3

T3

4

values[0x1]

all_enables

biggest_size

15717

1

T1

2

T6

1

T7

1