Module Definition
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Module : usbdev_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_csr_assert 100.00 100.00



Module Instance : tb.dut.usbdev_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
89.25 96.75 68.07 93.93 87.50 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : usbdev_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 10 10 100.00 10 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 10 10 100.00 10 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 278315424 13633 0 0
ep_in_enable_rd_A 278315424 3447 0 0
ep_out_enable_rd_A 278315424 3462 0 0
in_iso_rd_A 278315424 3734 0 0
intr_enable_rd_A 278315424 5855 0 0
out_iso_rd_A 278315424 3815 0 0
phy_config_rd_A 278315424 2378 0 0
phy_pins_drive_rd_A 278315424 3188 0 0
rxenable_setup_rd_A 278315424 3555 0 0
set_nak_out_rd_A 278315424 3479 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 278315424 13633 0 0
T47 11805 3 0 0
T48 3496 527 0 0
T49 5994 2 0 0
T81 11789 4 0 0
T184 2233 255 0 0
T185 8743 738 0 0
T186 22592 3 0 0
T187 5228 429 0 0
T188 5977 26 0 0
T191 10212 2 0 0

ep_in_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 278315424 3447 0 0
T47 11805 317 0 0
T54 6991 26 0 0
T79 2663 42 0 0
T80 3696 16 0 0
T81 11789 100 0 0
T82 2729 70 0 0
T186 22592 476 0 0
T190 4097 10 0 0
T191 10212 109 0 0
T242 1811 1 0 0

ep_out_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 278315424 3462 0 0
T47 11805 324 0 0
T54 6991 40 0 0
T79 2663 43 0 0
T80 3696 3 0 0
T81 11789 149 0 0
T82 2729 113 0 0
T186 22592 369 0 0
T190 4097 4 0 0
T191 10212 124 0 0
T242 1811 3 0 0

in_iso_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 278315424 3734 0 0
T47 11805 273 0 0
T54 6991 29 0 0
T79 2663 51 0 0
T80 3696 8 0 0
T81 11789 114 0 0
T82 2729 48 0 0
T186 22592 598 0 0
T190 4097 51 0 0
T191 10212 169 0 0
T192 21749 282 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 278315424 5855 0 0
T47 11805 358 0 0
T54 6991 24 0 0
T62 1243 11 0 0
T79 2663 2 0 0
T80 3696 19 0 0
T81 11789 238 0 0
T82 2729 73 0 0
T186 22592 702 0 0
T191 10212 160 0 0
T243 1354 7 0 0

out_iso_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 278315424 3815 0 0
T47 11805 237 0 0
T53 1799 1 0 0
T54 6991 13 0 0
T79 2663 23 0 0
T80 3696 44 0 0
T81 11789 176 0 0
T82 2729 41 0 0
T186 22592 475 0 0
T191 10212 96 0 0
T242 1811 8 0 0

phy_config_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 278315424 2378 0 0
T47 11805 108 0 0
T54 6991 50 0 0
T79 2663 22 0 0
T80 3696 14 0 0
T81 11789 72 0 0
T82 2729 33 0 0
T186 22592 333 0 0
T191 10212 92 0 0
T192 21749 221 0 0
T244 6411 53 0 0

phy_pins_drive_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 278315424 3188 0 0
T47 11805 277 0 0
T53 1799 6 0 0
T54 6991 31 0 0
T79 2663 40 0 0
T80 3696 33 0 0
T81 11789 115 0 0
T82 2729 43 0 0
T186 22592 389 0 0
T191 10212 71 0 0
T242 1811 3 0 0

rxenable_setup_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 278315424 3555 0 0
T47 11805 277 0 0
T53 1799 4 0 0
T54 6991 35 0 0
T79 2663 2 0 0
T80 3696 12 0 0
T81 11789 183 0 0
T82 2729 7 0 0
T186 22592 354 0 0
T191 10212 116 0 0
T242 1811 4 0 0

set_nak_out_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 278315424 3479 0 0
T47 11805 149 0 0
T54 6991 60 0 0
T79 2663 53 0 0
T80 3696 18 0 0
T81 11789 94 0 0
T82 2729 64 0 0
T186 22592 419 0 0
T190 4097 6 0 0
T191 10212 102 0 0
T242 1811 4 0 0

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