Unified Coverage Report :: Module :: usb_fs_rx

Module : usb_fs_rx

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.25	98.92	87.56			93.26

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_rx	93.25	98.92	87.56			93.26

---

Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_rx

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.25	98.92	87.56			93.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.25	98.92	87.56			93.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	50.00				100.00	u_usb_fs_nb_pe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usb_fs_rx

	Line No.	Total	Covered	Percent
TOTAL		185	183	98.92
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	122	5	5	100.00
ALWAYS	132	11	11	100.00
ALWAYS	151	5	5	100.00
ALWAYS	169	5	5	100.00
CONT_ASSIGN	221	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
ALWAYS	249	5	5	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
ALWAYS	291	3	3	100.00
ALWAYS	299	9	8	88.89
CONT_ASSIGN	322	1	1	100.00
ALWAYS	326	8	8	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
ALWAYS	347	3	3	100.00
CONT_ASSIGN	355	1	1	100.00
ALWAYS	370	12	12	100.00
ALWAYS	396	5	5	100.00
ALWAYS	406	5	5	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
ALWAYS	428	5	4	80.00
ALWAYS	437	3	3	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
ALWAYS	460	5	5	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
ALWAYS	478	5	5	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
ALWAYS	500	5	5	100.00
CONT_ASSIGN	516	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
ALWAYS	547	5	5	100.00
ALWAYS	560	7	7	100.00
CONT_ASSIGN	571	1	1	100.00
CONT_ASSIGN	572	1	1	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
CONT_ASSIGN	589	1	1	100.00
ALWAYS	592	5	5	100.00
ALWAYS	608	26	26	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
122	1	1
123	1	1
124	1	1
126	1	1
127	1	1
132	1	1
133	1	1
134	1	1
135	1	1
137	1	1
138	1	1
139	1	1
140	1	1
142	1	1
143	1	1
144	1	1
151	1	1
153	1	1
156	1	1
161	1	1
162	1	1
			MISSING_ELSE
169	1	1
171	1	1
174	1	1
179	1	1
180	1	1
			MISSING_ELSE
221	1	1
222	1	1
242	1	1
243	1	1
246	1	1
249	1	1
250	1	1
252	1	1
253	1	1
255	1	1
276	1	1
277	1	1
282	1	1
286	1	1
287	1	1
291	1	1
292	1	1
294	1	1
299	1	1
302	1	1
303	0	1
305	1	1
306	1	1
310	1	1
311	1	1
314	1	1
317	1	1
322	1	1
326	1	1
327	1	1
328	1	1
330	1	1
331	1	1
332	1	1
334	1	1
335	1	1
343	1	1
344	1	1
347	1	1
348	1	1
350	1	1
355	1	1
370	1	1
371	1	1
372	1	1
373	1	1
374	1	1
378	1	1
379	1	1
380	1	1
381	1	1
382	1	1
383	1	1
387	1	1
396	1	1
397	1	1
398	1	1
399	1	1
401	1	1
406	1	1
407	1	1
409	1	1
410	1	1
412	1	1
418	1	1
424	1	1
428	1	1
429	1	1
430	1	1
431	1	1
432	0	1
			MISSING_ELSE
437	1	1
438	1	1
440	1	1
444	1	1
456	1	1
457	1	1
460	1	1
461	1	1
462	1	1
463	1	1
465	1	1
474	1	1
475	1	1
478	1	1
480	1	1
481	1	1
			MISSING_ELSE
484	1	1
485	1	1
			MISSING_ELSE
496	1	1
497	1	1
500	1	1
502	1	1
503	1	1
			MISSING_ELSE
506	1	1
507	1	1
			MISSING_ELSE
516	1	1
517	1	1
518	1	1
520	1	1
524	1	1
531	1	1
535	1	1
540	1	1
547	1	1
549	1	1
550	1	1
			MISSING_ELSE
553	1	1
554	1	1
			MISSING_ELSE
560	1	1
561	1	1
562	1	1
564	1	1
565	1	1
566	1	1
567	1	1
			MISSING_ELSE
571	1	1
572	1	1
573	1	1
574	1	1
576	1	1
577	1	1
587	1	1
588	1	1
589	1	1
592	1	1
594	1	1
595	1	1
			MISSING_ELSE
598	1	1
599	1	1
			MISSING_ELSE
608	1	1
609	1	1
610	1	1
611	1	1
612	1	1
613	1	1
614	1	1
615	1	1
616	1	1
618	1	1
619	1	1
620	1	1
621	1	1
622	1	1
623	1	1
624	1	1
625	1	1
626	1	1
628	1	1
629	1	1
630	1	1
631	1	1
632	1	1
633	1	1
634	1	1
635	1	1

---

Cond Coverage for Module : usb_fs_rx

	Total	Covered	Percent
Conditions	193	169	87.56
Logical	193	169	87.56
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (cfg_pinflip_i ? usb_dn_i : usb_dp_i)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       71
 EXPRESSION (cfg_pinflip_i ? usb_dp_i : usb_dn_i)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       72
 EXPRESSION (usb_d_i ^ cfg_pinflip_i)
             ---1---   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       127
 EXPRESSION (usb_d_flipped ? DJ[1:0] : DK[1:0])
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       153
 EXPRESSION (line_state_q == DT)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (dpair != line_state_q[1:0])
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION (diff_state_q == DT)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       179
 EXPRESSION (ddiff != diff_state_q[1:0])
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       221
 EXPRESSION ((line_state_q == SE0) || ((line_state_q == DT) && (line_state_qq == SE0)))
             ----------1----------    ------------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       221
 SUB-EXPRESSION (line_state_q == SE0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       221
 SUB-EXPRESSION ((line_state_q == DT) && (line_state_qq == SE0))
                 ----------1---------    -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       221
 SUB-EXPRESSION (line_state_q == DT)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       221
 SUB-EXPRESSION (line_state_qq == SE0)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       222
 EXPRESSION (cfg_use_diff_rcvr_i ? (use_se ? line_state_q : diff_state_q) : line_state_q)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       222
 SUB-EXPRESSION (use_se ? line_state_q : diff_state_q)
                 ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       242
 EXPRESSION (bit_phase_q == 2'b1)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       243
 EXPRESSION (bit_phase_q == 2'd2)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       246
 EXPRESSION ((line_state_rx == DT) ? 0 : ((bit_phase_q + 1)))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       246
 SUB-EXPRESSION (line_state_rx == DT)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       276
 EXPRESSION (packet_valid_d & ((~packet_valid_q)))
             -------1------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       277
 EXPRESSION (((~packet_valid_d)) & packet_valid_q)
             ---------1---------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       282
 EXPRESSION ((cfg_eop_single_bit_i && (line_history_q[1:0] == 2'b0)) || (line_history_q[3:0] == 4'b0) || bitstuff_error_q || see_preamble)
             ---------------------------1---------------------------    --------------2--------------    --------3-------    ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T2,T3

 LINE       282
 SUB-EXPRESSION (cfg_eop_single_bit_i && (line_history_q[1:0] == 2'b0))
                 ----------1---------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       282
 SUB-EXPRESSION (line_history_q[1:0] == 2'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       282
 SUB-EXPRESSION (line_history_q[3:0] == 4'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       286
 EXPRESSION ((line_history_q[3:0] == 4'b1001) & ((~tx_en_i)) & ((~in_packet_q)))
             ----------------1---------------   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

 LINE       286
 SUB-EXPRESSION (line_history_q[3:0] == 4'b1001)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       287
 EXPRESSION (see_eop ? 1'b0 : (see_sop ? 1'b1 : in_packet_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       287
 SUB-EXPRESSION (see_sop ? 1'b1 : in_packet_q)
                 ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       305
 EXPRESSION (((!packet_valid_q)) && (line_history_q[11:0] == 12'b011001100101))
             ---------1---------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       305
 SUB-EXPRESSION (line_history_q[11:0] == 12'b011001100101)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       310
 EXPRESSION (packet_valid_q && see_eop)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       322
 EXPRESSION (line_state_valid ? ({line_history_q[9:0], line_state_rx[1:0]}) : line_history_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       343
 EXPRESSION ((((~tx_en_i)) & line_state_valid) ? (line_state_q == DJ) : rx_idle_det_q)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       343
 SUB-EXPRESSION (((~tx_en_i)) & line_state_valid)
                 ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       343
 SUB-EXPRESSION (line_state_q == DJ)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       355
 EXPRESSION (diff_rx_ok_i & ((~tx_en_i)) & (line_history_q[1:0] == 2'b10))
             ------1-----   ------2-----   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       355
 SUB-EXPRESSION (line_history_q[1:0] == 2'b10)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       378
 EXPRESSION (packet_valid_q && line_state_valid)
             -------1------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       418
 EXPRESSION (dvalid_raw && ( ! (bitstuff_history_q[5:0] == 6'b111111) ))
             -----1----    ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T4

 LINE       418
 SUB-EXPRESSION ( ! (bitstuff_history_q[5:0] == 6'b111111) )
                    -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       418
 SUB-EXPRESSION (bitstuff_history_q[5:0] == 6'b111111)
                -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       424
 EXPRESSION (bitstuff_history_q == 7'b1111111)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       431
 EXPRESSION (bitstuff_error && dvalid_raw)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Not Covered

 LINE       444
 EXPRESSION (bitstuff_error_q && packet_end)
             --------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Not Covered

 LINE       456
 EXPRESSION (full_pid_q[4:1] == (~full_pid_q[8:5]))
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       460
 EXPRESSION (dvalid && ((!pid_complete)))
             ---1--    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       474
 EXPRESSION (crc5_q == 5'b01100)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       475
 EXPRESSION (din ^ crc5_q[4])
             -1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       484
 EXPRESSION (dvalid && pid_complete)
             ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       496
 EXPRESSION (crc16_q == 16'b1000000000001101)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       497
 EXPRESSION (din ^ crc16_q[15])
             -1-   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       506
 EXPRESSION (dvalid && pid_complete)
             ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       516
 EXPRESSION (full_pid_q[2:1] == 2'b1)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       517
 EXPRESSION (full_pid_q[2:1] == 2'b11)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       518
 EXPRESSION (full_pid_q[2:1] == 2'b10)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       520
 EXPRESSION ((packet_valid_q & pid_valid & pid_complete) && (usb_pid_e'(full_pid_q[4:1]) == UsbPidPre))
             ---------------------1---------------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Not Covered

 LINE       520
 SUB-EXPRESSION (packet_valid_q & pid_valid & pid_complete)
                 -------1------   ----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

 LINE       520
 SUB-EXPRESSION (usb_pid_e'(full_pid_q[4:1]) == UsbPidPre)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       524
 EXPRESSION (pid_valid && ((!bitstuff_error_q)) && (pkt_is_handshake || (pkt_is_data && crc16_valid) || (pkt_is_token && crc5_valid)))
             ----1----    ----------2----------    -----------------------------------------3----------------------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

 LINE       524
 SUB-EXPRESSION (pkt_is_handshake || (pkt_is_data && crc16_valid) || (pkt_is_token && crc5_valid))
                 --------1-------    --------------2-------------    --------------3-------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	1	0	Covered	T1,T2,T4
1	0	0	Covered	T1,T2,T4

 LINE       524
 SUB-EXPRESSION (pkt_is_data && crc16_valid)
                 -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       524
 SUB-EXPRESSION (pkt_is_token && crc5_valid)
                 ------1-----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       531
 EXPRESSION (((pkt_is_data && ((!crc16_valid))) || (pkt_is_token && ((!crc5_valid)))) && packet_end)
             ------------------------------------1-----------------------------------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Not Covered

 LINE       531
 SUB-EXPRESSION ((pkt_is_data && ((!crc16_valid))) || (pkt_is_token && ((!crc5_valid))))
                 ----------------1----------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       531
 SUB-EXPRESSION (pkt_is_data && ((!crc16_valid)))
                 -----1-----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       531
 SUB-EXPRESSION (pkt_is_token && ((!crc5_valid)))
                 ------1-----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       535
 EXPRESSION (((!pid_valid)) && packet_end)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       553
 EXPRESSION (dvalid && pid_complete && pkt_is_token && ((!token_payload_done)))
             ---1--    ------2-----    ------3-----    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T4
1	0	1	1	Covered	T11,T12,T13
1	1	0	1	Covered	T1,T2,T4
1	1	1	0	Covered	T1,T2,T4
1	1	1	1	Covered	T1,T2,T4

 LINE       564
 EXPRESSION (token_payload_done && pkt_is_token)
             ---------1--------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       594
 EXPRESSION (packet_start || rx_data_buffer_full)
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       598
 EXPRESSION (dvalid && pid_complete && pkt_is_data)
             ---1--    ------2-----    -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

---

Branch Coverage for Module : usb_fs_rx

	Line No.	Total	Covered	Percent
Branches		89	83	93.26
TERNARY	70	2	1	50.00
TERNARY	71	2	1	50.00
TERNARY	222	3	1	33.33
TERNARY	246	2	2	100.00
TERNARY	287	3	3	100.00
TERNARY	322	2	2	100.00
TERNARY	343	2	2	100.00
IF	122	3	3	100.00
IF	132	3	3	100.00
IF	153	3	3	100.00
IF	171	3	3	100.00
IF	249	3	3	100.00
IF	291	2	2	100.00
IF	299	5	4	80.00
IF	326	3	3	100.00
IF	347	2	2	100.00
CASE	370	5	5	100.00
IF	378	6	6	100.00
IF	396	3	3	100.00
IF	406	3	3	100.00
IF	429	3	2	66.67
IF	437	2	2	100.00
IF	460	3	3	100.00
IF	480	2	2	100.00
IF	484	2	2	100.00
IF	502	2	2	100.00
IF	506	2	2	100.00
IF	549	2	2	100.00
IF	553	2	2	100.00
IF	564	2	2	100.00
IF	594	2	2	100.00
IF	598	2	2	100.00
IF	608	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	70	(cfg_pinflip_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	71	(cfg_pinflip_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	(cfg_use_diff_rcvr_i) ? 
-2-:	222	(use_se) ? 

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	246	((line_state_rx == DT)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	287	(see_eop) ? 
-2-:	287	(see_sop) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	322	(line_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	343	(((~tx_en_i) & line_state_valid)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	122	if (tx_en_i)
-2-:	127	(usb_d_flipped) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	132	if ((!rst_ni))
-2-:	137	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((line_state_q == DT))
-2-:	161	if ((dpair != line_state_q[1:0]))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	if ((diff_state_q == DT))
-2-:	179	if ((ddiff != diff_state_q[1:0]))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	249	if ((!rst_ni))
-2-:	252	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	291	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if (line_state_valid)
-2-:	302	if ((~diff_rx_ok_i))
-3-:	305	if (((!packet_valid_q) && (line_history_q[11:0] == 12'b011001100101)))
-4-:	310	if ((packet_valid_q && see_eop))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Not Covered
1	0	1	-	Covered	T1,T2,T4
1	0	0	1	Covered	T1,T2,T4
1	0	0	0	Covered	T1,T2,T3
0	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	326	if ((!rst_ni))
-2-:	330	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	347	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	370	case (line_history_q[3:0])

Branches:

-1-	Status	Tests
4'b0101	Covered	T1,T2,T4
4'b0110	Covered	T1,T2,T4
4'b1001	Covered	T1,T2,T4
4'b1010	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	378	if ((packet_valid_q && line_state_valid))
-2-:	379	case (line_history_q[3:0])

Branches:

-1-	-2-	Status	Tests
1	4'b0101	Covered	T1,T2,T4
1	4'b0110	Covered	T1,T2,T4
1	4'b1001	Covered	T1,T2,T4
1	4'b1010	Covered	T1,T2,T4
1	default	Covered	T1,T2,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	if (packet_end)
-2-:	398	if (dvalid_raw)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	406	if ((!rst_ni))
-2-:	409	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	429	if (packet_start)
-2-:	431	if ((bitstuff_error && dvalid_raw))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	460	if ((dvalid && (!pid_complete)))
-2-:	462	if (packet_start)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	480	if (packet_start)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	if ((dvalid && pid_complete))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	502	if (packet_start)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	506	if ((dvalid && pid_complete))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	549	if (packet_start)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	if ((((dvalid && pid_complete) && pkt_is_token) && (!token_payload_done)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	564	if ((token_payload_done && pkt_is_token))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	594	if ((packet_start || rx_data_buffer_full))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	598	if (((dvalid && pid_complete) && pkt_is_data))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	608	if ((!rst_ni))
-2-:	618	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3