Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	88579	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	75428	1		T1	8		T2	6		T3	9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82225	1		T1	7		T2	2		T3	7
values[0x0]	40343	1		T1	3		T2	4		T3	5
values[0x1]	41439	1		T1	3		T2	1		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66530	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	97477	1		T1	10		T2	6		T3	10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	648	1		T6	1		T76	5		T84	6
valid_sources[0x01]	551	1		T272	1		T6	1		T76	2
valid_sources[0x02]	545	1		T76	3		T34	1		T108	1
valid_sources[0x03]	538	1		T76	3		T120	2		T78	2
valid_sources[0x04]	595	1		T32	1		T76	6		T273	2
valid_sources[0x05]	564	1		T76	9		T34	2		T46	1
valid_sources[0x06]	473	1		T11	1		T33	1		T76	2
valid_sources[0x07]	622	1		T76	1		T78	1		T7	2
valid_sources[0x08]	566	1		T32	1		T15	1		T76	4
valid_sources[0x09]	509	1		T33	1		T76	2		T108	1
valid_sources[0x0a]	576	1		T76	4		T274	1		T78	1
valid_sources[0x0b]	561	1		T76	6		T275	2		T178	1
valid_sources[0x0c]	519	1		T28	1		T15	1		T76	5
valid_sources[0x0d]	558	1		T6	1		T76	6		T78	1
valid_sources[0x0e]	572	1		T1	1		T76	6		T276	1
valid_sources[0x0f]	527	1		T6	2		T76	7		T16	1
valid_sources[0x10]	495	1		T76	6		T78	1		T277	1
valid_sources[0x11]	1497	1		T23	3		T51	994		T76	1
valid_sources[0x12]	582	1		T272	1		T76	1		T42	5
valid_sources[0x13]	449	1		T24	1		T76	2		T78	2
valid_sources[0x14]	589	1		T76	3		T83	16		T132	1
valid_sources[0x15]	727	1		T9	1		T76	6		T17	39
valid_sources[0x16]	544	1		T6	2		T76	3		T278	13
valid_sources[0x17]	1243	1		T14	13		T279	1		T76	5
valid_sources[0x18]	549	1		T76	4		T46	1		T134	1
valid_sources[0x19]	633	1		T8	1		T22	6		T38	4
valid_sources[0x1a]	667	1		T76	4		T280	1		T21	1
valid_sources[0x1b]	610	1		T76	1		T45	9		T78	1
valid_sources[0x1c]	586	1		T22	2		T272	1		T76	4
valid_sources[0x1d]	543	1		T279	2		T76	1		T78	7
valid_sources[0x1e]	524	1		T9	2		T31	1		T76	6
valid_sources[0x1f]	532	1		T22	1		T24	1		T76	3
valid_sources[0x20]	624	1		T76	5		T281	11		T78	2
valid_sources[0x21]	3667	1		T1	1		T76	3		T40	1
valid_sources[0x22]	469	1		T13	1		T6	1		T76	2
valid_sources[0x23]	630	1		T76	10		T78	2		T214	1
valid_sources[0x24]	632	1		T76	3		T108	2		T21	1
valid_sources[0x25]	1650	1		T76	7		T78	3		T108	1
valid_sources[0x26]	531	1		T24	1		T76	6		T78	1
valid_sources[0x27]	583	1		T76	1		T78	1		T282	1
valid_sources[0x28]	714	1		T76	2		T276	1		T283	1
valid_sources[0x29]	490	1		T76	5		T16	1		T78	1
valid_sources[0x2a]	639	1		T3	2		T48	1		T6	1
valid_sources[0x2b]	472	1		T32	1		T76	5		T276	1
valid_sources[0x2c]	496	1		T76	4		T280	1		T284	1
valid_sources[0x2d]	502	1		T1	1		T76	4		T16	1
valid_sources[0x2e]	593	1		T76	4		T16	1		T78	2
valid_sources[0x2f]	560	1		T76	4		T78	2		T285	1
valid_sources[0x30]	478	1		T15	2		T76	5		T44	3
valid_sources[0x31]	465	1		T15	1		T76	3		T78	2
valid_sources[0x32]	610	1		T23	8		T76	2		T16	5
valid_sources[0x33]	604	1		T11	1		T48	1		T76	5
valid_sources[0x34]	511	1		T76	4		T5	2		T132	1
valid_sources[0x35]	682	1		T15	1		T76	5		T46	1
valid_sources[0x36]	588	1		T36	2		T76	5		T84	3
valid_sources[0x37]	549	1		T76	4		T44	36		T46	1
valid_sources[0x38]	736	1		T6	1		T76	4		T46	1
valid_sources[0x39]	492	1		T31	1		T76	3		T120	1
valid_sources[0x3a]	575	1		T15	1		T76	4		T78	3
valid_sources[0x3b]	438	1		T1	1		T76	5		T283	1
valid_sources[0x3c]	628	1		T4	1		T28	1		T48	1
valid_sources[0x3d]	1825	1		T24	1		T33	1		T50	1196
valid_sources[0x3e]	529	1		T272	2		T76	6		T275	1
valid_sources[0x3f]	531	1		T76	3		T46	1		T78	3
valid_sources[0x40]	769	1		T76	6		T280	1		T132	2
valid_sources[0x41]	1634	1		T76	1		T46	1		T78	4
valid_sources[0x42]	494	1		T76	6		T286	2		T78	1
valid_sources[0x43]	475	1		T76	7		T274	1		T78	2
valid_sources[0x44]	865	1		T8	1		T24	1		T76	3
valid_sources[0x45]	496	1		T76	3		T78	4		T285	1
valid_sources[0x46]	512	1		T76	4		T16	1		T276	1
valid_sources[0x47]	542	1		T15	1		T76	5		T39	11
valid_sources[0x48]	524	1		T28	1		T24	1		T31	1
valid_sources[0x49]	532	1		T38	9		T76	5		T34	1
valid_sources[0x4a]	552	1		T76	2		T78	1		T7	2
valid_sources[0x4b]	490	1		T272	1		T76	4		T280	2
valid_sources[0x4c]	724	1		T24	1		T76	6		T276	2
valid_sources[0x4d]	524	1		T76	7		T78	2		T284	1
valid_sources[0x4e]	493	1		T76	5		T5	1		T274	1
valid_sources[0x4f]	712	1		T5	1		T117	2		T78	2
valid_sources[0x50]	495	1		T24	1		T76	4		T120	1
valid_sources[0x51]	623	1		T22	1		T15	3		T76	2
valid_sources[0x52]	533	1		T32	1		T76	3		T78	3
valid_sources[0x53]	708	1		T76	4		T78	2		T173	1
valid_sources[0x54]	498	1		T76	1		T78	2		T285	2
valid_sources[0x55]	495	1		T76	1		T78	2		T287	1
valid_sources[0x56]	600	1		T279	1		T76	4		T78	3
valid_sources[0x57]	546	1		T279	1		T76	7		T16	3
valid_sources[0x58]	498	1		T28	1		T272	1		T76	7
valid_sources[0x59]	533	1		T37	16		T76	4		T120	3
valid_sources[0x5a]	551	1		T76	8		T288	1		T46	1
valid_sources[0x5b]	591	1		T76	3		T275	5		T78	1
valid_sources[0x5c]	584	1		T76	3		T285	6		T289	1
valid_sources[0x5d]	504	1		T76	2		T280	1		T290	1
valid_sources[0x5e]	642	1		T8	1		T279	1		T76	5
valid_sources[0x5f]	545	1		T23	1		T15	1		T76	5
valid_sources[0x60]	636	1		T2	7		T32	1		T76	4
valid_sources[0x61]	571	1		T3	2		T78	1		T285	5
valid_sources[0x62]	633	1		T8	1		T4	1		T76	5
valid_sources[0x63]	519	1		T76	2		T16	1		T283	1
valid_sources[0x64]	531	1		T24	1		T76	4		T16	1
valid_sources[0x65]	555	1		T4	1		T24	1		T6	1
valid_sources[0x66]	1737	1		T11	1		T9	2		T48	1
valid_sources[0x67]	559	1		T76	1		T120	1		T78	1
valid_sources[0x68]	536	1		T6	1		T32	1		T76	2
valid_sources[0x69]	1347	1		T15	1		T76	7		T16	1
valid_sources[0x6a]	601	1		T48	1		T76	6		T275	1
valid_sources[0x6b]	509	1		T76	4		T291	1		T78	5
valid_sources[0x6c]	469	1		T76	10		T276	1		T280	1
valid_sources[0x6d]	1071	1		T76	3		T78	4		T285	1
valid_sources[0x6e]	559	1		T76	5		T292	1		T113	1
valid_sources[0x6f]	550	1		T47	24		T76	3		T286	1
valid_sources[0x70]	1665	1		T76	10		T290	1		T78	2
valid_sources[0x71]	537	1		T1	2		T15	1		T76	1
valid_sources[0x72]	607	1		T48	1		T76	5		T286	2
valid_sources[0x73]	514	1		T76	5		T290	1		T78	1
valid_sources[0x74]	449	1		T76	3		T20	2		T293	1
valid_sources[0x75]	528	1		T76	7		T16	3		T78	3
valid_sources[0x76]	529	1		T48	1		T76	2		T26	1
valid_sources[0x77]	641	1		T76	6		T288	1		T294	1
valid_sources[0x78]	1419	1		T24	1		T76	3		T280	1
valid_sources[0x79]	626	1		T9	1		T76	4		T78	5
valid_sources[0x7a]	687	1		T4	1		T76	10		T40	2
valid_sources[0x7b]	498	1		T76	6		T280	2		T286	1
valid_sources[0x7c]	493	1		T3	1		T76	5		T78	2
valid_sources[0x7d]	484	1		T48	1		T76	3		T78	1
valid_sources[0x7e]	509	1		T76	7		T291	1		T78	1
valid_sources[0x7f]	533	1		T15	1		T76	6		T16	1
valid_sources[0x80]	472	1		T8	2		T24	1		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30773

1

T1

4

T2

2

T3

3

values[0x0]

all_enables

biggest_size

25123

1

T1

3

T2

3

T3

5

values[0x1]

all_enables

biggest_size

19532

1

T1

1

T2

1

T3

1