Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	104855	1		T1	5		T2	1		T3	4
full_word	76560	1		T1	8		T2	6		T3	9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	181145	1		T1	13		T2	7		T3	13
auto[TlIntgErrCmd]	80	1		T54	3		T61	3		T194	8
auto[TlIntgErrData]	83	1		T54	2		T61	3		T194	6
auto[TlIntgErrBoth]	107	1		T54	5		T61	4		T194	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	84254	1		T1	7		T2	2		T3	7
auto[1]	97161	1		T1	6		T2	5		T3	6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	53144	1		T1	3		T3	4		T12	1
auto[TlIntgErrNone]	partial	auto[1]	51463	1		T1	2		T2	1		T11	3
auto[TlIntgErrNone]	full_word	auto[0]	30984	1		T1	4		T2	2		T3	3
auto[TlIntgErrNone]	full_word	auto[1]	45554	1		T1	4		T2	4		T3	6
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T61	2		T194	4		T246	3
auto[TlIntgErrCmd]	partial	auto[1]	36	1		T54	2		T61	1		T194	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T265	1		T269	1		T270	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T54	1		T250	1		T269	1
auto[TlIntgErrData]	partial	auto[0]	37	1		T54	1		T61	1		T194	4
auto[TlIntgErrData]	partial	auto[1]	40	1		T54	1		T61	2		T194	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T246	1		T271	1		T269	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T197	1		T265	1		T267	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1		T54	2		T61	3		T194	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1		T54	3		T194	4		T246	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T61	1		T266	1		T250	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T265	2		T266	1		T267	2