Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.11	94.94	64.18	93.93		87.50	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	282726225	12141	0	0
ep_in_enable_rd_A	282726225	1686	0	0
ep_out_enable_rd_A	282726225	1607	0	0
in_iso_rd_A	282726225	1595	0	0
intr_enable_rd_A	282726225	2283	0	0
out_iso_rd_A	282726225	1467	0	0
phy_config_rd_A	282726225	966	0	0
phy_pins_drive_rd_A	282726225	1328	0	0
rxenable_setup_rd_A	282726225	1586	0	0
set_nak_out_rd_A	282726225	1497	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282726225	12141	0	0
T52	4335	874	0	0
T53	1783	124	0	0
T54	5553	2	0	0
T61	5368	5	0	0
T80	5760	18	0	0
T82	4367	6	0	0
T192	6362	371	0	0
T193	4586	854	0	0
T194	10456	6	0	0
T195	4067	9	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282726225	1686	0	0
T64	1631	6	0	0
T82	4367	13	0	0
T199	1724	7	0	0
T244	5999	9	0	0
T246	12773	204	0	0
T247	16263	81	0	0
T248	2190	70	0	0
T249	3688	24	0	0
T250	14416	337	0	0
T251	6899	10	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282726225	1607	0	0
T64	1631	6	0	0
T82	4367	6	0	0
T199	1724	3	0	0
T246	12773	99	0	0
T247	16263	113	0	0
T248	2190	52	0	0
T249	3688	23	0	0
T250	14416	322	0	0
T251	6899	30	0	0
T252	6871	44	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282726225	1595	0	0
T82	4367	44	0	0
T195	4067	4	0	0
T199	1724	8	0	0
T245	15316	3	0	0
T246	12773	112	0	0
T247	16263	109	0	0
T248	2190	46	0	0
T249	3688	5	0	0
T250	14416	214	0	0
T251	6899	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282726225	2283	0	0
T64	1631	4	0	0
T82	4367	11	0	0
T195	4067	6	0	0
T199	1724	1	0	0
T246	12773	281	0	0
T247	16263	130	0	0
T248	2190	6	0	0
T249	3688	18	0	0
T253	1312	25	0	0
T254	1252	11	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282726225	1467	0	0
T82	4367	10	0	0
T195	4067	7	0	0
T199	1724	7	0	0
T245	15316	2	0	0
T246	12773	94	0	0
T247	16263	123	0	0
T248	2190	4	0	0
T249	3688	14	0	0
T250	14416	389	0	0
T251	6899	4	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282726225	966	0	0
T64	1631	2	0	0
T82	4367	6	0	0
T195	4067	13	0	0
T199	1724	9	0	0
T246	12773	94	0	0
T247	16263	106	0	0
T248	2190	39	0	0
T250	14416	170	0	0
T251	6899	27	0	0
T252	6871	5	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282726225	1328	0	0
T64	1631	2	0	0
T82	4367	30	0	0
T195	4067	16	0	0
T246	12773	88	0	0
T247	16263	144	0	0
T248	2190	3	0	0
T249	3688	24	0	0
T250	14416	189	0	0
T251	6899	68	0	0
T252	6871	39	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282726225	1586	0	0
T64	1631	5	0	0
T82	4367	5	0	0
T192	6362	3	0	0
T195	4067	35	0	0
T199	1724	2	0	0
T246	12773	167	0	0
T247	16263	90	0	0
T248	2190	43	0	0
T249	3688	30	0	0
T250	14416	251	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282726225	1497	0	0
T64	1631	2	0	0
T82	4367	8	0	0
T199	1724	36	0	0
T246	12773	125	0	0
T247	16263	116	0	0
T248	2190	51	0	0
T249	3688	22	0	0
T250	14416	365	0	0
T251	6899	49	0	0
T252	6871	49	0	0