Unified Coverage Report :: Module :: usb_fs_rx

Module : usb_fs_rx

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.99	98.92	86.77			93.26

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_rx	92.99	98.92	86.77			93.26

---

Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_rx

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.99	98.92	86.77			93.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.99	98.92	86.77			93.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	50.00				100.00	u_usb_fs_nb_pe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usb_fs_rx

	Line No.	Total	Covered	Percent
TOTAL		186	184	98.92
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
ALWAYS	123	5	5	100.00
ALWAYS	133	11	11	100.00
ALWAYS	152	5	5	100.00
ALWAYS	170	5	5	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	223	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
ALWAYS	250	5	5	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
ALWAYS	292	3	3	100.00
ALWAYS	300	9	8	88.89
CONT_ASSIGN	323	1	1	100.00
ALWAYS	327	8	8	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
ALWAYS	348	3	3	100.00
CONT_ASSIGN	356	1	1	100.00
ALWAYS	371	12	12	100.00
ALWAYS	397	5	5	100.00
ALWAYS	407	5	5	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
ALWAYS	429	5	4	80.00
ALWAYS	438	3	3	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
ALWAYS	461	5	5	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	476	1	1	100.00
ALWAYS	479	5	5	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
ALWAYS	501	5	5	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	532	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
ALWAYS	548	5	5	100.00
ALWAYS	561	7	7	100.00
CONT_ASSIGN	572	1	1	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
CONT_ASSIGN	589	1	1	100.00
CONT_ASSIGN	590	1	1	100.00
ALWAYS	593	5	5	100.00
ALWAYS	609	26	26	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
71	1	1
72	1	1
73	1	1
123	1	1
124	1	1
125	1	1
127	1	1
128	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
139	1	1
140	1	1
141	1	1
143	1	1
144	1	1
145	1	1
152	1	1
154	1	1
157	1	1
162	1	1
163	1	1
			MISSING_ELSE
170	1	1
172	1	1
175	1	1
180	1	1
181	1	1
			MISSING_ELSE
222	1	1
223	1	1
243	1	1
244	1	1
247	1	1
250	1	1
251	1	1
253	1	1
254	1	1
256	1	1
277	1	1
278	1	1
283	1	1
287	1	1
288	1	1
292	1	1
293	1	1
295	1	1
300	1	1
303	1	1
304	0	1
306	1	1
307	1	1
311	1	1
312	1	1
315	1	1
318	1	1
323	1	1
327	1	1
328	1	1
329	1	1
331	1	1
332	1	1
333	1	1
335	1	1
336	1	1
344	1	1
345	1	1
348	1	1
349	1	1
351	1	1
356	1	1
371	1	1
372	1	1
373	1	1
374	1	1
375	1	1
379	1	1
380	1	1
381	1	1
382	1	1
383	1	1
384	1	1
388	1	1
397	1	1
398	1	1
399	1	1
400	1	1
402	1	1
407	1	1
408	1	1
410	1	1
411	1	1
413	1	1
419	1	1
425	1	1
429	1	1
430	1	1
431	1	1
432	1	1
433	0	1
			MISSING_ELSE
438	1	1
439	1	1
441	1	1
445	1	1
457	1	1
458	1	1
461	1	1
462	1	1
463	1	1
464	1	1
466	1	1
475	1	1
476	1	1
479	1	1
481	1	1
482	1	1
			MISSING_ELSE
485	1	1
486	1	1
			MISSING_ELSE
497	1	1
498	1	1
501	1	1
503	1	1
504	1	1
			MISSING_ELSE
507	1	1
508	1	1
			MISSING_ELSE
517	1	1
518	1	1
519	1	1
521	1	1
525	1	1
532	1	1
533	1	1
536	1	1
541	1	1
548	1	1
550	1	1
551	1	1
			MISSING_ELSE
554	1	1
555	1	1
			MISSING_ELSE
561	1	1
562	1	1
563	1	1
565	1	1
566	1	1
567	1	1
568	1	1
			MISSING_ELSE
572	1	1
573	1	1
574	1	1
575	1	1
577	1	1
578	1	1
588	1	1
589	1	1
590	1	1
593	1	1
595	1	1
596	1	1
			MISSING_ELSE
599	1	1
600	1	1
			MISSING_ELSE
609	1	1
610	1	1
611	1	1
612	1	1
613	1	1
614	1	1
615	1	1
616	1	1
617	1	1
619	1	1
620	1	1
621	1	1
622	1	1
623	1	1
624	1	1
625	1	1
626	1	1
627	1	1
629	1	1
630	1	1
631	1	1
632	1	1
633	1	1
634	1	1
635	1	1
636	1	1

---

Cond Coverage for Module : usb_fs_rx

	Total	Covered	Percent
Conditions	189	164	86.77
Logical	189	164	86.77
Non-Logical	0	0
Event	0	0

 LINE       71
 EXPRESSION (cfg_pinflip_i ? usb_dn_i : usb_dp_i)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       72
 EXPRESSION (cfg_pinflip_i ? usb_dp_i : usb_dn_i)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       73
 EXPRESSION (usb_d_i ^ cfg_pinflip_i)
             ---1---   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       128
 EXPRESSION (usb_d_flipped ? DJ[1:0] : DK[1:0])
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       154
 EXPRESSION (line_state_q == DT)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       162
 EXPRESSION (dpair != line_state_q[1:0])
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       172
 EXPRESSION (diff_state_q == DT)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       180
 EXPRESSION (ddiff != diff_state_q[1:0])
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       222
 EXPRESSION ((line_state_q == SE0) || ((line_state_q == DT) && (line_state_qq == SE0)))
             ----------1----------    ------------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       222
 SUB-EXPRESSION (line_state_q == SE0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       222
 SUB-EXPRESSION ((line_state_q == DT) && (line_state_qq == SE0))
                 ----------1---------    -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       222
 SUB-EXPRESSION (line_state_q == DT)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       222
 SUB-EXPRESSION (line_state_qq == SE0)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       223
 EXPRESSION (cfg_use_diff_rcvr_i ? (use_se ? line_state_q : diff_state_q) : line_state_q)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       223
 SUB-EXPRESSION (use_se ? line_state_q : diff_state_q)
                 ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       243
 EXPRESSION (bit_phase_q == 2'b1)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       244
 EXPRESSION (bit_phase_q == 2'd2)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       247
 EXPRESSION ((line_state_rx == DT) ? 0 : ((bit_phase_q + 1)))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       247
 SUB-EXPRESSION (line_state_rx == DT)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       277
 EXPRESSION (packet_valid_d & ((~packet_valid_q)))
             -------1------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       278
 EXPRESSION (((~packet_valid_d)) & packet_valid_q)
             ---------1---------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       283
 EXPRESSION ((cfg_eop_single_bit_i && (line_history_q[1:0] == 2'b0)) || (line_history_q[3:0] == 4'b0) || bitstuff_error_q || see_preamble)
             ---------------------------1---------------------------    --------------2--------------    --------3-------    ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Covered	T1,T2,T3

 LINE       283
 SUB-EXPRESSION (cfg_eop_single_bit_i && (line_history_q[1:0] == 2'b0))
                 ----------1---------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       283
 SUB-EXPRESSION (line_history_q[1:0] == 2'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       283
 SUB-EXPRESSION (line_history_q[3:0] == 4'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       287
 EXPRESSION ((line_history_q[3:0] == 4'b1001) & ((~tx_en_i)) & ((~in_packet_q)))
             ----------------1---------------   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       287
 SUB-EXPRESSION (line_history_q[3:0] == 4'b1001)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       288
 EXPRESSION (see_eop ? 1'b0 : (see_sop ? 1'b1 : in_packet_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       288
 SUB-EXPRESSION (see_sop ? 1'b1 : in_packet_q)
                 ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       306
 EXPRESSION (((!packet_valid_q)) && (line_history_q[11:0] == 12'b011001100101))
             ---------1---------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       306
 SUB-EXPRESSION (line_history_q[11:0] == 12'b011001100101)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       311
 EXPRESSION (packet_valid_q && see_eop)
             -------1------    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       323
 EXPRESSION (line_state_valid ? ({line_history_q[9:0], line_state_rx[1:0]}) : line_history_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION ((((~tx_en_i)) & line_state_valid) ? (line_state_q == DJ) : rx_idle_det_q)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (((~tx_en_i)) & line_state_valid)
                 ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (line_state_q == DJ)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       356
 EXPRESSION (diff_rx_ok_i & ((~tx_en_i)) & (line_history_q[1:0] == 2'b10))
             ------1-----   ------2-----   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       356
 SUB-EXPRESSION (line_history_q[1:0] == 2'b10)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       379
 EXPRESSION (packet_valid_q && line_state_valid)
             -------1------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       419
 EXPRESSION (dvalid_raw && ( ! (bitstuff_history_q[5:0] == 6'b111111) ))
             -----1----    ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T10
1	1	Covered	T1,T2,T3

 LINE       419
 SUB-EXPRESSION ( ! (bitstuff_history_q[5:0] == 6'b111111) )
                    -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T9,T10

 LINE       419
 SUB-EXPRESSION (bitstuff_history_q[5:0] == 6'b111111)
                -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T9,T10

 LINE       425
 EXPRESSION (bitstuff_history_q == 7'b1111111)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       432
 EXPRESSION (bitstuff_error && dvalid_raw)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       445
 EXPRESSION (bitstuff_error_q && packet_end)
             --------1-------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       457
 EXPRESSION (full_pid_q[4:1] == (~full_pid_q[8:5]))
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       461
 EXPRESSION (dvalid && ((!pid_complete)))
             ---1--    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       475
 EXPRESSION (crc5_q == 5'b01100)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       476
 EXPRESSION (din ^ crc5_q[4])
             -1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       485
 EXPRESSION (dvalid && pid_complete)
             ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       497
 EXPRESSION (crc16_q == 16'b1000000000001101)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       498
 EXPRESSION (din ^ crc16_q[15])
             -1-   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       507
 EXPRESSION (dvalid && pid_complete)
             ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       517
 EXPRESSION (full_pid_q[2:1] == 2'b1)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       518
 EXPRESSION (full_pid_q[2:1] == 2'b11)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       519
 EXPRESSION (full_pid_q[2:1] == 2'b10)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       521
 EXPRESSION ((packet_valid_q & pid_valid & pid_complete) && (usb_pid_e'(full_pid_q[4:1]) == UsbPidPre))
             ---------------------1---------------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       521
 SUB-EXPRESSION (packet_valid_q & pid_valid & pid_complete)
                 -------1------   ----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T1,T3,T8
1	1	1	Covered	T1,T2,T3

 LINE       521
 SUB-EXPRESSION (usb_pid_e'(full_pid_q[4:1]) == UsbPidPre)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       525
 EXPRESSION (pid_valid && ((!bitstuff_error_q)) && (pkt_is_handshake || (pkt_is_data && crc16_valid) || (pkt_is_token && crc5_valid)))
             ----1----    ----------2----------    -----------------------------------------3----------------------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       525
 SUB-EXPRESSION (pkt_is_handshake || (pkt_is_data && crc16_valid) || (pkt_is_token && crc5_valid))
                 --------1-------    --------------2-------------    --------------3-------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T3,T8
1	0	0	Covered	T1,T2,T3

 LINE       525
 SUB-EXPRESSION (pkt_is_data && crc16_valid)
                 -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T8

 LINE       525
 SUB-EXPRESSION (pkt_is_token && crc5_valid)
                 ------1-----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       532
 EXPRESSION (pkt_is_token & packet_end & ((!crc5_valid)))
             ------1-----   -----2----   -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Not Covered

 LINE       533
 EXPRESSION (pkt_is_data & packet_end & ((!crc16_valid)))
             -----1-----   -----2----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T3,T8
1	1	1	Not Covered

 LINE       536
 EXPRESSION (((!pid_valid)) && packet_end)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       554
 EXPRESSION (dvalid && pid_complete && pkt_is_token && ((!token_payload_done)))
             ---1--    ------2-----    ------3-----    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T14,T28,T29
1	1	0	1	Covered	T1,T3,T8
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T2,T3

 LINE       565
 EXPRESSION (token_payload_done && pkt_is_token)
             ---------1--------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       595
 EXPRESSION (packet_start || rx_data_buffer_full)
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3

 LINE       599
 EXPRESSION (dvalid && pid_complete && pkt_is_data)
             ---1--    ------2-----    -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T8
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T3,T8

---

Branch Coverage for Module : usb_fs_rx

	Line No.	Total	Covered	Percent
Branches		89	83	93.26
TERNARY	71	2	1	50.00
TERNARY	72	2	1	50.00
TERNARY	223	3	1	33.33
TERNARY	247	2	2	100.00
TERNARY	288	3	3	100.00
TERNARY	323	2	2	100.00
TERNARY	344	2	2	100.00
IF	123	3	3	100.00
IF	133	3	3	100.00
IF	154	3	3	100.00
IF	172	3	3	100.00
IF	250	3	3	100.00
IF	292	2	2	100.00
IF	300	5	4	80.00
IF	327	3	3	100.00
IF	348	2	2	100.00
CASE	371	5	5	100.00
IF	379	6	6	100.00
IF	397	3	3	100.00
IF	407	3	3	100.00
IF	430	3	2	66.67
IF	438	2	2	100.00
IF	461	3	3	100.00
IF	481	2	2	100.00
IF	485	2	2	100.00
IF	503	2	2	100.00
IF	507	2	2	100.00
IF	550	2	2	100.00
IF	554	2	2	100.00
IF	565	2	2	100.00
IF	595	2	2	100.00
IF	599	2	2	100.00
IF	609	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_rx.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	(cfg_pinflip_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	72	(cfg_pinflip_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	223	(cfg_use_diff_rcvr_i) ? 
-2-:	223	(use_se) ? 

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	247	((line_state_rx == DT)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	(see_eop) ? 
-2-:	288	(see_sop) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	(line_state_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	344	(((~tx_en_i) & line_state_valid)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (tx_en_i)
-2-:	128	(usb_d_flipped) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	133	if ((!rst_ni))
-2-:	138	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	154	if ((line_state_q == DT))
-2-:	162	if ((dpair != line_state_q[1:0]))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	172	if ((diff_state_q == DT))
-2-:	180	if ((ddiff != diff_state_q[1:0]))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	250	if ((!rst_ni))
-2-:	253	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	292	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if (line_state_valid)
-2-:	303	if ((~diff_rx_ok_i))
-3-:	306	if (((!packet_valid_q) && (line_history_q[11:0] == 12'b011001100101)))
-4-:	311	if ((packet_valid_q && see_eop))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Not Covered
1	0	1	-	Covered	T1,T2,T3
1	0	0	1	Covered	T1,T2,T3
1	0	0	0	Covered	T1,T2,T3
0	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	327	if ((!rst_ni))
-2-:	331	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	348	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	371	case (line_history_q[3:0])

Branches:

-1-	Status	Tests
4'b0101	Covered	T1,T2,T3
4'b0110	Covered	T1,T2,T3
4'b1001	Covered	T1,T2,T3
4'b1010	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	379	if ((packet_valid_q && line_state_valid))
-2-:	380	case (line_history_q[3:0])

Branches:

-1-	-2-	Status	Tests
1	4'b0101	Covered	T1,T2,T3
1	4'b0110	Covered	T1,T2,T3
1	4'b1001	Covered	T1,T2,T3
1	4'b1010	Covered	T1,T2,T3
1	default	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	397	if (packet_end)
-2-:	399	if (dvalid_raw)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	407	if ((!rst_ni))
-2-:	410	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	430	if (packet_start)
-2-:	432	if ((bitstuff_error && dvalid_raw))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	438	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((dvalid && (!pid_complete)))
-2-:	463	if (packet_start)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	481	if (packet_start)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	485	if ((dvalid && pid_complete))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	503	if (packet_start)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	507	if ((dvalid && pid_complete))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	if (packet_start)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	554	if ((((dvalid && pid_complete) && pkt_is_token) && (!token_payload_done)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	565	if ((token_payload_done && pkt_is_token))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	595	if ((packet_start || rx_data_buffer_full))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	599	if (((dvalid && pid_complete) && pkt_is_data))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	609	if ((!rst_ni))
-2-:	619	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3