Unified Coverage Report :: Module :: usb_fs_nb_out_pe

Module : usb_fs_nb_out_pe

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.33	87.40	73.13		50.00	81.13	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe	78.33	87.40	73.13		50.00	81.13	100.00

---

Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.33	87.40	73.13		50.00	81.13	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.33	87.40	73.13		50.00	81.13	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	50.00				100.00	u_usb_fs_nb_pe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usb_fs_nb_out_pe

	Line No.	Total	Covered	Percent
TOTAL		127	111	87.40
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	185	6	6	100.00
ALWAYS	197	4	4	100.00
ALWAYS	213	54	39	72.22
CONT_ASSIGN	326	1	1	100.00
ALWAYS	329	3	3	100.00
CONT_ASSIGN	339	1	1	100.00
ALWAYS	342	3	3	100.00
ALWAYS	351	7	6	85.71
CONT_ASSIGN	365	1	1	100.00
ALWAYS	368	5	5	100.00
ALWAYS	378	9	9	100.00
ALWAYS	395	3	3	100.00
ALWAYS	407	6	6	100.00
CONT_ASSIGN	423	1	1	100.00
ALWAYS	426	6	6	100.00
CONT_ASSIGN	440	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
91	1	1
132	1	1
133	1	1
135	1	1
141	1	1
145	1	1
149	1	1
153	1	1
158	1	1
164	1	1
165	1	1
172	1	1
173	1	1
176	1	1
177	1	1
179	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
			MISSING_ELSE
197	1	1
198	1	1
200	1	1
201	1	1
			MISSING_ELSE
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
222	1	1
226	1	1
227	1	1
228	1	1
230	1	1
238	1	1
240	1	1
241	1	1
242	1	1
243	0	1
245	1	1
250	1	1
254	0	1
255	1	1
258	0	1
259	0	1
260	0	1
261	0	1
262	1	1
264	0	1
265	0	1
266	1	1
267	1	1
269	1	1
274	1	1
275	1	1
277	1	1
279	1	1
281	0	1
282	0	1
284	1	1
285	1	1
286	1	1
290	1	1
291	1	1
292	1	1
293	1	1
294	1	1
296	1	1
297	1	1
298	1	1
305	0	1
307	0	1
309	0	1
312	0	1
313	0	1
326	1	1
329	1	1
330	1	1
332	1	1
339	1	1
342	1	1
343	1	1
345	1	1
351	1	1
353	1	1
354	1	1
355	1	1
356	1	1
			MISSING_ELSE
359	1	1
360	0	1
			MISSING_ELSE
365	1	1
368	1	1
369	1	1
370	1	1
371	1	1
373	1	1
378	1	1
379	1	1
380	1	1
381	1	1
383	1	1
384	1	1
385	1	1
386	1	1
388	1	1
395	1	1
396	1	1
398	1	1
407	1	1
408	1	1
410	1	1
411	1	1
412	1	1
413	1	1
			MISSING_ELSE
423	1	1
426	1	1
427	1	1
429	1	1
430	1	1
431	1	1
432	1	1
			MISSING_ELSE
440	1	1

---

Cond Coverage for Module : usb_fs_nb_out_pe

	Total	Covered	Percent
Conditions	134	98	73.13
Logical	134	98	73.13
Non-Logical	0	0
Event	0	0

 LINE       135
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T3,T8
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       135
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       135
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (token_received && (rx_pid == UsbPidOut))
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T2,T11,T14
1	1	Covered	T1,T3,T8

 LINE       141
 SUB-EXPRESSION (rx_pid == UsbPidOut)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       145
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T16,T17

 LINE       145
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T16,T17

 LINE       149
 EXPRESSION (rx_pkt_end_i && ((!rx_pkt_valid_i)))
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       153
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)))
             ------1-----    -------2------    --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T8
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T3,T8

 LINE       153
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T15,T16
1	0	Covered	T1,T2,T3

 LINE       153
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       153
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T15,T16

 LINE       158
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) ))
             ------1-----    -------2------    -----------------------------3----------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T1,T3,T8
1	1	1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) )
                    --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T15,T16
1	0	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       158
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T15,T16

 LINE       165
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       176
 EXPRESSION (out_ep_enabled_i[out_ep_index_d] & ep_in_hw)
             ----------------1---------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

 LINE       179
 EXPRESSION (data_packet_received && ep_active && (rx_pid_i[3] != data_toggle_q[out_ep_index_d]))
             ----------1---------    ----2----    -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T8
1	0	1	Not Covered
1	1	0	Covered	T1,T3,T8
1	1	1	Not Covered

 LINE       179
 SUB-EXPRESSION (rx_pid_i[3] != data_toggle_q[out_ep_index_d])
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       188
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Not Covered
1	1	Covered	T15,T16,T17

 LINE       190
 EXPRESSION (out_token_received && ep_active)
             ---------1--------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Not Covered
1	1	Covered	T1,T3,T8

 LINE       226
 EXPRESSION (ep_active && (out_token_received || (setup_token_received && ep_is_control)))
             ----1----    -------------------------------2-------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       226
 SUB-EXPRESSION (out_token_received || (setup_token_received && ep_is_control))
                 ---------1--------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T3,T8

 LINE       226
 SUB-EXPRESSION (setup_token_received && ep_is_control)
                 ----------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T17
1	0	Covered	T19,T20,T21
1	1	Covered	T15,T16,T17

 LINE       242
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Not Covered

 LINE       250
 EXPRESSION (((!ep_is_control)) && out_ep_iso_i[out_ep_index] && data_packet_received)
             ---------1--------    -------------2------------    ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T8
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       255
 EXPRESSION (bad_data_toggle && ((!out_ep_stall_i[out_ep_index])))
             -------1-------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T13
1	0	Not Covered
1	1	Not Covered

 LINE       262
 EXPRESSION (invalid_packet_received || non_data_packet_received)
             -----------1-----------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Not Covered
1	0	Not Covered

 LINE       279
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Not Covered
1	0	Not Covered

 LINE       292
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T13
0	1	Not Covered
1	0	Not Covered

 LINE       307
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       345
 EXPRESSION (link_reset_i ? StIdle : out_xact_state_next)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       353
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Not Covered
1	1	Covered	T15,T16,T17

 LINE       398
 EXPRESSION ((out_xact_state == StRcvdDataStart) && rx_data_put_i)
             -----------------1-----------------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       398
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       410
 EXPRESSION ((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))
             -------------1------------    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3

 LINE       410
 SUB-EXPRESSION (out_xact_state == StIdle)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T8
1	Covered	T1,T2,T3

 LINE       410
 SUB-EXPRESSION (out_xact_state == StRcvdOut)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       412
 EXPRESSION (out_ep_data_put_o && out_ep_full_i[out_ep_index])
             --------1--------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T22,T23
1	0	Covered	T1,T3,T8
1	1	Covered	T9,T22,T23

 LINE       423
 EXPRESSION (((!nak_out_transaction)) && ((~&out_ep_put_addr_o)) && out_ep_data_put_o)
             ------------1-----------    -----------2-----------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T22,T23
1	0	1	Covered	T24,T6,T25
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T3,T8

 LINE       429
 EXPRESSION (out_xact_state == StRcvdOut)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       431
 EXPRESSION ((out_xact_state == StRcvdDataStart) && increment_addr)
             -----------------1-----------------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       431
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       440
 EXPRESSION ((out_xact_state == StRcvdDataStart) && (ep_is_control || ((!out_ep_iso_i[out_ep_index]))) && ((!out_ep_stall_i[out_ep_index])) && bad_data_toggle)
             -----------------1-----------------    -------------------------2------------------------    ----------------3----------------    -------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Covered	T1,T3,T13
1	1	1	1	Not Covered

 LINE       440
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       440
 SUB-EXPRESSION (ep_is_control || ((!out_ep_iso_i[out_ep_index])))
                 ------1------    ---------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T2,T3
1	0	Not Covered

---

FSM Coverage for Module : usb_fs_nb_out_pe

Summary for FSM :: out_xact_state

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	8	4	50.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: out_xact_state

---

states	Line No.	Covered	Tests
StIdle	345	Covered	T1,T2,T3
StRcvdDataEnd	267	Covered	T1,T3,T8
StRcvdDataStart	241	Covered	T1,T3,T8
StRcvdIsoDataEnd	254	Not Covered
StRcvdOut	227	Covered	T1,T3,T8

transitions	Line No.	Covered	Tests
StIdle->StRcvdOut	227	Covered	T1,T3,T8
StRcvdDataEnd->StIdle	345	Covered	T1,T3,T8
StRcvdDataStart->StIdle	345	Not Covered
StRcvdDataStart->StRcvdDataEnd	267	Covered	T1,T3,T8
StRcvdDataStart->StRcvdIsoDataEnd	254	Not Covered
StRcvdIsoDataEnd->StIdle	345	Not Covered
StRcvdOut->StIdle	345	Not Covered
StRcvdOut->StRcvdDataStart	241	Covered	T1,T3,T8

---

Branch Coverage for Module : usb_fs_nb_out_pe

	Line No.	Total	Covered	Percent
Branches		53	43	81.13
TERNARY	165	2	1	50.00
IF	185	4	4	100.00
IF	197	3	3	100.00
CASE	222	18	10	55.56
IF	329	2	2	100.00
IF	342	3	3	100.00
IF	353	3	3	100.00
IF	359	2	1	50.00
IF	368	3	3	100.00
IF	378	3	3	100.00
IF	395	2	2	100.00
IF	407	4	4	100.00
IF	426	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	165	(ep_in_hw) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	185	if ((!rst_ni))
-2-:	188	if ((setup_token_received && ep_active))
-3-:	190	if ((out_token_received && ep_active))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T15,T16,T17
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	197	if ((!rst_ni))
-2-:	200	if (rx_data_put_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	case (out_xact_state)
-2-:	226	if ((ep_active && (out_token_received || (setup_token_received && ep_is_control))))
-3-:	240	if (rx_pkt_start_i)
-4-:	242	if ((timeout_cntdown_q == '0))
-5-:	250	if ((((!ep_is_control) && out_ep_iso_i[out_ep_index]) && data_packet_received))
-6-:	255	if ((bad_data_toggle && (!out_ep_stall_i[out_ep_index])))
-7-:	262	if ((invalid_packet_received || non_data_packet_received))
-8-:	266	if (data_packet_received)
-9-:	277	if (current_xact_setup_q)
-10-:	279	if ((nak_out_transaction | out_ep_full_i[out_ep_index]))
-11-:	290	if (out_ep_stall_i[out_ep_index])
-12-:	292	if ((nak_out_transaction | out_ep_full_i[out_ep_index]))
-13-:	307	if ((nak_out_transaction | out_ep_full_i[out_ep_index]))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T8
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRcvdOut	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T8
StRcvdOut	-	0	1	-	-	-	-	-	-	-	-	-	Not Covered
StRcvdOut	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T8
StRcvdDataStart	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
StRcvdDataStart	-	-	-	0	1	-	-	-	-	-	-	-	Not Covered
StRcvdDataStart	-	-	-	0	0	1	-	-	-	-	-	-	Not Covered
StRcvdDataStart	-	-	-	0	0	0	1	-	-	-	-	-	Covered	T1,T3,T8
StRcvdDataStart	-	-	-	0	0	0	0	-	-	-	-	-	Covered	T1,T3,T8
StRcvdDataEnd	-	-	-	-	-	-	-	1	1	-	-	-	Not Covered
StRcvdDataEnd	-	-	-	-	-	-	-	1	0	-	-	-	Covered	T15,T16,T17
StRcvdDataEnd	-	-	-	-	-	-	-	0	-	1	-	-	Covered	T8,T26,T27
StRcvdDataEnd	-	-	-	-	-	-	-	0	-	0	1	-	Covered	T9,T22,T23
StRcvdDataEnd	-	-	-	-	-	-	-	0	-	0	0	-	Covered	T1,T3,T13
StRcvdIsoDataEnd	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StRcvdIsoDataEnd	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	329	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	342	if ((!rst_ni))
-2-:	345	(link_reset_i) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	353	if ((setup_token_received && ep_active))
-2-:	355	if (new_pkt_end)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T16,T17
0	1	Covered	T1,T3,T13
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if (out_datatog_we_i)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	368	if ((!rst_ni))
-2-:	370	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	378	if ((!rst_ni))
-2-:	383	if (out_xact_start)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	407	if ((!rst_ni))
-2-:	410	if (((out_xact_state == StIdle) || (out_xact_state == StRcvdOut)))
-3-:	412	if ((out_ep_data_put_o && out_ep_full_i[out_ep_index]))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T9,T22,T23
0	0	0	Covered	T1,T3,T8

	LineNo.	Expression
-1-:	426	if ((!rst_ni))
-2-:	429	if ((out_xact_state == StRcvdOut))
-3-:	431	if (((out_xact_state == StRcvdDataStart) && increment_addr))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T8
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : usb_fs_nb_out_pe

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutXactStateValid_A	281958275	281859675	0	0

OutXactStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281958275	281859675	0	0
T1	401680	401597	0	0
T2	401112	401037	0	0
T3	401673	401575	0	0
T8	401898	401745	0	0
T9	402359	402188	0	0
T10	401896	401662	0	0
T11	401402	401342	0	0
T12	5118	4267	0	0
T13	401813	401739	0	0
T14	402036	401986	0	0