Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	76971	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	67680	1		T1	8		T2	23		T3	129

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	73320	1		T1	6		T2	21		T3	93
values[0x0]	35495	1		T1	4		T2	2		T3	175
values[0x1]	35836	1		T1	5		T2	3		T3	183

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57718	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	86933	1		T1	9		T2	25		T3	168

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	465	1		T3	2		T50	4		T81	3
valid_sources[0x01]	734	1		T3	2		T14	2		T30	1
valid_sources[0x02]	505	1		T3	1		T43	2		T268	1
valid_sources[0x03]	375	1		T3	2		T28	1		T268	1
valid_sources[0x04]	450	1		T3	2		T17	1		T50	2
valid_sources[0x05]	356	1		T3	2		T16	7		T50	3
valid_sources[0x06]	423	1		T3	3		T23	1		T129	1
valid_sources[0x07]	1481	1		T3	1		T41	1089		T18	2
valid_sources[0x08]	388	1		T3	2		T50	1		T81	5
valid_sources[0x09]	365	1		T18	1		T50	2		T269	1
valid_sources[0x0a]	341	1		T3	1		T50	4		T81	5
valid_sources[0x0b]	422	1		T3	2		T23	1		T79	1
valid_sources[0x0c]	575	1		T3	3		T50	1		T81	2
valid_sources[0x0d]	379	1		T43	1		T270	1		T50	1
valid_sources[0x0e]	405	1		T22	1		T29	1		T6	3
valid_sources[0x0f]	1158	1		T3	1		T271	25		T50	4
valid_sources[0x10]	689	1		T3	2		T18	2		T272	26
valid_sources[0x11]	449	1		T3	1		T26	1		T50	1
valid_sources[0x12]	405	1		T3	1		T11	1		T13	1
valid_sources[0x13]	496	1		T3	2		T43	1		T50	2
valid_sources[0x14]	565	1		T3	4		T39	1		T221	1
valid_sources[0x15]	402	1		T134	1		T50	2		T81	2
valid_sources[0x16]	391	1		T3	1		T273	2		T50	3
valid_sources[0x17]	441	1		T22	2		T274	1		T270	1
valid_sources[0x18]	2193	1		T3	1		T42	2		T22	1
valid_sources[0x19]	393	1		T3	1		T42	1		T50	2
valid_sources[0x1a]	699	1		T3	2		T23	1		T46	13
valid_sources[0x1b]	661	1		T28	1		T40	2		T50	3
valid_sources[0x1c]	866	1		T3	3		T19	1		T50	3
valid_sources[0x1d]	520	1		T3	1		T19	1		T79	1
valid_sources[0x1e]	533	1		T3	1		T32	1		T50	3
valid_sources[0x1f]	550	1		T3	1		T275	26		T50	1
valid_sources[0x20]	522	1		T3	6		T8	1		T276	2
valid_sources[0x21]	469	1		T3	2		T23	1		T17	1
valid_sources[0x22]	486	1		T3	1		T8	1		T13	1
valid_sources[0x23]	454	1		T270	1		T277	4		T81	7
valid_sources[0x24]	440	1		T3	3		T28	1		T50	1
valid_sources[0x25]	586	1		T3	1		T24	3		T278	5
valid_sources[0x26]	694	1		T1	15		T3	3		T12	1
valid_sources[0x27]	1542	1		T3	3		T29	2		T273	1
valid_sources[0x28]	1765	1		T3	1		T17	1		T24	6
valid_sources[0x29]	420	1		T3	2		T17	1		T20	1
valid_sources[0x2a]	563	1		T3	1		T42	1		T134	1
valid_sources[0x2b]	398	1		T3	2		T93	1		T50	2
valid_sources[0x2c]	630	1		T3	2		T23	1		T25	2
valid_sources[0x2d]	462	1		T3	2		T48	19		T25	1
valid_sources[0x2e]	453	1		T279	2		T18	1		T79	2
valid_sources[0x2f]	527	1		T18	1		T50	1		T280	26
valid_sources[0x30]	750	1		T3	3		T18	1		T87	4
valid_sources[0x31]	458	1		T3	1		T221	1		T43	1
valid_sources[0x32]	408	1		T3	4		T16	3		T281	1
valid_sources[0x33]	732	1		T3	1		T50	4		T81	1
valid_sources[0x34]	430	1		T3	3		T17	1		T50	1
valid_sources[0x35]	443	1		T3	1		T50	2		T282	1
valid_sources[0x36]	462	1		T3	1		T8	1		T50	2
valid_sources[0x37]	737	1		T274	1		T283	1		T273	4
valid_sources[0x38]	406	1		T3	5		T50	2		T212	1
valid_sources[0x39]	436	1		T3	1		T23	1		T50	2
valid_sources[0x3a]	452	1		T3	2		T221	1		T79	2
valid_sources[0x3b]	447	1		T3	3		T40	2		T50	3
valid_sources[0x3c]	433	1		T3	2		T9	6		T23	1
valid_sources[0x3d]	411	1		T3	3		T50	4		T81	6
valid_sources[0x3e]	465	1		T4	7		T284	7		T50	4
valid_sources[0x3f]	587	1		T81	3		T285	1		T286	2
valid_sources[0x40]	622	1		T3	1		T284	5		T281	1
valid_sources[0x41]	388	1		T3	1		T50	2		T81	1
valid_sources[0x42]	428	1		T3	3		T129	6		T50	1
valid_sources[0x43]	448	1		T221	3		T79	1		T278	5
valid_sources[0x44]	473	1		T3	4		T50	3		T81	3
valid_sources[0x45]	462	1		T3	2		T50	2		T81	4
valid_sources[0x46]	515	1		T3	1		T287	1		T81	4
valid_sources[0x47]	416	1		T3	1		T14	1		T50	1
valid_sources[0x48]	452	1		T3	4		T288	2		T50	2
valid_sources[0x49]	460	1		T3	1		T50	3		T81	4
valid_sources[0x4a]	431	1		T40	2		T274	1		T5	5
valid_sources[0x4b]	423	1		T3	1		T10	3		T268	1
valid_sources[0x4c]	483	1		T3	1		T79	1		T270	2
valid_sources[0x4d]	432	1		T3	2		T11	2		T10	1
valid_sources[0x4e]	679	1		T3	2		T17	4		T25	1
valid_sources[0x4f]	428	1		T3	2		T39	1		T20	1
valid_sources[0x50]	472	1		T3	2		T43	1		T50	5
valid_sources[0x51]	357	1		T3	3		T25	1		T50	1
valid_sources[0x52]	427	1		T3	1		T18	1		T273	3
valid_sources[0x53]	605	1		T3	5		T81	5		T289	1
valid_sources[0x54]	450	1		T3	1		T32	1		T93	1
valid_sources[0x55]	399	1		T3	1		T274	1		T50	3
valid_sources[0x56]	443	1		T29	1		T18	2		T79	1
valid_sources[0x57]	554	1		T3	1		T49	6		T17	1
valid_sources[0x58]	524	1		T3	2		T30	1		T50	1
valid_sources[0x59]	549	1		T30	1		T50	2		T81	5
valid_sources[0x5a]	571	1		T18	2		T79	1		T50	2
valid_sources[0x5b]	386	1		T3	2		T17	1		T273	2
valid_sources[0x5c]	459	1		T3	3		T28	1		T17	1
valid_sources[0x5d]	448	1		T3	1		T28	1		T30	6
valid_sources[0x5e]	634	1		T3	5		T221	1		T79	1
valid_sources[0x5f]	435	1		T3	2		T134	1		T79	1
valid_sources[0x60]	459	1		T50	1		T81	5		T290	1
valid_sources[0x61]	496	1		T3	1		T23	1		T287	1
valid_sources[0x62]	476	1		T3	7		T283	1		T81	7
valid_sources[0x63]	492	1		T3	3		T28	1		T274	1
valid_sources[0x64]	487	1		T3	3		T43	1		T26	2
valid_sources[0x65]	368	1		T3	1		T50	1		T133	1
valid_sources[0x66]	485	1		T3	1		T23	1		T287	1
valid_sources[0x67]	442	1		T3	1		T283	1		T50	4
valid_sources[0x68]	487	1		T3	2		T28	1		T274	1
valid_sources[0x69]	446	1		T3	1		T117	15		T291	1
valid_sources[0x6a]	447	1		T3	1		T16	6		T18	1
valid_sources[0x6b]	588	1		T2	26		T42	2		T221	5
valid_sources[0x6c]	442	1		T17	1		T50	2		T133	1
valid_sources[0x6d]	429	1		T3	2		T43	2		T36	11
valid_sources[0x6e]	1314	1		T3	6		T273	1		T50	2
valid_sources[0x6f]	1556	1		T3	2		T18	1		T50	5
valid_sources[0x70]	506	1		T17	2		T50	3		T81	11
valid_sources[0x71]	448	1		T3	1		T50	2		T81	3
valid_sources[0x72]	446	1		T3	4		T274	1		T50	4
valid_sources[0x73]	528	1		T3	2		T28	1		T81	2
valid_sources[0x74]	387	1		T3	2		T18	4		T25	2
valid_sources[0x75]	379	1		T3	1		T17	1		T221	3
valid_sources[0x76]	449	1		T20	1		T50	2		T81	1
valid_sources[0x77]	498	1		T3	2		T32	2		T276	1
valid_sources[0x78]	521	1		T3	1		T22	1		T284	1
valid_sources[0x79]	526	1		T3	5		T19	1		T291	1
valid_sources[0x7a]	641	1		T3	1		T129	2		T21	10
valid_sources[0x7b]	496	1		T3	3		T12	2		T13	1
valid_sources[0x7c]	676	1		T3	4		T19	4		T270	1
valid_sources[0x7d]	1144	1		T3	3		T10	1		T30	1
valid_sources[0x7e]	553	1		T13	1		T29	1		T129	1
valid_sources[0x7f]	741	1		T3	3		T30	4		T273	1
valid_sources[0x80]	433	1		T3	1		T281	3		T50	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27781

1

T1

2

T2

21

T3

47

values[0x0]

all_enables

biggest_size

22577

1

T1

3

T2

1

T3

57

values[0x1]

all_enables

biggest_size

17322

1

T1

3

T2

1

T3

25