Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	91573	1		T1	7		T2	3		T3	322
full_word	68730	1		T1	8		T2	23		T3	129

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	160043	1		T1	15		T2	26		T3	451
auto[TlIntgErrCmd]	88	1		T51	3		T58	5		T86	1
auto[TlIntgErrData]	80	1		T51	3		T58	3		T86	5
auto[TlIntgErrBoth]	92	1		T51	4		T58	2		T86	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	75290	1		T1	6		T2	21		T3	93
auto[1]	85013	1		T1	9		T2	5		T3	358

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	47188	1		T1	4		T3	46		T7	1
auto[TlIntgErrNone]	partial	auto[1]	44151	1		T1	3		T2	3		T3	276
auto[TlIntgErrNone]	full_word	auto[0]	27981	1		T1	2		T2	21		T3	47
auto[TlIntgErrNone]	full_word	auto[1]	40723	1		T1	6		T2	2		T3	82
auto[TlIntgErrCmd]	partial	auto[0]	31	1		T51	1		T58	1		T183	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T51	2		T58	2		T86	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T58	1		T183	1		T261	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T58	1		T183	1		T262	1
auto[TlIntgErrData]	partial	auto[0]	38	1		T51	2		T58	1		T86	3
auto[TlIntgErrData]	partial	auto[1]	36	1		T51	1		T58	2		T86	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T263	1		T259	1		T264	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T265	1		T259	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	42	1		T51	3		T58	2		T86	3
auto[TlIntgErrBoth]	partial	auto[1]	39	1		T86	1		T183	1		T257	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T266	1		T258	1		T267	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T51	1		T183	1		T257	1