Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.11	94.94	64.18	93.93		87.50	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	282411840	12635	0	0
ep_in_enable_rd_A	282411840	2529	0	0
ep_out_enable_rd_A	282411840	2561	0	0
in_iso_rd_A	282411840	3000	0	0
intr_enable_rd_A	282411840	3902	0	0
out_iso_rd_A	282411840	2405	0	0
phy_config_rd_A	282411840	1639	0	0
phy_pins_drive_rd_A	282411840	2282	0	0
rxenable_setup_rd_A	282411840	2901	0	0
set_nak_out_rd_A	282411840	2697	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	12635	0	0
T51	11041	3	0	0
T52	3467	7	0	0
T53	3385	6	0	0
T58	5594	4	0	0
T85	4057	9	0	0
T86	5483	2	0	0
T177	6342	15	0	0
T178	1739	9	0	0
T179	2286	13	0	0
T183	21923	4	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	2529	0	0
T52	3467	13	0	0
T53	3385	5	0	0
T62	3155	39	0	0
T83	2184	27	0	0
T85	4057	9	0	0
T177	6342	24	0	0
T185	3097	57	0	0
T186	3370	5	0	0
T235	7037	75	0	0
T236	6261	81	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	2561	0	0
T52	3467	2	0	0
T53	3385	5	0	0
T62	3155	114	0	0
T83	2184	13	0	0
T85	4057	41	0	0
T177	6342	33	0	0
T185	3097	59	0	0
T186	3370	5	0	0
T235	7037	40	0	0
T236	6261	15	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	3000	0	0
T52	3467	53	0	0
T53	3385	14	0	0
T62	3155	94	0	0
T83	2184	15	0	0
T177	6342	44	0	0
T185	3097	72	0	0
T186	3370	55	0	0
T235	7037	63	0	0
T236	6261	51	0	0
T237	7702	45	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	3902	0	0
T52	3467	12	0	0
T53	3385	7	0	0
T62	3155	5	0	0
T83	2184	48	0	0
T177	6342	43	0	0
T185	3097	5	0	0
T186	3370	80	0	0
T235	7037	10	0	0
T236	6261	80	0	0
T237	7702	66	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	2405	0	0
T52	3467	21	0	0
T53	3385	42	0	0
T62	3155	55	0	0
T83	2184	4	0	0
T85	4057	18	0	0
T177	6342	36	0	0
T185	3097	81	0	0
T186	3370	40	0	0
T235	7037	10	0	0
T236	6261	8	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	1639	0	0
T52	3467	15	0	0
T53	3385	23	0	0
T62	3155	44	0	0
T83	2184	13	0	0
T85	4057	20	0	0
T177	6342	39	0	0
T185	3097	37	0	0
T186	3370	47	0	0
T235	7037	44	0	0
T236	6261	35	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	2282	0	0
T52	3467	4	0	0
T53	3385	52	0	0
T62	3155	39	0	0
T83	2184	13	0	0
T85	4057	46	0	0
T177	6342	25	0	0
T185	3097	44	0	0
T186	3370	52	0	0
T235	7037	27	0	0
T236	6261	22	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	2901	0	0
T52	3467	9	0	0
T53	3385	40	0	0
T62	3155	50	0	0
T83	2184	29	0	0
T85	4057	7	0	0
T177	6342	51	0	0
T185	3097	79	0	0
T186	3370	105	0	0
T235	7037	27	0	0
T236	6261	60	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	2697	0	0
T52	3467	3	0	0
T53	3385	62	0	0
T62	3155	4	0	0
T177	6342	9	0	0
T185	3097	43	0	0
T186	3370	41	0	0
T235	7037	69	0	0
T236	6261	105	0	0
T237	7702	83	0	0
T238	4167	19	0	0