Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.91	100.00	67.63			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_rxfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.usbdev_avsetupfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.usbdev_avoutfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo	92.19	100.00	68.75			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.95	90.24	55.56			70.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.11	94.94	64.18	93.93		87.50	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.01	85.19	50.00			53.85

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.38	95.38	70.80			83.33	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	97.56	70.59			88.89	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.11	94.94	64.18	93.93		87.50	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.30	96.30	75.00			84.62

---

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	97.56	70.59			88.89	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.11	94.94	64.18	93.93		87.50	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	85.30	96.30	75.00			84.62

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.38	95.38	70.80			83.33	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.38	95.38	70.80			83.33	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.62	100.00

tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	LINE
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.75	75.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T8

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T8

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T8

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T42
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
91.07	64.29

tb.dut.usbdev_avsetupfifo

SCORE	COND
91.07	64.29

tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T41,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.usbdev_rxfifo

SCORE	COND
92.19	68.75

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T8

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
90.62	100.00

tb.dut.usbdev_rxfifo

SCORE	BRANCH
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	BRANCH
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	241726420	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1689560250	240610187	0	0
gen_passthru_fifo.paramCheckPass	5700	5700	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	241726420	0	0
T1	2416248	400730	0	0
T2	4443714	402524	0	0
T3	52476	8026	0	0
T4	4816572	28	0	0
T7	4821996	400966	0	0
T8	4821768	400154	0	0
T9	4838064	402717	0	0
T10	4866240	404886	0	0
T11	4817544	400361	0	0
T12	4816236	36	0	0
T16	0	400056	0	0
T17	0	399798	0	0
T19	2412810	401432	0	0
T27	401911	400769	0	0
T41	0	8064	0	0
T42	0	11	0	0
T45	0	5	0	0
T46	0	10	0	0
T47	0	103	0	0
T48	0	45	0	0
T49	0	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4832496	4831896	0	0
T2	4847688	4847052	0	0
T3	52476	51780	0	0
T4	4816572	4815768	0	0
T7	4821996	4821024	0	0
T8	4821768	4818720	0	0
T9	4838064	4836024	0	0
T10	4866240	4863972	0	0
T11	4817544	4816608	0	0
T12	4816236	4814004	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4832496	4831896	0	0
T2	4847688	4847052	0	0
T3	52476	51780	0	0
T4	4816572	4815768	0	0
T7	4821996	4821024	0	0
T8	4821768	4818720	0	0
T9	4838064	4836024	0	0
T10	4866240	4863972	0	0
T11	4817544	4816608	0	0
T12	4816236	4814004	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4832496	4831896	0	0
T2	4847688	4847052	0	0
T3	52476	51780	0	0
T4	4816572	4815768	0	0
T7	4821996	4821024	0	0
T8	4821768	4818720	0	0
T9	4838064	4836024	0	0
T10	4866240	4863972	0	0
T11	4817544	4816608	0	0
T12	4816236	4814004	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1689560250	240610187	0	0
T1	805416	400670	0	0
T2	2019870	402420	0	0
T3	26238	6222	0	0
T4	2408286	0	0	0
T7	2410998	400906	0	0
T8	2410884	400026	0	0
T9	2419032	402577	0	0
T10	2433120	404822	0	0
T11	2408772	400321	0	0
T12	2408118	0	0	0
T16	0	400056	0	0
T17	0	399798	0	0
T18	0	399853	0	0
T19	1608540	401432	0	0
T27	401911	400762	0	0
T41	0	8064	0	0
T42	0	7	0	0
T45	0	3	0	0
T46	0	6	0	0
T47	0	66	0	0
T48	0	27	0	0
T49	0	14	0	0
T79	0	399864	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	5700	5700	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T7	6	6	0	0
T8	6	6	0	0
T9	6	6	0	0
T10	6	6	0	0
T11	6	6	0	0
T12	6	6	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	281593375	57024	0	0
DepthKnown_A	281593375	281492723	0	0
RvalidKnown_A	281593375	281492723	0	0
WreadyKnown_A	281593375	281492723	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	281593375	57024	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	57024	0	0
T1	402708	99	0	0
T2	403974	102	0	0
T3	4373	0	0	0
T4	401381	0	0	0
T7	401833	82	0	0
T8	401814	108	0	0
T9	403172	0	0	0
T10	405520	123	0	0
T11	401462	101	0	0
T12	401353	0	0	0
T15	0	130	0	0
T22	0	102	0	0
T27	0	94	0	0
T42	0	114	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	57024	0	0
T1	402708	99	0	0
T2	403974	102	0	0
T3	4373	0	0	0
T4	401381	0	0	0
T7	401833	82	0	0
T8	401814	108	0	0
T9	403172	0	0	0
T10	405520	123	0	0
T11	401462	101	0	0
T12	401353	0	0	0
T15	0	130	0	0
T22	0	102	0	0
T27	0	94	0	0
T42	0	114	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T8

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	281593375	2656	0	0
DepthKnown_A	281593375	281492723	0	0
RvalidKnown_A	281593375	281492723	0	0
WreadyKnown_A	281593375	281492723	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	281593375	2656	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	2656	0	0
T2	403974	16	0	0
T3	4373	0	0	0
T4	401381	0	0	0
T7	401833	4	0	0
T8	401814	2	0	0
T9	403172	0	0	0
T10	405520	0	0	0
T11	401462	0	0	0
T12	401353	0	0	0
T19	402135	0	0	0
T27	0	3	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	8	0	0
T48	0	9	0	0
T49	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	2656	0	0
T2	403974	16	0	0
T3	4373	0	0	0
T4	401381	0	0	0
T7	401833	4	0	0
T8	401814	2	0	0
T9	403172	0	0	0
T10	405520	0	0	0
T11	401462	0	0	0
T12	401353	0	0	0
T19	402135	0	0	0
T27	0	3	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	8	0	0
T48	0	9	0	0
T49	0	2	0	0

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T41,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T16,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T16,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T16,T17
1	1	0	Not Covered
1	1	1	Covered	T16,T17,T18

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T16,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	281593375	20204867	0	0
DepthKnown_A	281593375	281492723	0	0
RvalidKnown_A	281593375	281492723	0	0
WreadyKnown_A	281593375	281492723	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	281593375	20204867	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	20204867	0	0
T3	4373	3336	0	0
T4	401381	0	0	0
T7	401833	0	0	0
T8	401814	0	0	0
T9	403172	0	0	0
T10	405520	0	0	0
T11	401462	0	0	0
T12	401353	0	0	0
T16	0	400056	0	0
T17	0	399798	0	0
T18	0	399853	0	0
T19	402135	0	0	0
T27	401911	0	0	0
T41	0	8064	0	0
T50	0	3959	0	0
T79	0	399864	0	0
T80	0	399886	0	0
T81	0	4983	0	0
T82	0	399863	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	20204867	0	0
T3	4373	3336	0	0
T4	401381	0	0	0
T7	401833	0	0	0
T8	401814	0	0	0
T9	403172	0	0	0
T10	405520	0	0	0
T11	401462	0	0	0
T12	401353	0	0	0
T16	0	400056	0	0
T17	0	399798	0	0
T18	0	399853	0	0
T19	402135	0	0	0
T27	401911	0	0	0
T41	0	8064	0	0
T50	0	3959	0	0
T79	0	399864	0	0
T80	0	399886	0	0
T81	0	4983	0	0
T82	0	399863	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T41,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	281593375	220334658	0	0
DepthKnown_A	281593375	281492723	0	0
RvalidKnown_A	281593375	281492723	0	0
WreadyKnown_A	281593375	281492723	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	281593375	220334658	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	220334658	0	0
T1	402708	400670	0	0
T2	403974	402372	0	0
T3	4373	2886	0	0
T4	401381	0	0	0
T7	401833	400894	0	0
T8	401814	400008	0	0
T9	403172	402577	0	0
T10	405520	404822	0	0
T11	401462	400321	0	0
T12	401353	0	0	0
T19	0	401432	0	0
T27	0	400751	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	220334658	0	0
T1	402708	400670	0	0
T2	403974	402372	0	0
T3	4373	2886	0	0
T4	401381	0	0	0
T7	401833	400894	0	0
T8	401814	400008	0	0
T9	403172	402577	0	0
T10	405520	404822	0	0
T11	401462	400321	0	0
T12	401353	0	0	0
T19	0	401432	0	0
T27	0	400751	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T8

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	281593375	5491	0	0
DepthKnown_A	281593375	281492723	0	0
RvalidKnown_A	281593375	281492723	0	0
WreadyKnown_A	281593375	281492723	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	281593375	5491	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	5491	0	0
T2	403974	16	0	0
T3	4373	0	0	0
T4	401381	0	0	0
T7	401833	4	0	0
T8	401814	8	0	0
T9	403172	0	0	0
T10	405520	0	0	0
T11	401462	0	0	0
T12	401353	0	0	0
T19	402135	0	0	0
T27	0	4	0	0
T42	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	29	0	0
T48	0	9	0	0
T49	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	5491	0	0
T2	403974	16	0	0
T3	4373	0	0	0
T4	401381	0	0	0
T7	401833	4	0	0
T8	401814	8	0	0
T9	403172	0	0	0
T10	405520	0	0	0
T11	401462	0	0	0
T12	401353	0	0	0
T19	402135	0	0	0
T27	0	4	0	0
T42	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	29	0	0
T48	0	9	0	0
T49	0	6	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T8

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T8

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T8

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T42
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	281593375	5491	0	0
DepthKnown_A	281593375	281492723	0	0
RvalidKnown_A	281593375	281492723	0	0
WreadyKnown_A	281593375	281492723	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	281593375	5491	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	5491	0	0
T2	403974	16	0	0
T3	4373	0	0	0
T4	401381	0	0	0
T7	401833	4	0	0
T8	401814	8	0	0
T9	403172	0	0	0
T10	405520	0	0	0
T11	401462	0	0	0
T12	401353	0	0	0
T19	402135	0	0	0
T27	0	4	0	0
T42	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	29	0	0
T48	0	9	0	0
T49	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	281492723	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	281593375	5491	0	0
T2	403974	16	0	0
T3	4373	0	0	0
T4	401381	0	0	0
T7	401833	4	0	0
T8	401814	8	0	0
T9	403172	0	0	0
T10	405520	0	0	0
T11	401462	0	0	0
T12	401353	0	0	0
T19	402135	0	0	0
T27	0	4	0	0
T42	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	29	0	0
T48	0	9	0	0
T49	0	6	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282411840	237227	0	0
DepthKnown_A	282411840	282279070	0	0
RvalidKnown_A	282411840	282279070	0	0
WreadyKnown_A	282411840	282279070	0	0
gen_passthru_fifo.paramCheckPass	950	950	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	237227	0	0
T1	402708	15	0	0
T2	403974	26	0	0
T3	4373	451	0	0
T4	401381	7	0	0
T7	401833	15	0	0
T8	401814	11	0	0
T9	403172	12	0	0
T10	405520	16	0	0
T11	401462	10	0	0
T12	401353	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	950	950	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282411840	326861	0	0
DepthKnown_A	282411840	282279070	0	0
RvalidKnown_A	282411840	282279070	0	0
WreadyKnown_A	282411840	282279070	0	0
gen_passthru_fifo.paramCheckPass	950	950	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	326861	0	0
T1	402708	15	0	0
T2	403974	26	0	0
T3	4373	451	0	0
T4	401381	7	0	0
T7	401833	15	0	0
T8	401814	53	0	0
T9	403172	58	0	0
T10	405520	16	0	0
T11	401462	10	0	0
T12	401353	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	950	950	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282411840	32004	0	0
DepthKnown_A	282411840	282279070	0	0
RvalidKnown_A	282411840	282279070	0	0
WreadyKnown_A	282411840	282279070	0	0
gen_passthru_fifo.paramCheckPass	950	950	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	32004	0	0
T2	403974	16	0	0
T3	4373	0	0	0
T4	401381	0	0	0
T7	401833	4	0	0
T8	401814	2	0	0
T9	403172	0	0	0
T10	405520	0	0	0
T11	401462	0	0	0
T12	401353	0	0	0
T19	402135	0	0	0
T27	0	3	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	8	0	0
T48	0	9	0	0
T49	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	950	950	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282411840	45763	0	0
DepthKnown_A	282411840	282279070	0	0
RvalidKnown_A	282411840	282279070	0	0
WreadyKnown_A	282411840	282279070	0	0
gen_passthru_fifo.paramCheckPass	950	950	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	45763	0	0
T2	403974	16	0	0
T3	4373	0	0	0
T4	401381	0	0	0
T7	401833	4	0	0
T8	401814	8	0	0
T9	403172	0	0	0
T10	405520	0	0	0
T11	401462	0	0	0
T12	401353	0	0	0
T19	402135	0	0	0
T27	0	4	0	0
T42	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	29	0	0
T48	0	9	0	0
T49	0	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	950	950	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282411840	193280	0	0
DepthKnown_A	282411840	282279070	0	0
RvalidKnown_A	282411840	282279070	0	0
WreadyKnown_A	282411840	282279070	0	0
gen_passthru_fifo.paramCheckPass	950	950	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	193280	0	0
T1	402708	15	0	0
T2	403974	10	0	0
T3	4373	451	0	0
T4	401381	7	0	0
T7	401833	11	0	0
T8	401814	9	0	0
T9	403172	12	0	0
T10	405520	16	0	0
T11	401462	10	0	0
T12	401353	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	950	950	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	282411840	281098	0	0
DepthKnown_A	282411840	282279070	0	0
RvalidKnown_A	282411840	282279070	0	0
WreadyKnown_A	282411840	282279070	0	0
gen_passthru_fifo.paramCheckPass	950	950	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	281098	0	0
T1	402708	15	0	0
T2	403974	10	0	0
T3	4373	451	0	0
T4	401381	7	0	0
T7	401833	11	0	0
T8	401814	45	0	0
T9	403172	58	0	0
T10	405520	16	0	0
T11	401462	10	0	0
T12	401353	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	282411840	282279070	0	0
T1	402708	402658	0	0
T2	403974	403921	0	0
T3	4373	4315	0	0
T4	401381	401314	0	0
T7	401833	401752	0	0
T8	401814	401560	0	0
T9	403172	403002	0	0
T10	405520	405331	0	0
T11	401462	401384	0	0
T12	401353	401167	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	950	950	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0