Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	247997	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	447715	1		T1	5		T2	5		T3	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	435682	1		T1	4		T2	7		T3	5
values[0x0]	129619	1		T1	2		T2	2		T3	3
values[0x1]	130411	1		T1	6		T2	4		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	188143	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	507569	1		T1	8		T2	7		T3	9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2287	1		T17	1		T45	1		T30	1
valid_sources[0x01]	2251	1		T42	2		T12	33		T58	1
valid_sources[0x02]	2551	1		T17	2		T44	1		T93	1
valid_sources[0x03]	2844	1		T2	1		T3	14		T17	4
valid_sources[0x04]	2982	1		T17	4		T43	1		T12	39
valid_sources[0x05]	2887	1		T2	1		T17	5		T293	4
valid_sources[0x06]	2532	1		T17	2		T93	1		T30	1
valid_sources[0x07]	2463	1		T17	2		T36	2		T12	18
valid_sources[0x08]	5703	1		T17	6		T294	1		T12	68
valid_sources[0x09]	2312	1		T17	3		T42	1		T12	46
valid_sources[0x0a]	2363	1		T17	6		T30	1		T4	7
valid_sources[0x0b]	2815	1		T17	4		T90	14		T30	2
valid_sources[0x0c]	2373	1		T17	5		T93	1		T30	1
valid_sources[0x0d]	2318	1		T17	2		T94	1		T5	1
valid_sources[0x0e]	2862	1		T17	2		T42	1		T12	22
valid_sources[0x0f]	2238	1		T17	4		T43	1		T12	38
valid_sources[0x10]	2412	1		T17	2		T12	54		T58	2
valid_sources[0x11]	2292	1		T17	2		T12	43		T58	3
valid_sources[0x12]	3127	1		T17	2		T233	1		T55	1
valid_sources[0x13]	2270	1		T17	5		T30	1		T12	40
valid_sources[0x14]	2323	1		T17	1		T12	44		T32	1
valid_sources[0x15]	2125	1		T17	5		T294	1		T12	36
valid_sources[0x16]	2331	1		T22	1		T12	44		T160	1
valid_sources[0x17]	2543	1		T17	3		T99	3		T12	39
valid_sources[0x18]	3868	1		T17	1		T12	26		T13	43
valid_sources[0x19]	3460	1		T17	2		T30	1		T295	4
valid_sources[0x1a]	2887	1		T17	1		T43	1		T12	42
valid_sources[0x1b]	2628	1		T17	1		T43	2		T12	36
valid_sources[0x1c]	2033	1		T17	6		T42	1		T12	36
valid_sources[0x1d]	2445	1		T17	1		T12	42		T147	1
valid_sources[0x1e]	5336	1		T2	1		T17	8		T296	1
valid_sources[0x1f]	2711	1		T17	2		T12	32		T270	3
valid_sources[0x20]	2430	1		T17	1		T12	22		T58	6
valid_sources[0x21]	2255	1		T34	1		T12	56		T297	1
valid_sources[0x22]	2674	1		T233	3		T12	43		T58	2
valid_sources[0x23]	3020	1		T17	1		T22	2		T30	2
valid_sources[0x24]	3626	1		T17	1		T22	1		T94	1
valid_sources[0x25]	2240	1		T17	6		T21	1		T99	1
valid_sources[0x26]	2640	1		T17	6		T298	1		T42	2
valid_sources[0x27]	2733	1		T17	5		T43	1		T12	49
valid_sources[0x28]	3051	1		T17	4		T44	1		T12	31
valid_sources[0x29]	3262	1		T17	1		T12	40		T58	2
valid_sources[0x2a]	2378	1		T17	1		T12	42		T58	2
valid_sources[0x2b]	2687	1		T17	3		T12	31		T32	1
valid_sources[0x2c]	2086	1		T17	8		T233	1		T43	2
valid_sources[0x2d]	6318	1		T17	2		T93	1		T12	53
valid_sources[0x2e]	2891	1		T17	1		T94	1		T30	1
valid_sources[0x2f]	2805	1		T17	2		T22	1		T24	1
valid_sources[0x30]	2997	1		T17	2		T20	4		T21	1
valid_sources[0x31]	6929	1		T17	4		T94	1		T233	4
valid_sources[0x32]	2900	1		T22	3		T93	1		T12	57
valid_sources[0x33]	2730	1		T44	2		T43	1		T12	52
valid_sources[0x34]	2875	1		T17	1		T43	1		T12	35
valid_sources[0x35]	3641	1		T17	2		T12	17		T58	1
valid_sources[0x36]	2104	1		T17	3		T94	1		T43	1
valid_sources[0x37]	2211	1		T17	4		T12	27		T232	3
valid_sources[0x38]	2449	1		T17	1		T19	1		T12	79
valid_sources[0x39]	2951	1		T17	4		T21	1		T12	22
valid_sources[0x3a]	2658	1		T17	3		T30	5		T12	47
valid_sources[0x3b]	2358	1		T12	31		T58	8		T232	5
valid_sources[0x3c]	2464	1		T17	1		T21	1		T92	3
valid_sources[0x3d]	2068	1		T17	3		T22	1		T34	1
valid_sources[0x3e]	2407	1		T17	2		T30	1		T12	48
valid_sources[0x3f]	3832	1		T17	2		T12	84		T232	14
valid_sources[0x40]	2151	1		T2	1		T17	3		T94	1
valid_sources[0x41]	2439	1		T17	4		T56	1		T12	26
valid_sources[0x42]	5354	1		T17	2		T12	40		T271	1
valid_sources[0x43]	3456	1		T17	3		T12	61		T58	4
valid_sources[0x44]	2803	1		T17	1		T21	1		T33	1
valid_sources[0x45]	2330	1		T17	2		T12	65		T58	5
valid_sources[0x46]	2590	1		T30	1		T56	2		T12	46
valid_sources[0x47]	2280	1		T34	1		T12	16		T58	2
valid_sources[0x48]	2238	1		T17	1		T30	1		T12	53
valid_sources[0x49]	2514	1		T17	1		T93	1		T12	65
valid_sources[0x4a]	2211	1		T17	3		T43	1		T12	33
valid_sources[0x4b]	2493	1		T17	8		T31	9		T12	41
valid_sources[0x4c]	2706	1		T17	2		T36	1		T34	1
valid_sources[0x4d]	2192	1		T17	3		T294	1		T12	36
valid_sources[0x4e]	2578	1		T17	4		T233	1		T294	1
valid_sources[0x4f]	2330	1		T17	1		T22	1		T99	1
valid_sources[0x50]	2278	1		T17	3		T44	1		T12	49
valid_sources[0x51]	2775	1		T17	2		T12	23		T59	7
valid_sources[0x52]	2316	1		T17	2		T12	21		T59	3
valid_sources[0x53]	2577	1		T17	3		T22	1		T34	1
valid_sources[0x54]	2723	1		T17	1		T19	1		T12	78
valid_sources[0x55]	2078	1		T12	25		T58	1		T232	7
valid_sources[0x56]	2238	1		T17	1		T43	1		T12	51
valid_sources[0x57]	2785	1		T17	3		T30	1		T295	6
valid_sources[0x58]	2211	1		T17	3		T296	1		T43	1
valid_sources[0x59]	6357	1		T17	2		T94	1		T42	1
valid_sources[0x5a]	2846	1		T17	3		T43	1		T12	40
valid_sources[0x5b]	2353	1		T19	1		T22	1		T94	2
valid_sources[0x5c]	3545	1		T17	3		T12	40		T59	26
valid_sources[0x5d]	2057	1		T17	3		T293	3		T12	25
valid_sources[0x5e]	2830	1		T17	5		T36	1		T12	52
valid_sources[0x5f]	2442	1		T12	41		T58	7		T147	1
valid_sources[0x60]	2357	1		T17	1		T19	1		T12	18
valid_sources[0x61]	2081	1		T17	4		T42	1		T12	43
valid_sources[0x62]	2424	1		T17	6		T44	1		T30	1
valid_sources[0x63]	2109	1		T12	58		T58	3		T299	1
valid_sources[0x64]	2900	1		T17	3		T92	2		T30	1
valid_sources[0x65]	2695	1		T294	1		T12	29		T13	56
valid_sources[0x66]	2216	1		T17	11		T12	42		T232	11
valid_sources[0x67]	2561	1		T2	1		T17	4		T42	1
valid_sources[0x68]	2154	1		T17	3		T93	1		T12	25
valid_sources[0x69]	2486	1		T17	2		T12	50		T58	1
valid_sources[0x6a]	2179	1		T17	2		T12	21		T271	1
valid_sources[0x6b]	2591	1		T17	1		T16	2		T24	1
valid_sources[0x6c]	2451	1		T17	1		T92	5		T12	71
valid_sources[0x6d]	2642	1		T17	3		T22	5		T12	87
valid_sources[0x6e]	2244	1		T233	1		T12	70		T58	3
valid_sources[0x6f]	2433	1		T17	1		T16	1		T91	20
valid_sources[0x70]	2630	1		T22	1		T12	21		T97	2
valid_sources[0x71]	2538	1		T17	2		T43	2		T12	53
valid_sources[0x72]	2192	1		T296	1		T12	105		T58	4
valid_sources[0x73]	2004	1		T17	6		T30	1		T43	1
valid_sources[0x74]	5493	1		T17	4		T12	32		T58	8
valid_sources[0x75]	2611	1		T30	1		T12	52		T58	1
valid_sources[0x76]	2194	1		T16	1		T34	1		T12	28
valid_sources[0x77]	2478	1		T2	1		T17	2		T30	1
valid_sources[0x78]	2290	1		T17	4		T34	1		T12	19
valid_sources[0x79]	3140	1		T17	1		T22	1		T12	62
valid_sources[0x7a]	2349	1		T17	2		T12	69		T13	50
valid_sources[0x7b]	2583	1		T17	7		T233	1		T12	41
valid_sources[0x7c]	2116	1		T17	1		T99	1		T293	5
valid_sources[0x7d]	2245	1		T20	4		T33	2		T36	1
valid_sources[0x7e]	3195	1		T17	1		T16	1		T12	61
valid_sources[0x7f]	2551	1		T12	30		T297	1		T232	3
valid_sources[0x80]	3328	1		T17	2		T12	54		T13	46

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

233843

1

T1

3

T2

4

T3

2

values[0x0]

all_enables

biggest_size

110199

1

T1

2

T3

2

T17

73

values[0x1]

all_enables

biggest_size

103673

1

T2

1

T3

1

T17

46