Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.73	94.94	67.16	94.86		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	396763763	12162	0	0
ep_in_enable_rd_A	396763763	2521	0	0
ep_out_enable_rd_A	396763763	2318	0	0
in_iso_rd_A	396763763	2521	0	0
intr_enable_rd_A	396763763	3706	0	0
out_iso_rd_A	396763763	1955	0	0
phy_config_rd_A	396763763	1509	0	0
phy_pins_drive_rd_A	396763763	1808	0	0
rxenable_setup_rd_A	396763763	2486	0	0
set_nak_out_rd_A	396763763	2249	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396763763	12162	0	0
T60	22988	6	0	0
T61	6654	329	0	0
T62	15657	791	0	0
T227	8667	554	0	0
T230	12188	2	0	0
T231	23917	6	0	0
T240	10432	828	0	0
T241	3998	611	0	0
T244	11265	4	0	0
T245	6806	338	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396763763	2521	0	0
T60	22988	221	0	0
T106	3726	5	0	0
T107	1814	2	0	0
T230	12188	289	0	0
T231	23917	249	0	0
T259	3092	10	0	0
T261	17824	183	0	0
T262	2086	28	0	0
T272	1910	18	0	0
T273	2209	5	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396763763	2318	0	0
T60	22988	278	0	0
T106	3726	14	0	0
T107	1814	4	0	0
T230	12188	205	0	0
T231	23917	297	0	0
T245	6806	5	0	0
T247	3944	40	0	0
T259	3092	5	0	0
T261	17824	175	0	0
T273	2209	55	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396763763	2521	0	0
T60	22988	290	0	0
T67	2694	7	0	0
T107	1814	45	0	0
T230	12188	229	0	0
T231	23917	262	0	0
T247	3944	7	0	0
T259	3092	54	0	0
T261	17824	191	0	0
T273	2209	2	0	0
T274	6655	47	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396763763	3706	0	0
T60	22988	374	0	0
T78	1351	7	0	0
T106	3726	7	0	0
T107	1814	4	0	0
T230	12188	349	0	0
T231	23917	237	0	0
T259	3092	138	0	0
T261	17824	184	0	0
T272	1910	32	0	0
T275	1310	5	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396763763	1955	0	0
T60	22988	170	0	0
T62	15657	1	0	0
T106	3726	8	0	0
T107	1814	3	0	0
T230	12188	188	0	0
T231	23917	263	0	0
T259	3092	77	0	0
T261	17824	173	0	0
T262	2086	30	0	0
T272	1910	4	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396763763	1509	0	0
T60	22988	140	0	0
T106	3726	6	0	0
T107	1814	34	0	0
T230	12188	135	0	0
T231	23917	215	0	0
T259	3092	46	0	0
T261	17824	197	0	0
T262	2086	15	0	0
T272	1910	14	0	0
T273	2209	20	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396763763	1808	0	0
T60	22988	121	0	0
T106	3726	7	0	0
T107	1814	37	0	0
T230	12188	157	0	0
T231	23917	236	0	0
T247	3944	26	0	0
T259	3092	71	0	0
T261	17824	157	0	0
T272	1910	19	0	0
T273	2209	33	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396763763	2486	0	0
T60	22988	197	0	0
T106	3726	15	0	0
T107	1814	9	0	0
T230	12188	168	0	0
T231	23917	259	0	0
T247	3944	5	0	0
T259	3092	46	0	0
T261	17824	203	0	0
T272	1910	6	0	0
T273	2209	42	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396763763	2249	0	0
T60	22988	163	0	0
T106	3726	36	0	0
T107	1814	40	0	0
T230	12188	159	0	0
T231	23917	248	0	0
T259	3092	5	0	0
T261	17824	172	0	0
T262	2086	40	0	0
T272	1910	1	0	0
T273	2209	2	0	0