Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	248313	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	456362	1		T1	7		T2	8		T3	8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	441178	1		T1	6		T2	7		T3	7
values[0x0]	131311	1		T1	5		T2	5		T3	2
values[0x1]	132186	1		T1	4		T2	1		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	188312	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	516363	1		T1	10		T2	10		T3	10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2891	1		T22	1		T52	3		T42	1
valid_sources[0x01]	3189	1		T22	1		T52	4		T11	45
valid_sources[0x02]	2551	1		T22	1		T15	1		T11	61
valid_sources[0x03]	2226	1		T22	2		T11	54		T12	30
valid_sources[0x04]	2570	1		T22	3		T52	1		T11	57
valid_sources[0x05]	5500	1		T22	2		T52	6		T16	1
valid_sources[0x06]	5271	1		T1	1		T22	4		T15	1
valid_sources[0x07]	2519	1		T18	1		T22	3		T11	49
valid_sources[0x08]	2830	1		T52	4		T11	42		T12	36
valid_sources[0x09]	2247	1		T22	1		T52	3		T11	32
valid_sources[0x0a]	2585	1		T52	1		T11	57		T12	38
valid_sources[0x0b]	3260	1		T22	1		T52	5		T11	56
valid_sources[0x0c]	3369	1		T22	2		T52	5		T11	50
valid_sources[0x0d]	2717	1		T22	3		T52	5		T11	50
valid_sources[0x0e]	2394	1		T22	1		T11	54		T12	38
valid_sources[0x0f]	2532	1		T22	1		T52	2		T11	51
valid_sources[0x10]	2621	1		T22	4		T52	1		T34	1
valid_sources[0x11]	2421	1		T18	1		T22	1		T52	10
valid_sources[0x12]	2299	1		T22	5		T52	4		T11	54
valid_sources[0x13]	2386	1		T22	2		T15	1		T52	9
valid_sources[0x14]	3152	1		T22	2		T52	1		T89	1
valid_sources[0x15]	2414	1		T22	4		T52	3		T41	1
valid_sources[0x16]	3599	1		T22	5		T52	3		T92	1
valid_sources[0x17]	3309	1		T22	3		T52	1		T11	46
valid_sources[0x18]	2177	1		T22	1		T52	11		T11	46
valid_sources[0x19]	2235	1		T22	9		T52	11		T11	62
valid_sources[0x1a]	2655	1		T22	3		T52	5		T11	40
valid_sources[0x1b]	2996	1		T52	5		T11	40		T12	32
valid_sources[0x1c]	2852	1		T52	8		T91	1		T11	43
valid_sources[0x1d]	2342	1		T18	1		T22	3		T15	1
valid_sources[0x1e]	2374	1		T52	6		T11	40		T12	35
valid_sources[0x1f]	2164	1		T22	4		T34	1		T24	5
valid_sources[0x20]	3145	1		T22	1		T52	4		T11	46
valid_sources[0x21]	2399	1		T22	1		T52	5		T91	1
valid_sources[0x22]	2216	1		T18	1		T22	3		T52	14
valid_sources[0x23]	2202	1		T22	1		T52	3		T11	43
valid_sources[0x24]	2522	1		T22	5		T52	8		T42	1
valid_sources[0x25]	5522	1		T22	3		T52	2		T41	1
valid_sources[0x26]	2563	1		T22	5		T52	1		T89	1
valid_sources[0x27]	2237	1		T22	4		T52	9		T89	1
valid_sources[0x28]	2230	1		T52	3		T11	46		T30	1
valid_sources[0x29]	2600	1		T22	1		T52	1		T42	1
valid_sources[0x2a]	2137	1		T22	1		T52	21		T11	45
valid_sources[0x2b]	2496	1		T22	1		T52	6		T16	1
valid_sources[0x2c]	2605	1		T22	2		T52	5		T11	62
valid_sources[0x2d]	2651	1		T22	2		T52	2		T11	56
valid_sources[0x2e]	3060	1		T1	2		T52	13		T16	3
valid_sources[0x2f]	2435	1		T2	13		T22	4		T52	10
valid_sources[0x30]	2604	1		T22	1		T52	6		T23	5
valid_sources[0x31]	2343	1		T22	1		T92	1		T11	56
valid_sources[0x32]	2247	1		T52	5		T11	45		T30	2
valid_sources[0x33]	2515	1		T52	14		T11	46		T12	46
valid_sources[0x34]	5716	1		T52	4		T11	43		T12	33
valid_sources[0x35]	2725	1		T22	2		T52	1		T41	1
valid_sources[0x36]	3625	1		T22	2		T52	2		T11	50
valid_sources[0x37]	2501	1		T22	1		T52	3		T91	2
valid_sources[0x38]	2369	1		T22	2		T52	3		T11	52
valid_sources[0x39]	2501	1		T22	2		T52	8		T34	1
valid_sources[0x3a]	2904	1		T22	2		T52	3		T91	1
valid_sources[0x3b]	2416	1		T22	2		T52	16		T89	1
valid_sources[0x3c]	2959	1		T52	1		T11	51		T262	1
valid_sources[0x3d]	2605	1		T22	1		T52	3		T11	47
valid_sources[0x3e]	2321	1		T22	2		T15	1		T52	23
valid_sources[0x3f]	2819	1		T22	3		T52	8		T23	2
valid_sources[0x40]	2582	1		T22	3		T52	2		T155	2
valid_sources[0x41]	3058	1		T52	4		T11	43		T12	36
valid_sources[0x42]	2203	1		T22	5		T52	7		T11	51
valid_sources[0x43]	2223	1		T22	2		T52	8		T11	50
valid_sources[0x44]	2691	1		T22	1		T52	4		T11	68
valid_sources[0x45]	2204	1		T52	7		T11	41		T12	33
valid_sources[0x46]	2980	1		T22	1		T52	6		T237	1
valid_sources[0x47]	2452	1		T22	5		T90	3		T11	54
valid_sources[0x48]	3285	1		T22	1		T52	1		T42	1
valid_sources[0x49]	3041	1		T22	1		T52	2		T11	50
valid_sources[0x4a]	2417	1		T52	9		T11	44		T12	32
valid_sources[0x4b]	2186	1		T22	2		T52	7		T11	51
valid_sources[0x4c]	2350	1		T22	8		T52	11		T11	49
valid_sources[0x4d]	2378	1		T22	2		T52	7		T11	49
valid_sources[0x4e]	4377	1		T22	2		T52	4		T155	8
valid_sources[0x4f]	2498	1		T22	1		T41	1		T11	48
valid_sources[0x50]	2385	1		T22	1		T52	2		T237	1
valid_sources[0x51]	2374	1		T1	1		T22	5		T52	3
valid_sources[0x52]	2669	1		T18	1		T22	10		T52	4
valid_sources[0x53]	2629	1		T22	2		T52	1		T91	1
valid_sources[0x54]	2442	1		T22	5		T52	6		T11	41
valid_sources[0x55]	3474	1		T22	2		T52	7		T11	40
valid_sources[0x56]	2850	1		T22	3		T52	4		T91	1
valid_sources[0x57]	2795	1		T22	2		T52	18		T11	37
valid_sources[0x58]	2527	1		T18	1		T22	2		T52	1
valid_sources[0x59]	2329	1		T22	7		T52	1		T11	39
valid_sources[0x5a]	3711	1		T22	3		T52	8		T34	1
valid_sources[0x5b]	2628	1		T22	3		T15	1		T52	5
valid_sources[0x5c]	2673	1		T22	1		T52	3		T11	50
valid_sources[0x5d]	2838	1		T22	1		T52	10		T293	4
valid_sources[0x5e]	3002	1		T22	6		T52	3		T11	50
valid_sources[0x5f]	3404	1		T22	3		T52	4		T36	4
valid_sources[0x60]	2297	1		T22	1		T52	7		T37	1
valid_sources[0x61]	2615	1		T20	15		T22	2		T52	1
valid_sources[0x62]	2672	1		T22	2		T52	5		T11	49
valid_sources[0x63]	2716	1		T11	55		T261	1		T12	30
valid_sources[0x64]	2260	1		T18	1		T22	1		T52	2
valid_sources[0x65]	2562	1		T22	2		T52	3		T11	45
valid_sources[0x66]	2424	1		T22	5		T52	3		T34	1
valid_sources[0x67]	2581	1		T22	2		T11	45		T261	1
valid_sources[0x68]	2457	1		T22	3		T52	10		T16	1
valid_sources[0x69]	2577	1		T52	3		T41	1		T11	56
valid_sources[0x6a]	2440	1		T22	5		T52	4		T11	41
valid_sources[0x6b]	2606	1		T22	6		T52	2		T36	1
valid_sources[0x6c]	2659	1		T22	2		T52	2		T11	41
valid_sources[0x6d]	2526	1		T22	6		T52	2		T41	1
valid_sources[0x6e]	2660	1		T1	1		T22	5		T52	5
valid_sources[0x6f]	2333	1		T14	10		T22	4		T52	9
valid_sources[0x70]	2652	1		T22	7		T52	2		T92	1
valid_sources[0x71]	2693	1		T22	5		T52	6		T34	1
valid_sources[0x72]	2335	1		T22	2		T52	5		T91	1
valid_sources[0x73]	2086	1		T22	3		T52	9		T11	43
valid_sources[0x74]	2559	1		T1	1		T22	1		T52	5
valid_sources[0x75]	2496	1		T22	7		T52	1		T11	52
valid_sources[0x76]	2123	1		T22	8		T52	3		T11	52
valid_sources[0x77]	5551	1		T22	7		T52	2		T11	54
valid_sources[0x78]	3228	1		T22	5		T52	9		T42	1
valid_sources[0x79]	7099	1		T22	3		T52	6		T155	1
valid_sources[0x7a]	3260	1		T22	3		T52	3		T34	1
valid_sources[0x7b]	2493	1		T11	52		T12	34		T53	3
valid_sources[0x7c]	2133	1		T22	1		T52	12		T34	1
valid_sources[0x7d]	3523	1		T22	3		T34	1		T11	36
valid_sources[0x7e]	2599	1		T18	1		T22	4		T52	2
valid_sources[0x7f]	2233	1		T22	4		T52	5		T16	1
valid_sources[0x80]	6296	1		T22	6		T11	59		T262	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

238761

1

T1

2

T2

5

T3

6

values[0x0]

all_enables

biggest_size

111907

1

T1

5

T2

3

T3

1

values[0x1]

all_enables

biggest_size

105694

1

T3

1

T17

2

T18

2