Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	262270	1		T1	8		T2	5		T3	4
full_word	457367	1		T1	7		T2	8		T3	8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	719417	1		T1	15		T2	13		T3	12
auto[TlIntgErrCmd]	78	1		T55	2		T67	3		T103	10
auto[TlIntgErrData]	71	1		T55	4		T67	4		T103	7
auto[TlIntgErrBoth]	71	1		T55	4		T67	3		T103	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	443122	1		T1	6		T2	7		T3	7
auto[1]	276515	1		T1	9		T2	6		T3	5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	204093	1		T1	4		T2	2		T3	1
auto[TlIntgErrNone]	partial	auto[1]	57978	1		T1	4		T2	3		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	238932	1		T1	2		T2	5		T3	6
auto[TlIntgErrNone]	full_word	auto[1]	218414	1		T1	5		T2	3		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	34	1		T67	2		T103	3		T241	1
auto[TlIntgErrCmd]	partial	auto[1]	38	1		T55	2		T67	1		T103	7
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T236	1		T286	1		T287	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T236	2		T285	1		-	-
auto[TlIntgErrData]	partial	auto[0]	31	1		T55	3		T103	4		T241	1
auto[TlIntgErrData]	partial	auto[1]	33	1		T55	1		T67	4		T103	3
auto[TlIntgErrData]	full_word	auto[0]	1	1		T286	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1		T241	1		T239	1		T288	1
auto[TlIntgErrBoth]	partial	auto[0]	25	1		T67	2		T239	5		T289	1
auto[TlIntgErrBoth]	partial	auto[1]	38	1		T55	4		T67	1		T103	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T289	1		T236	1		T290	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T291	1		T288	1		T292	1