Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.73	94.94	67.16	94.86		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	398730682	11404	0	0
ep_in_enable_rd_A	398730682	1717	0	0
ep_out_enable_rd_A	398730682	1428	0	0
in_iso_rd_A	398730682	1845	0	0
intr_enable_rd_A	398730682	2319	0	0
out_iso_rd_A	398730682	1491	0	0
phy_config_rd_A	398730682	1242	0	0
phy_pins_drive_rd_A	398730682	1360	0	0
rxenable_setup_rd_A	398730682	1963	0	0
set_nak_out_rd_A	398730682	1593	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398730682	11404	0	0
T54	10996	732	0	0
T55	11821	2	0	0
T56	2415	13	0	0
T67	14981	6	0	0
T103	20615	3	0	0
T222	2925	345	0	0
T226	10335	887	0	0
T238	2640	8	0	0
T239	21483	6	0	0
T241	13246	5	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398730682	1717	0	0
T65	1957	5	0	0
T67	14981	369	0	0
T104	9359	83	0	0
T241	13246	227	0	0
T249	2841	47	0	0
T265	6317	41	0	0
T266	7166	68	0	0
T267	7212	57	0	0
T268	8388	51	0	0
T269	6438	112	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398730682	1428	0	0
T67	14981	170	0	0
T104	9359	85	0	0
T241	13246	356	0	0
T249	2841	33	0	0
T250	2114	3	0	0
T265	6317	39	0	0
T266	7166	18	0	0
T267	7212	15	0	0
T268	8388	33	0	0
T269	6438	9	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398730682	1845	0	0
T65	1957	6	0	0
T67	14981	326	0	0
T104	9359	104	0	0
T241	13246	202	0	0
T249	2841	61	0	0
T250	2114	61	0	0
T265	6317	87	0	0
T266	7166	74	0	0
T267	7212	70	0	0
T268	8388	64	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398730682	2319	0	0
T65	1957	32	0	0
T67	14981	397	0	0
T72	1126	15	0	0
T75	1297	22	0	0
T104	9359	108	0	0
T241	13246	443	0	0
T249	2841	5	0	0
T265	6317	130	0	0
T266	7166	52	0	0
T270	1203	6	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398730682	1491	0	0
T54	10996	1	0	0
T67	14981	209	0	0
T104	9359	77	0	0
T241	13246	209	0	0
T249	2841	57	0	0
T250	2114	9	0	0
T265	6317	47	0	0
T266	7166	52	0	0
T267	7212	90	0	0
T268	8388	39	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398730682	1242	0	0
T65	1957	26	0	0
T67	14981	188	0	0
T104	9359	114	0	0
T241	13246	114	0	0
T249	2841	37	0	0
T250	2114	8	0	0
T265	6317	58	0	0
T266	7166	82	0	0
T267	7212	31	0	0
T268	8388	52	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398730682	1360	0	0
T67	14981	127	0	0
T104	9359	95	0	0
T241	13246	230	0	0
T249	2841	10	0	0
T265	6317	47	0	0
T266	7166	53	0	0
T267	7212	1	0	0
T268	8388	36	0	0
T269	6438	70	0	0
T271	7334	108	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398730682	1963	0	0
T65	1957	9	0	0
T67	14981	313	0	0
T104	9359	87	0	0
T241	13246	279	0	0
T249	2841	38	0	0
T250	2114	35	0	0
T265	6317	61	0	0
T266	7166	42	0	0
T267	7212	51	0	0
T268	8388	59	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398730682	1593	0	0
T65	1957	38	0	0
T67	14981	277	0	0
T104	9359	110	0	0
T241	13246	154	0	0
T249	2841	5	0	0
T265	6317	15	0	0
T266	7166	36	0	0
T267	7212	23	0	0
T268	8388	74	0	0
T269	6438	56	0	0