Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	313757	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	535890	1		T1	6		T2	6		T3	7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	569692	1		T1	4		T2	3		T3	4
values[0x0]	139227	1		T1	5		T2	3		T3	5
values[0x1]	140728	1		T1	2		T2	4		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	240350	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	609297	1		T1	6		T2	7		T3	9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2724	1		T11	4		T12	35		T13	36
valid_sources[0x01]	2844	1		T11	143		T12	4		T13	42
valid_sources[0x02]	2684	1		T11	4		T12	5		T13	38
valid_sources[0x03]	3090	1		T12	170		T13	38		T52	9
valid_sources[0x04]	2743	1		T19	1		T48	1		T12	2
valid_sources[0x05]	2785	1		T11	3		T12	5		T13	41
valid_sources[0x06]	3975	1		T2	1		T11	4		T13	48
valid_sources[0x07]	2916	1		T11	1		T32	1		T12	5
valid_sources[0x08]	2564	1		T11	3		T12	1		T71	1
valid_sources[0x09]	2831	1		T3	3		T11	1		T12	2
valid_sources[0x0a]	2709	1		T19	2		T11	4		T12	3
valid_sources[0x0b]	3623	1		T19	1		T15	1		T11	1
valid_sources[0x0c]	3226	1		T11	5		T12	18		T13	32
valid_sources[0x0d]	2765	1		T11	1		T12	1		T46	2
valid_sources[0x0e]	2918	1		T19	1		T11	3		T276	3
valid_sources[0x0f]	3260	1		T11	4		T13	22		T122	1
valid_sources[0x10]	3566	1		T19	1		T11	2		T12	6
valid_sources[0x11]	3020	1		T11	2		T12	4		T13	30
valid_sources[0x12]	2876	1		T11	1		T12	2		T13	46
valid_sources[0x13]	3041	1		T11	2		T12	3		T13	43
valid_sources[0x14]	3326	1		T12	130		T13	43		T52	5
valid_sources[0x15]	3130	1		T40	1		T11	2		T12	2
valid_sources[0x16]	3261	1		T11	6		T12	3		T13	47
valid_sources[0x17]	3341	1		T12	2		T13	44		T277	1
valid_sources[0x18]	4089	1		T11	1		T12	143		T13	41
valid_sources[0x19]	4239	1		T36	32		T11	4		T12	182
valid_sources[0x1a]	3254	1		T11	87		T48	1		T12	1
valid_sources[0x1b]	2680	1		T11	4		T12	6		T13	39
valid_sources[0x1c]	3245	1		T11	1		T12	7		T13	51
valid_sources[0x1d]	2722	1		T11	4		T12	1		T13	47
valid_sources[0x1e]	3168	1		T11	4		T12	5		T13	39
valid_sources[0x1f]	3616	1		T11	6		T12	430		T13	64
valid_sources[0x20]	2982	1		T12	4		T13	47		T75	1
valid_sources[0x21]	2678	1		T11	1		T13	36		T278	1
valid_sources[0x22]	3207	1		T11	1		T12	2		T13	37
valid_sources[0x23]	3708	1		T19	1		T11	3		T12	5
valid_sources[0x24]	3171	1		T14	2		T11	1		T12	125
valid_sources[0x25]	3303	1		T11	3		T13	48		T52	12
valid_sources[0x26]	3494	1		T19	1		T12	1		T13	45
valid_sources[0x27]	3317	1		T40	1		T11	1		T12	82
valid_sources[0x28]	2825	1		T19	1		T7	2		T11	3
valid_sources[0x29]	2708	1		T19	1		T11	3		T13	46
valid_sources[0x2a]	3147	1		T11	241		T12	1		T13	49
valid_sources[0x2b]	2978	1		T40	1		T11	1		T12	239
valid_sources[0x2c]	2871	1		T11	5		T12	50		T13	55
valid_sources[0x2d]	4001	1		T11	1		T12	4		T13	54
valid_sources[0x2e]	2975	1		T11	4		T12	2		T13	29
valid_sources[0x2f]	2721	1		T12	5		T13	38		T277	1
valid_sources[0x30]	2987	1		T32	1		T12	6		T13	48
valid_sources[0x31]	3037	1		T13	44		T52	12		T31	1
valid_sources[0x32]	3009	1		T19	1		T15	1		T26	2
valid_sources[0x33]	2724	1		T4	3		T11	1		T12	2
valid_sources[0x34]	2774	1		T4	2		T12	34		T13	55
valid_sources[0x35]	2836	1		T11	4		T12	12		T13	35
valid_sources[0x36]	3221	1		T11	1		T12	1		T13	41
valid_sources[0x37]	2747	1		T35	1		T11	6		T32	1
valid_sources[0x38]	3137	1		T11	3		T12	2		T13	44
valid_sources[0x39]	3210	1		T40	1		T11	2		T29	12
valid_sources[0x3a]	2761	1		T11	2		T13	44		T52	13
valid_sources[0x3b]	3235	1		T11	146		T12	8		T13	49
valid_sources[0x3c]	3382	1		T40	1		T11	1		T12	4
valid_sources[0x3d]	2685	1		T15	1		T11	1		T12	3
valid_sources[0x3e]	3046	1		T11	1		T12	1		T13	41
valid_sources[0x3f]	2761	1		T2	2		T26	3		T40	2
valid_sources[0x40]	3855	1		T4	1		T11	4		T12	2
valid_sources[0x41]	3595	1		T11	1		T12	255		T13	32
valid_sources[0x42]	2834	1		T11	1		T12	2		T13	50
valid_sources[0x43]	2653	1		T19	1		T11	4		T12	1
valid_sources[0x44]	2757	1		T3	1		T19	1		T40	1
valid_sources[0x45]	2905	1		T26	2		T11	3		T13	43
valid_sources[0x46]	4533	1		T40	1		T11	138		T12	133
valid_sources[0x47]	2499	1		T11	3		T39	2		T12	2
valid_sources[0x48]	3411	1		T19	1		T7	1		T11	5
valid_sources[0x49]	3414	1		T19	1		T11	4		T32	1
valid_sources[0x4a]	2963	1		T3	1		T11	4		T37	1
valid_sources[0x4b]	3222	1		T11	4		T32	2		T12	1
valid_sources[0x4c]	3136	1		T19	1		T11	2		T13	42
valid_sources[0x4d]	6257	1		T11	2		T12	6		T13	43
valid_sources[0x4e]	3399	1		T19	1		T11	1		T12	4
valid_sources[0x4f]	2818	1		T11	2		T12	4		T13	43
valid_sources[0x50]	3289	1		T14	1		T11	472		T12	51
valid_sources[0x51]	3978	1		T11	230		T13	38		T50	1
valid_sources[0x52]	3116	1		T11	1		T9	8		T12	3
valid_sources[0x53]	3479	1		T19	1		T11	5		T12	3
valid_sources[0x54]	3491	1		T19	2		T11	103		T12	138
valid_sources[0x55]	2965	1		T11	2		T12	3		T13	51
valid_sources[0x56]	3286	1		T11	2		T12	2		T13	42
valid_sources[0x57]	3514	1		T11	4		T12	1		T13	34
valid_sources[0x58]	3275	1		T1	3		T11	2		T12	5
valid_sources[0x59]	3051	1		T35	1		T40	1		T11	1
valid_sources[0x5a]	6328	1		T19	1		T11	3		T12	1
valid_sources[0x5b]	2924	1		T11	3		T12	10		T46	2
valid_sources[0x5c]	3032	1		T19	1		T11	2		T12	3
valid_sources[0x5d]	3109	1		T11	8		T12	2		T46	1
valid_sources[0x5e]	3051	1		T1	1		T11	89		T13	28
valid_sources[0x5f]	2977	1		T11	1		T13	49		T52	5
valid_sources[0x60]	2803	1		T11	3		T37	1		T12	1
valid_sources[0x61]	2858	1		T35	3		T11	5		T39	1
valid_sources[0x62]	2777	1		T12	1		T13	40		T279	1
valid_sources[0x63]	2775	1		T7	1		T11	1		T12	5
valid_sources[0x64]	2641	1		T19	1		T11	1		T13	34
valid_sources[0x65]	2911	1		T11	23		T46	1		T13	42
valid_sources[0x66]	3544	1		T11	1		T12	1		T13	55
valid_sources[0x67]	2806	1		T11	1		T12	5		T13	48
valid_sources[0x68]	2555	1		T11	1		T12	3		T13	37
valid_sources[0x69]	2870	1		T11	1		T12	21		T13	52
valid_sources[0x6a]	3720	1		T11	6		T58	1		T12	2
valid_sources[0x6b]	3460	1		T1	1		T11	2		T12	4
valid_sources[0x6c]	3180	1		T7	1		T11	540		T12	2
valid_sources[0x6d]	3195	1		T15	1		T11	5		T12	2
valid_sources[0x6e]	2765	1		T3	1		T12	3		T13	37
valid_sources[0x6f]	3930	1		T40	1		T12	2		T13	47
valid_sources[0x70]	3331	1		T13	47		T52	1		T80	58
valid_sources[0x71]	2768	1		T19	1		T11	4		T12	5
valid_sources[0x72]	3087	1		T4	1		T11	2		T12	2
valid_sources[0x73]	3473	1		T40	1		T11	6		T32	1
valid_sources[0x74]	3167	1		T11	189		T12	17		T13	35
valid_sources[0x75]	3254	1		T48	1		T12	1		T13	44
valid_sources[0x76]	3006	1		T11	7		T12	3		T13	32
valid_sources[0x77]	2918	1		T17	1		T11	1		T13	32
valid_sources[0x78]	2858	1		T19	1		T11	4		T12	2
valid_sources[0x79]	4146	1		T35	1		T11	5		T12	2
valid_sources[0x7a]	2723	1		T11	2		T13	40		T52	3
valid_sources[0x7b]	3622	1		T11	698		T12	2		T13	40
valid_sources[0x7c]	3445	1		T11	651		T12	91		T13	47
valid_sources[0x7d]	3437	1		T11	2		T12	2		T13	43
valid_sources[0x7e]	2967	1		T11	7		T12	5		T46	1
valid_sources[0x7f]	3185	1		T40	1		T11	1		T12	4
valid_sources[0x80]	3650	1		T11	6		T13	45		T52	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

306095

1

T1

2

T2

2

T3

1

values[0x0]

all_enables

biggest_size

118406

1

T1

3

T2

2

T3

4

values[0x1]

all_enables

biggest_size

111389

1

T1

1

T2

2

T3

2