Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	328660	1		T1	5		T2	4		T3	6
full_word	536894	1		T1	6		T2	6		T3	7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	865304	1		T1	11		T2	10		T3	13
auto[TlIntgErrCmd]	94	1		T55	5		T189	1		T198	2
auto[TlIntgErrData]	79	1		T55	3		T189	5		T198	4
auto[TlIntgErrBoth]	77	1		T55	2		T189	4		T198	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	571650	1		T1	4		T2	3		T3	4
auto[1]	293904	1		T1	7		T2	7		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	265275	1		T1	2		T2	1		T3	3
auto[TlIntgErrNone]	partial	auto[1]	63166	1		T1	3		T2	3		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	306272	1		T1	2		T2	2		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	230591	1		T1	4		T2	4		T3	6
auto[TlIntgErrCmd]	partial	auto[0]	39	1		T55	2		T189	1		T198	2
auto[TlIntgErrCmd]	partial	auto[1]	45	1		T55	1		T218	6		T256	3
auto[TlIntgErrCmd]	full_word	auto[1]	10	1		T55	2		T257	1		T258	1
auto[TlIntgErrData]	partial	auto[0]	33	1		T55	2		T189	1		T198	1
auto[TlIntgErrData]	partial	auto[1]	37	1		T55	1		T189	2		T198	3
auto[TlIntgErrData]	full_word	auto[0]	6	1		T189	2		T257	1		T259	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T218	1		T260	1		T196	1
auto[TlIntgErrBoth]	partial	auto[0]	21	1		T189	2		T198	1		T218	4
auto[TlIntgErrBoth]	partial	auto[1]	44	1		T55	1		T189	2		T198	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T198	1		T256	1		T257	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T55	1		T198	1		T261	1