Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.05	92.59	67.16	93.81		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	521654107	11918	0	0
ep_in_enable_rd_A	521654107	2813	0	0
ep_out_enable_rd_A	521654107	2549	0	0
in_iso_rd_A	521654107	2838	0	0
intr_enable_rd_A	521654107	3817	0	0
out_iso_rd_A	521654107	2618	0	0
phy_config_rd_A	521654107	1973	0	0
phy_pins_drive_rd_A	521654107	2197	0	0
rxenable_setup_rd_A	521654107	2564	0	0
set_nak_out_rd_A	521654107	2596	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521654107	11918	0	0
T55	18615	3	0	0
T56	11469	13	0	0
T57	5357	8	0	0
T187	7580	15	0	0
T188	4073	24	0	0
T189	25592	1	0	0
T193	4378	622	0	0
T197	3223	400	0	0
T199	12381	705	0	0
T214	8167	23	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521654107	2813	0	0
T55	18615	309	0	0
T57	5357	25	0	0
T189	25592	163	0	0
T214	8167	81	0	0
T216	7176	63	0	0
T236	3273	30	0	0
T245	7746	28	0	0
T246	4695	7	0	0
T250	4829	33	0	0
T251	7784	54	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521654107	2549	0	0
T55	18615	272	0	0
T57	5357	39	0	0
T189	25592	141	0	0
T214	8167	99	0	0
T216	7176	41	0	0
T236	3273	9	0	0
T245	7746	1	0	0
T246	4695	45	0	0
T250	4829	5	0	0
T251	7784	37	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521654107	2838	0	0
T55	18615	224	0	0
T57	5357	1	0	0
T189	25592	114	0	0
T214	8167	51	0	0
T216	7176	83	0	0
T236	3273	43	0	0
T245	7746	85	0	0
T246	4695	23	0	0
T250	4829	10	0	0
T251	7784	108	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521654107	3817	0	0
T55	18615	464	0	0
T57	5357	60	0	0
T63	2092	14	0	0
T68	1727	24	0	0
T189	25592	179	0	0
T214	8167	8	0	0
T250	4829	74	0	0
T252	1538	7	0	0
T253	1856	29	0	0
T254	1524	14	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521654107	2618	0	0
T55	18615	231	0	0
T57	5357	26	0	0
T189	25592	173	0	0
T214	8167	67	0	0
T216	7176	20	0	0
T236	3273	34	0	0
T245	7746	88	0	0
T246	4695	25	0	0
T250	4829	7	0	0
T251	7784	101	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521654107	1973	0	0
T55	18615	188	0	0
T57	5357	7	0	0
T189	25592	57	0	0
T214	8167	10	0	0
T216	7176	37	0	0
T236	3273	9	0	0
T245	7746	36	0	0
T246	4695	18	0	0
T250	4829	7	0	0
T251	7784	56	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521654107	2197	0	0
T55	18615	260	0	0
T57	5357	5	0	0
T189	25592	69	0	0
T214	8167	18	0	0
T216	7176	20	0	0
T236	3273	26	0	0
T245	7746	25	0	0
T246	4695	13	0	0
T250	4829	41	0	0
T251	7784	44	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521654107	2564	0	0
T55	18615	321	0	0
T57	5357	39	0	0
T189	25592	144	0	0
T213	15992	1	0	0
T214	8167	44	0	0
T216	7176	42	0	0
T245	7746	10	0	0
T246	4695	14	0	0
T250	4829	1	0	0
T251	7784	50	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521654107	2596	0	0
T55	18615	191	0	0
T189	25592	157	0	0
T213	15992	1	0	0
T214	8167	47	0	0
T216	7176	125	0	0
T236	3273	32	0	0
T245	7746	50	0	0
T250	4829	12	0	0
T251	7784	61	0	0
T255	2238	45	0	0