Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	274915	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	467732	1		T1	4660		T2	5		T3	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	473998	1		T1	5514		T2	3		T3	2
values[0x0]	134298	1		T1	1162		T2	5		T3	1
values[0x1]	134351	1		T1	1122		T2	1		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	207830	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	534817	1		T1	5389		T2	7		T3	4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3049	1		T58	2		T4	3		T12	46
valid_sources[0x01]	2316	1		T1	4		T3	2		T10	1
valid_sources[0x02]	2557	1		T3	3		T58	8		T281	10
valid_sources[0x03]	2663	1		T12	53		T13	65		T92	123
valid_sources[0x04]	2527	1		T1	4		T52	2		T12	57
valid_sources[0x05]	2779	1		T1	1		T61	2		T58	4
valid_sources[0x06]	2740	1		T1	2		T58	1		T36	1
valid_sources[0x07]	2726	1		T1	1		T123	1		T12	56
valid_sources[0x08]	5840	1		T1	2		T12	56		T282	1
valid_sources[0x09]	2823	1		T1	1		T58	7		T283	1
valid_sources[0x0a]	3282	1		T1	2		T58	1		T129	1
valid_sources[0x0b]	3489	1		T1	3		T58	11		T59	458
valid_sources[0x0c]	2532	1		T1	4		T58	16		T123	1
valid_sources[0x0d]	2613	1		T54	2		T284	1		T285	8
valid_sources[0x0e]	3198	1		T87	1		T39	1		T12	44
valid_sources[0x0f]	2450	1		T30	3		T87	1		T98	11
valid_sources[0x10]	2080	1		T1	2		T286	1		T149	1
valid_sources[0x11]	2669	1		T1	2		T31	26		T91	1
valid_sources[0x12]	2385	1		T58	4		T286	2		T126	1
valid_sources[0x13]	2895	1		T1	35		T57	5		T284	1
valid_sources[0x14]	2712	1		T1	101		T12	62		T287	2
valid_sources[0x15]	2655	1		T1	6		T87	2		T288	1
valid_sources[0x16]	2661	1		T58	6		T212	1		T169	1
valid_sources[0x17]	5506	1		T1	2		T22	1		T289	1
valid_sources[0x18]	3659	1		T1	196		T58	11		T51	1
valid_sources[0x19]	3186	1		T1	4		T39	1		T51	1
valid_sources[0x1a]	2489	1		T1	1		T87	1		T36	2
valid_sources[0x1b]	2717	1		T1	72		T14	1		T58	1
valid_sources[0x1c]	2546	1		T1	1		T32	26		T290	1
valid_sources[0x1d]	2715	1		T1	4		T58	2		T100	12
valid_sources[0x1e]	2385	1		T1	2		T27	1		T52	1
valid_sources[0x1f]	2629	1		T35	1		T58	9		T111	2
valid_sources[0x20]	3097	1		T1	3		T286	1		T12	52
valid_sources[0x21]	2867	1		T1	546		T16	10		T58	12
valid_sources[0x22]	2324	1		T1	2		T17	1		T58	7
valid_sources[0x23]	2284	1		T291	1		T49	1		T12	53
valid_sources[0x24]	2301	1		T58	7		T55	1		T292	1
valid_sources[0x25]	2814	1		T58	1		T54	8		T51	1
valid_sources[0x26]	23814	1		T1	2		T284	1		T123	1
valid_sources[0x27]	2113	1		T1	1		T58	23		T55	1
valid_sources[0x28]	2620	1		T58	1		T293	2		T12	50
valid_sources[0x29]	2208	1		T1	3		T58	4		T51	1
valid_sources[0x2a]	2557	1		T1	1		T87	1		T88	1
valid_sources[0x2b]	2455	1		T58	5		T36	1		T283	1
valid_sources[0x2c]	2229	1		T1	1		T58	14		T139	1
valid_sources[0x2d]	2163	1		T58	1		T55	1		T142	2
valid_sources[0x2e]	3196	1		T1	1		T58	7		T12	67
valid_sources[0x2f]	3136	1		T1	1		T294	1		T295	21
valid_sources[0x30]	2232	1		T1	1		T58	6		T296	1
valid_sources[0x31]	2635	1		T1	2		T141	1		T283	1
valid_sources[0x32]	2709	1		T88	1		T12	56		T297	1
valid_sources[0x33]	3612	1		T91	1		T126	1		T12	46
valid_sources[0x34]	2772	1		T1	382		T89	4		T41	1
valid_sources[0x35]	3603	1		T1	3		T58	6		T54	2
valid_sources[0x36]	2592	1		T1	86		T35	2		T298	1
valid_sources[0x37]	2247	1		T51	1		T145	1		T288	1
valid_sources[0x38]	2343	1		T1	2		T58	1		T55	1
valid_sources[0x39]	2407	1		T2	6		T283	1		T12	50
valid_sources[0x3a]	2501	1		T1	1		T58	4		T88	1
valid_sources[0x3b]	2303	1		T58	1		T28	1		T299	12
valid_sources[0x3c]	2299	1		T87	1		T4	1		T52	1
valid_sources[0x3d]	2649	1		T300	1		T12	53		T287	4
valid_sources[0x3e]	2723	1		T1	2		T10	1		T30	1
valid_sources[0x3f]	2731	1		T1	1		T58	3		T149	1
valid_sources[0x40]	3374	1		T1	2		T17	2		T58	10
valid_sources[0x41]	2521	1		T1	1		T51	1		T286	1
valid_sources[0x42]	2458	1		T1	4		T58	3		T144	1
valid_sources[0x43]	2127	1		T88	1		T111	9		T291	1
valid_sources[0x44]	2377	1		T58	1		T286	1		T145	1
valid_sources[0x45]	2347	1		T58	4		T27	1		T123	1
valid_sources[0x46]	4307	1		T1	2		T87	1		T58	3
valid_sources[0x47]	3262	1		T1	1		T58	1		T55	1
valid_sources[0x48]	2525	1		T1	2		T58	1		T27	1
valid_sources[0x49]	2685	1		T1	2		T129	1		T301	1
valid_sources[0x4a]	3015	1		T91	1		T41	2		T301	1
valid_sources[0x4b]	2555	1		T12	41		T148	1		T287	4
valid_sources[0x4c]	3514	1		T1	366		T58	1		T291	1
valid_sources[0x4d]	2645	1		T97	1		T165	1		T12	53
valid_sources[0x4e]	3361	1		T1	4		T40	14		T91	1
valid_sources[0x4f]	2826	1		T1	218		T19	2		T58	11
valid_sources[0x50]	2526	1		T1	1		T33	1		T54	2
valid_sources[0x51]	2435	1		T1	1		T58	4		T91	2
valid_sources[0x52]	2352	1		T1	2		T61	4		T286	1
valid_sources[0x53]	3035	1		T1	1		T146	1		T12	61
valid_sources[0x54]	2599	1		T14	1		T132	2		T302	1
valid_sources[0x55]	2560	1		T1	69		T289	1		T12	61
valid_sources[0x56]	2518	1		T1	4		T35	1		T58	2
valid_sources[0x57]	2480	1		T1	1		T144	1		T12	79
valid_sources[0x58]	3129	1		T1	3		T58	11		T303	2
valid_sources[0x59]	3356	1		T88	1		T212	1		T284	1
valid_sources[0x5a]	3092	1		T1	2		T3	2		T10	2
valid_sources[0x5b]	2789	1		T58	2		T288	1		T12	52
valid_sources[0x5c]	3480	1		T1	2		T58	12		T91	1
valid_sources[0x5d]	2591	1		T1	2		T58	1		T36	1
valid_sources[0x5e]	2393	1		T1	3		T88	1		T286	1
valid_sources[0x5f]	2350	1		T1	3		T146	2		T126	1
valid_sources[0x60]	3078	1		T1	528		T7	1		T144	1
valid_sources[0x61]	3034	1		T1	2		T18	3		T88	1
valid_sources[0x62]	2809	1		T1	1		T58	2		T97	1
valid_sources[0x63]	3020	1		T1	2		T37	1		T55	1
valid_sources[0x64]	2691	1		T1	4		T289	1		T212	2
valid_sources[0x65]	2732	1		T58	1		T51	1		T286	1
valid_sources[0x66]	2639	1		T37	1		T290	1		T146	2
valid_sources[0x67]	2107	1		T1	2		T289	1		T144	2
valid_sources[0x68]	3055	1		T1	172		T58	3		T146	1
valid_sources[0x69]	2393	1		T1	1		T55	1		T51	2
valid_sources[0x6a]	3510	1		T1	1		T35	1		T58	5
valid_sources[0x6b]	3042	1		T1	4		T290	2		T12	60
valid_sources[0x6c]	3618	1		T27	1		T289	1		T139	2
valid_sources[0x6d]	5544	1		T1	3102		T6	1		T12	53
valid_sources[0x6e]	2518	1		T144	1		T91	2		T140	14
valid_sources[0x6f]	2607	1		T1	1		T35	1		T51	1
valid_sources[0x70]	2581	1		T51	1		T290	1		T91	1
valid_sources[0x71]	2306	1		T1	1		T298	7		T91	1
valid_sources[0x72]	2547	1		T1	1		T58	1		T139	1
valid_sources[0x73]	2985	1		T1	220		T7	1		T87	1
valid_sources[0x74]	2438	1		T1	1		T91	1		T12	54
valid_sources[0x75]	2589	1		T1	4		T18	8		T51	1
valid_sources[0x76]	2777	1		T61	3		T58	2		T303	3
valid_sources[0x77]	2489	1		T1	2		T10	1		T139	1
valid_sources[0x78]	3440	1		T1	3		T10	1		T290	1
valid_sources[0x79]	2986	1		T1	2		T35	1		T55	1
valid_sources[0x7a]	2370	1		T1	6		T2	1		T58	6
valid_sources[0x7b]	2618	1		T14	1		T55	1		T144	1
valid_sources[0x7c]	2622	1		T1	2		T12	66		T287	14
valid_sources[0x7d]	5430	1		T10	1		T141	1		T304	2
valid_sources[0x7e]	2366	1		T1	5		T305	1		T301	7
valid_sources[0x7f]	2156	1		T22	1		T58	8		T37	1
valid_sources[0x80]	2162	1		T1	1		T58	1		T51	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

248013

1

T1

2514

T2

1

T3

2

values[0x0]

all_enables

biggest_size

113981

1

T1

1091

T2

4

T3

1

values[0x1]

all_enables

biggest_size

105738

1

T1

1055

T10

1

T16

1