Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	290326	1		T1	3138		T2	4		T3	5
full_word	468866	1		T1	4660		T2	5		T3	3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	758882	1		T1	7798		T2	9		T3	8
auto[TlIntgErrCmd]	116	1		T199	7		T203	3		T205	4
auto[TlIntgErrData]	108	1		T199	6		T203	6		T205	8
auto[TlIntgErrBoth]	86	1		T199	7		T203	1		T205	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	475986	1		T1	5514		T2	3		T3	2
auto[1]	283206	1		T1	2284		T2	6		T3	6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	227626	1		T1	3000		T2	2		T9	1
auto[TlIntgErrNone]	partial	auto[1]	62415	1		T1	138		T2	2		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	248237	1		T1	2514		T2	1		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	220604	1		T1	2146		T2	4		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T199	2		T203	2		T205	1
auto[TlIntgErrCmd]	partial	auto[1]	64	1		T199	3		T205	3		T204	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T256	1		T277	1		T278	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T199	2		T203	1		T204	1
auto[TlIntgErrData]	partial	auto[0]	39	1		T199	2		T203	3		T205	4
auto[TlIntgErrData]	partial	auto[1]	55	1		T199	4		T203	2		T205	3
auto[TlIntgErrData]	full_word	auto[0]	5	1		T203	1		T205	1		T226	1
auto[TlIntgErrData]	full_word	auto[1]	9	1		T279	1		T256	1		T277	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T199	5		T203	1		T205	4
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T199	2		T205	4		T204	6
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T277	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T280	1		-	-		-	-