Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.14	92.59	67.16	94.27		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	519915427	12321	0	0
ep_in_enable_rd_A	519915427	2675	0	0
ep_out_enable_rd_A	519915427	2487	0	0
in_iso_rd_A	519915427	2772	0	0
intr_enable_rd_A	519915427	4317	0	0
out_iso_rd_A	519915427	2819	0	0
phy_config_rd_A	519915427	1738	0	0
phy_pins_drive_rd_A	519915427	2463	0	0
rxenable_setup_rd_A	519915427	2192	0	0
set_nak_out_rd_A	519915427	2904	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519915427	12321	0	0
T62	11304	1115	0	0
T63	5286	23	0	0
T64	9685	10	0	0
T199	39638	3	0	0
T203	41558	2	0	0
T205	38764	4	0	0
T206	5900	19	0	0
T207	4415	632	0	0
T224	6649	25	0	0
T225	7600	18	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519915427	2675	0	0
T198	9273	55	0	0
T200	2134	29	0	0
T202	2606	12	0	0
T203	41558	368	0	0
T204	28027	223	0	0
T208	8996	1	0	0
T225	7600	15	0	0
T243	3598	24	0	0
T255	3899	5	0	0
T256	38934	313	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519915427	2487	0	0
T198	9273	52	0	0
T200	2134	36	0	0
T203	41558	230	0	0
T204	28027	331	0	0
T225	7600	43	0	0
T243	3598	18	0	0
T255	3899	3	0	0
T256	38934	262	0	0
T257	2820	10	0	0
T258	23786	239	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519915427	2772	0	0
T198	9273	60	0	0
T200	2134	12	0	0
T202	2606	22	0	0
T203	41558	222	0	0
T204	28027	256	0	0
T225	7600	63	0	0
T243	3598	21	0	0
T255	3899	2	0	0
T256	38934	343	0	0
T257	2820	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519915427	4317	0	0
T75	2593	16	0	0
T198	9273	63	0	0
T202	2606	29	0	0
T203	41558	410	0	0
T204	28027	435	0	0
T225	7600	36	0	0
T243	3598	30	0	0
T259	1900	24	0	0
T260	1497	3	0	0
T261	3720	23	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519915427	2819	0	0
T198	9273	49	0	0
T200	2134	3	0	0
T202	2606	37	0	0
T203	41558	328	0	0
T204	28027	233	0	0
T225	7600	39	0	0
T243	3598	46	0	0
T255	3899	6	0	0
T256	38934	291	0	0
T257	2820	5	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519915427	1738	0	0
T198	9273	63	0	0
T200	2134	13	0	0
T202	2606	8	0	0
T203	41558	128	0	0
T204	28027	148	0	0
T225	7600	23	0	0
T243	3598	8	0	0
T255	3899	4	0	0
T256	38934	182	0	0
T257	2820	24	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519915427	2463	0	0
T198	9273	77	0	0
T200	2134	14	0	0
T202	2606	1	0	0
T203	41558	260	0	0
T204	28027	182	0	0
T208	8996	9	0	0
T225	7600	37	0	0
T243	3598	32	0	0
T256	38934	251	0	0
T257	2820	23	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519915427	2192	0	0
T198	9273	83	0	0
T202	2606	33	0	0
T203	41558	160	0	0
T204	28027	217	0	0
T225	7600	31	0	0
T243	3598	40	0	0
T255	3899	22	0	0
T256	38934	273	0	0
T257	2820	20	0	0
T258	23786	173	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519915427	2904	0	0
T198	9273	41	0	0
T200	2134	40	0	0
T202	2606	3	0	0
T203	41558	171	0	0
T204	28027	397	0	0
T225	7600	19	0	0
T243	3598	25	0	0
T255	3899	32	0	0
T256	38934	319	0	0
T257	2820	2	0	0