Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wake_events_cdc	68.40	94.12	46.15			83.33	50.00
tb.dut.u_reg.u_wake_control_cdc	97.73	100.00	90.91			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wake_events_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.40	94.12	46.15			83.33	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.81	89.84	52.94			82.46	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.47	99.76	98.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	75.00	88.78	57.14			79.07	75.00
u_src_to_dst_req	56.41	92.31	33.33			100.00	0.00

---

Module Instance : tb.dut.u_reg.u_wake_control_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	96.08	96.43			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.47	99.76	98.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.88	87.50	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T68,T69,T63

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T68,T69,T63
1	1	Covered	T68,T69,T63

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21
1	0	Covered	T68,T69,T63

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T68,T69,T63
1	1	Covered	T68,T69,T63

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T20,T21

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T68,T69,T63
0	0	1	Covered	T68,T69,T63
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T68,T69,T63
0	0	1	Covered	T68,T69,T63
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1039830854	162922	0	0
DstReqKnown_A	23539550	23507166	0	0
SrcAckBusyChk_A	1039830854	815	0	0
SrcBusyKnown_A	1039830854	1039488486	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039830854	162922	0	0
T63	5286	299	0	0
T64	9685	701	0	0
T68	3655	794	0	0
T69	3033	132	0	0
T70	2574	741	0	0
T198	9273	201	0	0
T199	39638	3429	0	0
T200	2134	77	0	0
T201	6048	707	0	0
T202	2606	123	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23539550	23507166	0	0
T1	34766	34748	0	0
T2	30098	30062	0	0
T3	18354	18340	0	0
T9	18222	18206	0	0
T10	4708	4694	0	0
T14	17690	17666	0	0
T16	27174	27160	0	0
T17	15866	15846	0	0
T18	31810	31796	0	0
T19	28142	28122	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039830854	815	0	0
T63	5286	2	0	0
T64	9685	1	0	0
T68	3655	11	0	0
T69	3033	2	0	0
T70	2574	9	0	0
T198	9273	1	0	0
T199	39638	20	0	0
T200	2134	1	0	0
T201	6048	10	0	0
T202	2606	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039830854	1039488486	0	0
T1	1723914	1723746	0	0
T2	803506	803182	0	0
T3	803908	803710	0	0
T9	805416	805246	0	0
T10	807358	807180	0	0
T14	807282	806932	0	0
T16	804174	803984	0	0
T17	805094	804918	0	0
T18	805770	805598	0	0
T19	806498	806366	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Line No.	Total	Covered	Percent
TOTAL		17	16	94.12
CONT_ASSIGN	65	0	0
ALWAYS	71	5	4	80.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	7	7	100.00
CONT_ASSIGN	150	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65		unreachable
71	1	1
72	1	1
73	1	1
74		unreachable
75	1	1
76	0	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123		unreachable
124		unreachable
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150		unreachable
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Total	Covered	Percent
Conditions	13	6	46.15
Logical	13	6	46.15
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T21
1	0	Not Covered

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T20,T21

---

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Line No.	Total	Covered	Percent
Branches		6	5	83.33
IF	71	3	2	66.67
IF	115	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Unreachable
0	0	1	Covered	T20,T21
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	2	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	2	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	519915427	0	0	0
DstReqKnown_A	11769775	11753583	0	0
SrcAckBusyChk_A	519915427	0	0	0
SrcBusyKnown_A	519915427	519744243	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519915427	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11769775	11753583	0	0
T1	17383	17374	0	0
T2	15049	15031	0	0
T3	9177	9170	0	0
T9	9111	9103	0	0
T10	2354	2347	0	0
T14	8845	8833	0	0
T16	13587	13580	0	0
T17	7933	7923	0	0
T18	15905	15898	0	0
T19	14071	14061	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519915427	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519915427	519744243	0	0
T1	861957	861873	0	0
T2	401753	401591	0	0
T3	401954	401855	0	0
T9	402708	402623	0	0
T10	403679	403590	0	0
T14	403641	403466	0	0
T16	402087	401992	0	0
T17	402547	402459	0	0
T18	402885	402799	0	0
T19	403249	403183	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T68,T69,T63

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T68,T69,T63
1	1	Covered	T68,T69,T63

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T68,T69,T63

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T68,T69,T63
1	1	Covered	T68,T69,T63

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T68,T69,T63
0	0	1	Covered	T68,T69,T63
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T68,T69,T63
0	0	1	Covered	T68,T69,T63
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	519915427	162922	0	0
DstReqKnown_A	11769775	11753583	0	0
SrcAckBusyChk_A	519915427	815	0	0
SrcBusyKnown_A	519915427	519744243	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519915427	162922	0	0
T63	5286	299	0	0
T64	9685	701	0	0
T68	3655	794	0	0
T69	3033	132	0	0
T70	2574	741	0	0
T198	9273	201	0	0
T199	39638	3429	0	0
T200	2134	77	0	0
T201	6048	707	0	0
T202	2606	123	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11769775	11753583	0	0
T1	17383	17374	0	0
T2	15049	15031	0	0
T3	9177	9170	0	0
T9	9111	9103	0	0
T10	2354	2347	0	0
T14	8845	8833	0	0
T16	13587	13580	0	0
T17	7933	7923	0	0
T18	15905	15898	0	0
T19	14071	14061	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519915427	815	0	0
T63	5286	2	0	0
T64	9685	1	0	0
T68	3655	11	0	0
T69	3033	2	0	0
T70	2574	9	0	0
T198	9273	1	0	0
T199	39638	20	0	0
T200	2134	1	0	0
T201	6048	10	0	0
T202	2606	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519915427	519744243	0	0
T1	861957	861873	0	0
T2	401753	401591	0	0
T3	401954	401855	0	0
T9	402708	402623	0	0
T10	403679	403590	0	0
T14	403641	403466	0	0
T16	402087	401992	0	0
T17	402547	402459	0	0
T18	402885	402799	0	0
T19	403249	403183	0	0