Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	273961	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	459272	1		T1	138		T2	10		T3	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	467303	1		T1	87		T2	10		T3	4
values[0x0]	132458	1		T1	170		T2	3		T3	4
values[0x1]	133472	1		T1	170		T2	3		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	207204	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	526029	1		T1	179		T2	11		T3	6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2699	1		T53	8		T12	95		T13	52
valid_sources[0x01]	2034	1		T1	2		T53	2		T12	51
valid_sources[0x02]	2293	1		T1	4		T53	2		T12	15
valid_sources[0x03]	3088	1		T1	1		T8	1		T53	1
valid_sources[0x04]	3596	1		T1	6		T53	4		T12	35
valid_sources[0x05]	2625	1		T1	2		T53	7		T38	1
valid_sources[0x06]	2452	1		T1	2		T53	9		T12	31
valid_sources[0x07]	3166	1		T1	1		T53	4		T12	52
valid_sources[0x08]	2319	1		T1	3		T53	2		T12	41
valid_sources[0x09]	3206	1		T1	1		T12	59		T13	59
valid_sources[0x0a]	3483	1		T1	5		T53	4		T12	33
valid_sources[0x0b]	2298	1		T1	2		T12	31		T13	66
valid_sources[0x0c]	2032	1		T1	1		T53	1		T12	32
valid_sources[0x0d]	3423	1		T1	10		T53	5		T12	23
valid_sources[0x0e]	2258	1		T53	3		T12	35		T13	62
valid_sources[0x0f]	2403	1		T53	3		T12	44		T31	7
valid_sources[0x10]	2428	1		T1	5		T53	4		T12	60
valid_sources[0x11]	2228	1		T53	2		T12	26		T40	2
valid_sources[0x12]	2610	1		T53	5		T12	25		T29	1
valid_sources[0x13]	3078	1		T1	2		T53	1		T12	40
valid_sources[0x14]	2167	1		T1	2		T53	7		T12	37
valid_sources[0x15]	2451	1		T53	8		T12	28		T31	1
valid_sources[0x16]	1985	1		T12	35		T13	53		T14	74
valid_sources[0x17]	1926	1		T1	2		T53	3		T12	23
valid_sources[0x18]	2659	1		T1	4		T53	1		T12	39
valid_sources[0x19]	3773	1		T12	28		T13	63		T14	43
valid_sources[0x1a]	2148	1		T53	4		T12	42		T39	1
valid_sources[0x1b]	2895	1		T53	2		T12	60		T13	54
valid_sources[0x1c]	2531	1		T1	1		T53	2		T38	1
valid_sources[0x1d]	2519	1		T1	3		T12	34		T10	1
valid_sources[0x1e]	2887	1		T12	48		T280	1		T13	55
valid_sources[0x1f]	2095	1		T53	6		T12	32		T13	51
valid_sources[0x20]	2626	1		T18	1		T53	2		T12	44
valid_sources[0x21]	2737	1		T53	1		T12	67		T13	69
valid_sources[0x22]	1912	1		T1	7		T53	4		T12	50
valid_sources[0x23]	3144	1		T1	1		T53	3		T12	58
valid_sources[0x24]	2522	1		T53	1		T16	11		T12	42
valid_sources[0x25]	3563	1		T53	2		T12	18		T13	51
valid_sources[0x26]	4108	1		T17	1		T53	1		T12	53
valid_sources[0x27]	2334	1		T8	1		T19	1		T53	1
valid_sources[0x28]	3374	1		T15	9		T53	1		T12	49
valid_sources[0x29]	2409	1		T33	3		T12	28		T13	49
valid_sources[0x2a]	2962	1		T53	4		T12	21		T13	59
valid_sources[0x2b]	2149	1		T53	4		T12	26		T29	1
valid_sources[0x2c]	1995	1		T12	26		T13	62		T14	57
valid_sources[0x2d]	2715	1		T1	1		T53	5		T12	17
valid_sources[0x2e]	2622	1		T1	2		T32	9		T53	2
valid_sources[0x2f]	2508	1		T12	29		T13	66		T14	63
valid_sources[0x30]	2382	1		T1	1		T12	31		T13	60
valid_sources[0x31]	2737	1		T1	1		T53	1		T12	33
valid_sources[0x32]	2828	1		T53	1		T12	14		T31	1
valid_sources[0x33]	2372	1		T53	2		T12	41		T13	63
valid_sources[0x34]	7326	1		T1	1		T53	3		T12	57
valid_sources[0x35]	2855	1		T1	8		T53	4		T12	39
valid_sources[0x36]	3153	1		T53	2		T12	28		T13	72
valid_sources[0x37]	2547	1		T53	2		T12	32		T13	59
valid_sources[0x38]	2105	1		T1	4		T53	2		T12	23
valid_sources[0x39]	2203	1		T53	1		T12	38		T13	72
valid_sources[0x3a]	2485	1		T53	3		T33	5		T12	33
valid_sources[0x3b]	3240	1		T53	3		T12	33		T13	58
valid_sources[0x3c]	2335	1		T53	4		T12	40		T13	55
valid_sources[0x3d]	2972	1		T1	1		T12	52		T13	64
valid_sources[0x3e]	2303	1		T1	3		T12	9		T13	67
valid_sources[0x3f]	3394	1		T53	3		T12	39		T13	63
valid_sources[0x40]	2065	1		T1	2		T53	9		T12	34
valid_sources[0x41]	2482	1		T53	6		T12	39		T13	63
valid_sources[0x42]	2580	1		T53	1		T12	29		T13	73
valid_sources[0x43]	2375	1		T53	3		T12	49		T13	75
valid_sources[0x44]	5381	1		T53	3		T12	27		T13	79
valid_sources[0x45]	2322	1		T12	17		T13	68		T14	47
valid_sources[0x46]	2595	1		T1	3		T53	2		T12	30
valid_sources[0x47]	2002	1		T53	3		T12	34		T39	1
valid_sources[0x48]	2101	1		T12	39		T13	46		T14	48
valid_sources[0x49]	2157	1		T12	26		T39	1		T13	51
valid_sources[0x4a]	3005	1		T53	1		T12	28		T13	39
valid_sources[0x4b]	5319	1		T1	1		T53	1		T38	1
valid_sources[0x4c]	2731	1		T1	2		T53	1		T12	41
valid_sources[0x4d]	2406	1		T53	2		T12	29		T10	2
valid_sources[0x4e]	2558	1		T1	1		T53	5		T12	32
valid_sources[0x4f]	3202	1		T53	1		T12	7		T13	57
valid_sources[0x50]	2196	1		T1	3		T53	2		T12	31
valid_sources[0x51]	2923	1		T1	2		T53	10		T12	23
valid_sources[0x52]	2300	1		T1	2		T53	5		T12	31
valid_sources[0x53]	2538	1		T1	5		T12	75		T13	57
valid_sources[0x54]	2328	1		T1	1		T12	43		T39	1
valid_sources[0x55]	2450	1		T12	26		T121	1		T281	1
valid_sources[0x56]	2441	1		T1	2		T53	1		T12	48
valid_sources[0x57]	2048	1		T1	5		T53	4		T12	34
valid_sources[0x58]	6771	1		T53	5		T12	25		T13	65
valid_sources[0x59]	2275	1		T1	3		T18	1		T19	1
valid_sources[0x5a]	3094	1		T1	1		T3	7		T18	1
valid_sources[0x5b]	1807	1		T1	1		T9	1		T53	3
valid_sources[0x5c]	2288	1		T53	4		T12	40		T281	1
valid_sources[0x5d]	2655	1		T53	1		T12	63		T13	78
valid_sources[0x5e]	2494	1		T1	4		T53	1		T12	55
valid_sources[0x5f]	3764	1		T1	2		T53	4		T12	52
valid_sources[0x60]	2690	1		T12	59		T121	1		T13	54
valid_sources[0x61]	3413	1		T53	7		T12	30		T13	54
valid_sources[0x62]	2460	1		T1	4		T53	1		T38	1
valid_sources[0x63]	2511	1		T1	1		T53	1		T12	34
valid_sources[0x64]	2707	1		T53	1		T12	27		T121	1
valid_sources[0x65]	2228	1		T1	5		T53	1		T12	45
valid_sources[0x66]	2329	1		T1	9		T53	1		T12	24
valid_sources[0x67]	2589	1		T1	7		T53	3		T12	37
valid_sources[0x68]	2522	1		T1	12		T9	4		T12	57
valid_sources[0x69]	6819	1		T1	1		T18	2		T53	1
valid_sources[0x6a]	5672	1		T53	2		T12	51		T280	1
valid_sources[0x6b]	3187	1		T1	7		T12	19		T85	8
valid_sources[0x6c]	2646	1		T1	2		T53	4		T12	42
valid_sources[0x6d]	2207	1		T53	1		T12	44		T23	1
valid_sources[0x6e]	5797	1		T1	1		T53	2		T12	42
valid_sources[0x6f]	5349	1		T1	1		T53	2		T12	39
valid_sources[0x70]	2380	1		T1	2		T53	2		T12	23
valid_sources[0x71]	2365	1		T53	2		T12	52		T46	4
valid_sources[0x72]	2173	1		T12	45		T13	48		T14	55
valid_sources[0x73]	2579	1		T1	1		T19	1		T53	1
valid_sources[0x74]	2189	1		T11	5		T53	3		T12	27
valid_sources[0x75]	2725	1		T20	13		T9	1		T53	3
valid_sources[0x76]	2845	1		T53	1		T12	39		T13	72
valid_sources[0x77]	3500	1		T1	4		T12	45		T13	53
valid_sources[0x78]	2082	1		T19	1		T53	1		T12	69
valid_sources[0x79]	3054	1		T1	1		T12	13		T13	82
valid_sources[0x7a]	2854	1		T53	3		T12	34		T13	66
valid_sources[0x7b]	2916	1		T53	5		T12	32		T13	80
valid_sources[0x7c]	3198	1		T1	1		T53	2		T12	24
valid_sources[0x7d]	2029	1		T1	5		T17	1		T53	2
valid_sources[0x7e]	2195	1		T53	8		T12	13		T13	62
valid_sources[0x7f]	3217	1		T53	1		T12	40		T13	72
valid_sources[0x80]	2161	1		T12	55		T31	3		T13	60

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

242872

1

T1

41

T2

7

T3

1

values[0x0]

all_enables

biggest_size

111984

1

T1

64

T2

3

T3

2

values[0x1]

all_enables

biggest_size

104416

1

T1

33

T8

2

T15

2