Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	288352	1		T1	289		T2	6		T3	9
full_word	460235	1		T1	138		T2	10		T3	3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	748317	1		T1	427		T2	16		T3	12
auto[TlIntgErrCmd]	95	1		T55	5		T56	6		T57	5
auto[TlIntgErrData]	91	1		T55	2		T56	3		T57	4
auto[TlIntgErrBoth]	84	1		T55	3		T56	1		T57	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	469109	1		T1	87		T2	10		T3	4
auto[1]	279478	1		T1	340		T2	6		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	225961	1		T1	46		T2	3		T3	3
auto[TlIntgErrNone]	partial	auto[1]	62136	1		T1	243		T2	3		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	243033	1		T1	41		T2	7		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	217187	1		T1	97		T2	3		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	34	1		T55	2		T56	2		T57	3
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T55	3		T56	4		T57	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T227	1		T276	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T254	1		T277	1		-	-
auto[TlIntgErrData]	partial	auto[0]	40	1		T56	1		T57	1		T199	5
auto[TlIntgErrData]	partial	auto[1]	45	1		T55	2		T56	2		T57	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T199	1		T278	1		T279	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T278	1		T275	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T55	2		T57	1		T199	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T55	1		T56	1		T199	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T199	1		T226	1		T275	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T227	1		T273	1		-	-