Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.14	92.59	67.16	94.27		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	518660105	11619	0	0
ep_in_enable_rd_A	518660105	1597	0	0
ep_out_enable_rd_A	518660105	1489	0	0
in_iso_rd_A	518660105	1838	0	0
intr_enable_rd_A	518660105	2591	0	0
out_iso_rd_A	518660105	1724	0	0
phy_config_rd_A	518660105	1386	0	0
phy_pins_drive_rd_A	518660105	1481	0	0
rxenable_setup_rd_A	518660105	1780	0	0
set_nak_out_rd_A	518660105	1720	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518660105	11619	0	0
T55	10597	5	0	0
T57	20663	3	0	0
T196	5906	11	0	0
T197	3511	18	0	0
T199	31903	5	0	0
T200	13582	4	0	0
T201	4367	9	0	0
T202	10620	16	0	0
T204	3043	351	0	0
T205	4321	797	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518660105	1597	0	0
T57	20663	132	0	0
T201	4367	58	0	0
T226	29396	91	0	0
T235	60304	224	0	0
T243	10991	17	0	0
T251	5936	4	0	0
T252	7484	38	0	0
T253	13393	33	0	0
T254	20689	208	0	0
T255	71922	250	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518660105	1489	0	0
T57	20663	177	0	0
T201	4367	2	0	0
T226	29396	166	0	0
T235	60304	243	0	0
T243	10991	16	0	0
T251	5936	21	0	0
T252	7484	10	0	0
T253	13393	44	0	0
T254	20689	83	0	0
T256	3367	24	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518660105	1838	0	0
T57	20663	169	0	0
T201	4367	16	0	0
T226	29396	214	0	0
T235	60304	286	0	0
T243	10991	14	0	0
T251	5936	16	0	0
T252	7484	12	0	0
T253	13393	15	0	0
T254	20689	233	0	0
T256	3367	68	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518660105	2591	0	0
T57	20663	219	0	0
T67	1362	2	0	0
T201	4367	59	0	0
T226	29396	297	0	0
T235	60304	296	0	0
T243	10991	19	0	0
T257	1997	19	0	0
T258	3253	28	0	0
T259	1710	1	0	0
T260	1982	12	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518660105	1724	0	0
T57	20663	154	0	0
T201	4367	4	0	0
T226	29396	145	0	0
T235	60304	239	0	0
T243	10991	44	0	0
T251	5936	13	0	0
T252	7484	20	0	0
T253	13393	72	0	0
T254	20689	287	0	0
T256	3367	28	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518660105	1386	0	0
T57	20663	64	0	0
T201	4367	16	0	0
T226	29396	68	0	0
T235	60304	310	0	0
T243	10991	7	0	0
T252	7484	8	0	0
T253	13393	14	0	0
T254	20689	172	0	0
T255	71922	290	0	0
T256	3367	27	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518660105	1481	0	0
T57	20663	152	0	0
T201	4367	12	0	0
T226	29396	78	0	0
T235	60304	205	0	0
T243	10991	14	0	0
T252	7484	18	0	0
T253	13393	27	0	0
T254	20689	138	0	0
T255	71922	255	0	0
T256	3367	21	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518660105	1780	0	0
T57	20663	127	0	0
T201	4367	8	0	0
T226	29396	160	0	0
T235	60304	233	0	0
T243	10991	31	0	0
T251	5936	25	0	0
T252	7484	7	0	0
T253	13393	50	0	0
T254	20689	103	0	0
T256	3367	53	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518660105	1720	0	0
T57	20663	111	0	0
T201	4367	20	0	0
T226	29396	122	0	0
T235	60304	246	0	0
T243	10991	19	0	0
T251	5936	15	0	0
T252	7484	2	0	0
T253	13393	38	0	0
T254	20689	316	0	0
T256	3367	53	0	0