Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	303646	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	516099	1		T1	6		T2	13		T3	8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	551529	1		T1	3		T2	11		T3	4
values[0x0]	133371	1		T1	3		T2	2		T3	3
values[0x1]	134845	1		T1	4		T2	3		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	232159	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	587586	1		T1	7		T2	13		T3	9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3115	1		T19	1		T10	107		T11	51
valid_sources[0x01]	3359	1		T10	11		T85	1		T87	2
valid_sources[0x02]	2915	1		T18	3		T10	117		T11	40
valid_sources[0x03]	3345	1		T10	21		T14	1		T24	3
valid_sources[0x04]	2667	1		T2	4		T17	1		T10	6
valid_sources[0x05]	2943	1		T18	2		T10	41		T11	46
valid_sources[0x06]	3426	1		T10	2		T34	1		T11	59
valid_sources[0x07]	2973	1		T10	18		T11	41		T55	1
valid_sources[0x08]	2895	1		T10	74		T54	1		T11	33
valid_sources[0x09]	3880	1		T3	1		T19	1		T10	50
valid_sources[0x0a]	3223	1		T11	49		T55	3		T274	3
valid_sources[0x0b]	3061	1		T10	30		T85	1		T11	48
valid_sources[0x0c]	3410	1		T18	1		T19	2		T10	88
valid_sources[0x0d]	2859	1		T16	1		T10	29		T11	35
valid_sources[0x0e]	2764	1		T10	29		T11	49		T55	2
valid_sources[0x0f]	3138	1		T10	16		T11	43		T55	4
valid_sources[0x10]	2864	1		T10	31		T11	36		T55	1
valid_sources[0x11]	2864	1		T11	42		T55	6		T56	48
valid_sources[0x12]	3118	1		T2	1		T10	26		T36	10
valid_sources[0x13]	4048	1		T19	2		T10	50		T11	43
valid_sources[0x14]	2701	1		T10	9		T11	45		T55	5
valid_sources[0x15]	3436	1		T10	27		T23	1		T11	40
valid_sources[0x16]	3151	1		T10	36		T30	4		T11	40
valid_sources[0x17]	2730	1		T10	18		T85	1		T29	1
valid_sources[0x18]	6625	1		T2	3		T18	1		T10	50
valid_sources[0x19]	6529	1		T3	1		T10	57		T29	1
valid_sources[0x1a]	2801	1		T10	146		T11	39		T55	6
valid_sources[0x1b]	3033	1		T10	13		T11	55		T55	5
valid_sources[0x1c]	3680	1		T10	33		T11	39		T55	6
valid_sources[0x1d]	3317	1		T16	1		T19	1		T10	3
valid_sources[0x1e]	3329	1		T10	10		T11	41		T55	3
valid_sources[0x1f]	2708	1		T10	3		T11	39		T55	3
valid_sources[0x20]	2439	1		T10	85		T37	2		T88	1
valid_sources[0x21]	2780	1		T10	69		T11	37		T55	4
valid_sources[0x22]	2456	1		T19	1		T10	72		T11	36
valid_sources[0x23]	2700	1		T10	35		T11	47		T55	1
valid_sources[0x24]	2992	1		T10	111		T11	37		T55	4
valid_sources[0x25]	3214	1		T10	22		T11	41		T153	1
valid_sources[0x26]	3200	1		T10	122		T38	3		T11	52
valid_sources[0x27]	3615	1		T10	77		T11	54		T153	1
valid_sources[0x28]	2969	1		T10	15		T11	42		T51	1
valid_sources[0x29]	2562	1		T3	1		T10	25		T11	27
valid_sources[0x2a]	3599	1		T10	85		T11	41		T55	3
valid_sources[0x2b]	2525	1		T16	1		T10	47		T37	2
valid_sources[0x2c]	2814	1		T10	75		T11	42		T55	4
valid_sources[0x2d]	2794	1		T10	30		T54	1		T11	59
valid_sources[0x2e]	2521	1		T10	72		T11	46		T55	2
valid_sources[0x2f]	2882	1		T10	29		T35	13		T54	1
valid_sources[0x30]	2817	1		T10	16		T14	1		T23	1
valid_sources[0x31]	3848	1		T10	6		T54	1		T11	41
valid_sources[0x32]	2529	1		T10	44		T87	2		T11	47
valid_sources[0x33]	2935	1		T10	97		T11	37		T7	1
valid_sources[0x34]	3436	1		T10	63		T87	1		T11	32
valid_sources[0x35]	3087	1		T2	1		T10	57		T11	42
valid_sources[0x36]	3087	1		T10	10		T54	1		T11	33
valid_sources[0x37]	2691	1		T3	1		T10	13		T11	51
valid_sources[0x38]	3270	1		T10	4		T11	26		T44	11
valid_sources[0x39]	2984	1		T10	142		T11	51		T55	6
valid_sources[0x3a]	2601	1		T19	1		T10	13		T54	1
valid_sources[0x3b]	2839	1		T10	38		T11	32		T55	3
valid_sources[0x3c]	2861	1		T19	1		T10	87		T11	39
valid_sources[0x3d]	2948	1		T13	1		T18	1		T10	52
valid_sources[0x3e]	2940	1		T16	1		T10	130		T11	46
valid_sources[0x3f]	6409	1		T19	1		T10	6		T11	47
valid_sources[0x40]	3385	1		T10	142		T14	5		T11	48
valid_sources[0x41]	3182	1		T10	11		T88	1		T11	36
valid_sources[0x42]	2822	1		T10	79		T11	46		T55	5
valid_sources[0x43]	2617	1		T10	16		T54	1		T11	39
valid_sources[0x44]	3017	1		T2	5		T10	38		T11	52
valid_sources[0x45]	3101	1		T10	13		T11	42		T55	7
valid_sources[0x46]	2686	1		T19	1		T10	43		T88	1
valid_sources[0x47]	2637	1		T18	1		T19	1		T10	3
valid_sources[0x48]	2765	1		T10	12		T26	3		T11	39
valid_sources[0x49]	3989	1		T10	24		T85	1		T11	55
valid_sources[0x4a]	2669	1		T10	11		T11	38		T51	1
valid_sources[0x4b]	3409	1		T19	1		T10	5		T11	53
valid_sources[0x4c]	2639	1		T10	84		T11	40		T7	1
valid_sources[0x4d]	3086	1		T15	12		T10	10		T11	42
valid_sources[0x4e]	2884	1		T10	37		T11	43		T55	4
valid_sources[0x4f]	2922	1		T10	44		T11	34		T55	3
valid_sources[0x50]	3713	1		T10	10		T23	1		T11	58
valid_sources[0x51]	3159	1		T3	2		T10	37		T11	33
valid_sources[0x52]	3155	1		T10	113		T87	1		T11	39
valid_sources[0x53]	3751	1		T10	18		T23	1		T11	47
valid_sources[0x54]	3361	1		T17	1		T10	8		T11	39
valid_sources[0x55]	3583	1		T2	1		T10	49		T11	40
valid_sources[0x56]	3143	1		T10	81		T11	33		T55	3
valid_sources[0x57]	3159	1		T10	41		T11	40		T55	4
valid_sources[0x58]	2782	1		T10	5		T11	34		T55	1
valid_sources[0x59]	3001	1		T19	1		T10	11		T11	40
valid_sources[0x5a]	3623	1		T10	60		T11	52		T55	4
valid_sources[0x5b]	3622	1		T10	36		T11	33		T55	10
valid_sources[0x5c]	2894	1		T10	39		T85	1		T11	44
valid_sources[0x5d]	4587	1		T10	60		T87	2		T11	46
valid_sources[0x5e]	2935	1		T10	97		T11	36		T55	4
valid_sources[0x5f]	2793	1		T10	49		T11	38		T55	6
valid_sources[0x60]	3112	1		T2	1		T3	1		T10	88
valid_sources[0x61]	3142	1		T10	71		T11	49		T55	5
valid_sources[0x62]	2802	1		T10	42		T11	37		T55	3
valid_sources[0x63]	2512	1		T13	2		T10	112		T87	1
valid_sources[0x64]	3425	1		T10	10		T11	49		T55	3
valid_sources[0x65]	2670	1		T13	1		T10	28		T11	48
valid_sources[0x66]	3390	1		T10	94		T11	42		T153	1
valid_sources[0x67]	2789	1		T10	141		T11	46		T55	4
valid_sources[0x68]	2607	1		T10	11		T87	1		T11	43
valid_sources[0x69]	2561	1		T10	54		T11	37		T55	7
valid_sources[0x6a]	3266	1		T10	66		T30	6		T11	45
valid_sources[0x6b]	3210	1		T19	1		T10	23		T11	47
valid_sources[0x6c]	2922	1		T10	31		T37	1		T38	1
valid_sources[0x6d]	2804	1		T10	10		T11	37		T55	4
valid_sources[0x6e]	3131	1		T10	5		T11	28		T55	7
valid_sources[0x6f]	3159	1		T10	33		T11	40		T55	6
valid_sources[0x70]	3036	1		T10	8		T11	39		T55	2
valid_sources[0x71]	3067	1		T10	20		T11	48		T55	3
valid_sources[0x72]	2823	1		T10	21		T85	1		T11	46
valid_sources[0x73]	2954	1		T10	21		T11	38		T55	3
valid_sources[0x74]	3073	1		T10	45		T29	3		T11	46
valid_sources[0x75]	2554	1		T19	1		T10	64		T11	34
valid_sources[0x76]	3379	1		T10	71		T11	39		T275	2
valid_sources[0x77]	2773	1		T10	35		T88	3		T40	10
valid_sources[0x78]	2696	1		T10	16		T11	46		T51	1
valid_sources[0x79]	2626	1		T10	7		T11	34		T55	4
valid_sources[0x7a]	3395	1		T10	55		T11	43		T55	7
valid_sources[0x7b]	3050	1		T19	1		T10	4		T11	55
valid_sources[0x7c]	3237	1		T10	70		T11	40		T7	2
valid_sources[0x7d]	2868	1		T10	55		T88	2		T11	40
valid_sources[0x7e]	2794	1		T10	48		T14	2		T11	44
valid_sources[0x7f]	6500	1		T10	6		T11	32		T275	2
valid_sources[0x80]	3191	1		T16	1		T10	8		T11	40

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

295151

1

T1

1

T2

8

T3

2

values[0x0]

all_enables

biggest_size

113801

1

T1

2

T2

2

T3

3

values[0x1]

all_enables

biggest_size

107147

1

T1

3

T2

3

T3

3