Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	319903	1		T1	4		T2	3		T3	4
full_word	517190	1		T1	6		T2	13		T3	8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	836873	1		T1	10		T2	16		T3	12
auto[TlIntgErrCmd]	70	1		T58	4		T59	3		T206	3
auto[TlIntgErrData]	82	1		T58	6		T59	5		T206	5
auto[TlIntgErrBoth]	68	1		T59	2		T206	2		T223	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	553557	1		T1	3		T2	11		T3	4
auto[1]	283536	1		T1	7		T2	5		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	258143	1		T1	2		T2	3		T3	2
auto[TlIntgErrNone]	partial	auto[1]	61559	1		T1	2		T3	2		T15	2
auto[TlIntgErrNone]	full_word	auto[0]	295318	1		T1	1		T2	8		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	221853	1		T1	5		T2	5		T3	6
auto[TlIntgErrCmd]	partial	auto[0]	22	1		T58	1		T59	1		T206	1
auto[TlIntgErrCmd]	partial	auto[1]	43	1		T58	3		T59	2		T206	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T223	1		T267	1		T268	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T223	1		T269	1		-	-
auto[TlIntgErrData]	partial	auto[0]	37	1		T58	4		T59	2		T206	4
auto[TlIntgErrData]	partial	auto[1]	37	1		T58	2		T59	3		T206	1
auto[TlIntgErrData]	full_word	auto[0]	5	1		T248	1		T205	1		T269	2
auto[TlIntgErrData]	full_word	auto[1]	3	1		T270	1		T251	1		T271	1
auto[TlIntgErrBoth]	partial	auto[0]	24	1		T206	1		T223	1		T248	1
auto[TlIntgErrBoth]	partial	auto[1]	38	1		T59	2		T206	1		T223	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T205	2		T272	1		T273	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T253	1		-	-		-	-