Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.77	92.59	67.16	92.43		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	520500413	13037	0	0
ep_in_enable_rd_A	520500413	2203	0	0
ep_out_enable_rd_A	520500413	1692	0	0
in_iso_rd_A	520500413	2474	0	0
intr_enable_rd_A	520500413	3300	0	0
out_iso_rd_A	520500413	2133	0	0
phy_config_rd_A	520500413	1496	0	0
phy_pins_drive_rd_A	520500413	1911	0	0
rxenable_setup_rd_A	520500413	2298	0	0
set_nak_out_rd_A	520500413	1925	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	13037	0	0
T58	9645	1	0	0
T59	14208	3	0	0
T60	7979	12	0	0
T98	2391	9	0	0
T100	4231	10	0	0
T203	4805	798	0	0
T204	2889	427	0	0
T206	12539	3	0	0
T211	3381	334	0	0
T212	6927	24	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	2203	0	0
T60	7979	75	0	0
T64	3043	5	0	0
T66	8682	10	0	0
T100	4231	6	0	0
T241	4358	31	0	0
T247	9407	41	0	0
T248	15750	184	0	0
T249	7193	70	0	0
T250	16574	48	0	0
T251	16077	281	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	1692	0	0
T60	7979	28	0	0
T64	3043	8	0	0
T66	8682	21	0	0
T100	4231	5	0	0
T218	4870	25	0	0
T221	4041	2	0	0
T240	2166	37	0	0
T241	4358	3	0	0
T247	9407	7	0	0
T248	15750	176	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	2474	0	0
T60	7979	22	0	0
T66	8682	14	0	0
T100	4231	14	0	0
T218	4870	26	0	0
T221	4041	25	0	0
T240	2166	13	0	0
T241	4358	15	0	0
T247	9407	35	0	0
T248	15750	297	0	0
T249	7193	72	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	3300	0	0
T60	7979	171	0	0
T64	3043	10	0	0
T66	8682	5	0	0
T67	2691	27	0	0
T70	2708	31	0	0
T71	1597	10	0	0
T100	4231	9	0	0
T221	4041	44	0	0
T247	9407	6	0	0
T252	2249	22	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	2133	0	0
T60	7979	45	0	0
T64	3043	1	0	0
T66	8682	13	0	0
T100	4231	5	0	0
T221	4041	3	0	0
T240	2166	6	0	0
T247	9407	4	0	0
T248	15750	378	0	0
T249	7193	56	0	0
T250	16574	8	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	1496	0	0
T60	7979	53	0	0
T64	3043	8	0	0
T66	8682	23	0	0
T100	4231	5	0	0
T218	4870	6	0	0
T221	4041	8	0	0
T240	2166	2	0	0
T241	4358	14	0	0
T247	9407	1	0	0
T248	15750	56	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	1911	0	0
T60	7979	32	0	0
T64	3043	1	0	0
T66	8682	24	0	0
T100	4231	31	0	0
T218	4870	3	0	0
T221	4041	14	0	0
T240	2166	4	0	0
T241	4358	24	0	0
T247	9407	31	0	0
T248	15750	180	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	2298	0	0
T60	7979	109	0	0
T66	8682	32	0	0
T100	4231	43	0	0
T221	4041	17	0	0
T240	2166	2	0	0
T241	4358	28	0	0
T247	9407	57	0	0
T248	15750	209	0	0
T249	7193	60	0	0
T250	16574	10	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	1925	0	0
T60	7979	48	0	0
T64	3043	5	0	0
T66	8682	9	0	0
T100	4231	12	0	0
T218	4870	23	0	0
T221	4041	6	0	0
T241	4358	2	0	0
T247	9407	48	0	0
T248	15750	241	0	0
T249	7193	109	0	0