Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.91	100.00	67.63			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_rxfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.usbdev_avsetupfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.usbdev_avoutfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo	92.19	100.00	68.75			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47	95.12	77.78			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.77	92.59	67.16	92.43		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	86.51	92.59	90.00			76.92

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.77	92.59	67.16	92.43		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.77	92.59	67.16	92.43		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.62	100.00

tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	LINE
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.75	75.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T85,T86
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T15,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T19,T85,T87
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T16

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T15,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T15,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T19,T85,T86
1	0	Covered	T2,T15,T16
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T15,T16
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
91.07	64.29

tb.dut.usbdev_avsetupfifo

SCORE	COND
91.07	64.29

tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T55,T56,T57
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T15

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.usbdev_rxfifo

SCORE	COND
92.19	68.75

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T15
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T15
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T15,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T15,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T15,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T16
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
90.62	100.00

tb.dut.usbdev_rxfifo

SCORE	BRANCH
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	BRANCH
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T15

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	452323072	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	447492630	0	0
gen_passthru_fifo.paramCheckPass	8880	8880	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	452323072	0	0
T1	2416896	400445	0	0
T2	4427929	400990	0	0
T3	4422935	400647	0	0
T10	1349748	532134	0	0
T13	18733	134	0	0
T14	2411862	0	0	0
T15	4429018	400738	0	0
T16	4425685	400460	0	0
T17	4824732	400688	0	0
T18	4850472	401334	0	0
T19	4854060	401772	0	0
T23	403257	401922	0	0
T28	404665	80	0	0
T34	402270	400447	0	0
T35	404832	401393	0	0
T50	0	400720	0	0
T54	402678	10	0	0
T55	0	2396	0	0
T56	0	4988	0	0
T85	0	92	0	0
T87	0	60	0	0
T88	0	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4833792	4833072	0	0
T2	4830468	4829652	0	0
T3	4825020	4823100	0	0
T10	1349748	1349676	0	0
T13	20436	19056	0	0
T15	4831656	4830708	0	0
T16	4828020	4827276	0	0
T17	4824732	4823628	0	0
T18	4850472	4849860	0	0
T19	4854060	4852944	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4833792	4833072	0	0
T2	4830468	4829652	0	0
T3	4825020	4823100	0	0
T10	1349748	1349676	0	0
T13	20436	19056	0	0
T15	4831656	4830708	0	0
T16	4828020	4827276	0	0
T17	4824732	4823628	0	0
T18	4850472	4849860	0	0
T19	4854060	4852944	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4833792	4833072	0	0
T2	4830468	4829652	0	0
T3	4825020	4823100	0	0
T10	1349748	1349676	0	0
T13	20436	19056	0	0
T15	4831656	4830708	0	0
T16	4828020	4827276	0	0
T17	4824732	4823628	0	0
T18	4850472	4849860	0	0
T19	4854060	4852944	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	447492630	0	0
T1	805632	400405	0	0
T2	2012695	400926	0	0
T3	2010425	400599	0	0
T10	674874	483278	0	0
T13	8515	0	0	0
T14	1607908	0	0	0
T15	2013190	400690	0	0
T16	2011675	400412	0	0
T17	2412366	400660	0	0
T18	2425236	401282	0	0
T19	2427030	401474	0	0
T23	403257	401922	0	0
T28	404665	48	0	0
T34	402270	400447	0	0
T35	404832	401393	0	0
T50	0	400720	0	0
T54	402678	6	0	0
T55	0	2396	0	0
T56	0	4988	0	0
T85	0	59	0	0
T87	0	36	0	0
T88	0	3	0	0
T89	0	400648	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	8880	8880	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T10	6	6	0	0
T13	6	6	0	0
T15	6	6	0	0
T16	6	6	0	0
T17	6	6	0	0
T18	6	6	0	0
T19	6	6	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T15
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T15
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T15

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519203803	2231913	0	0
DepthKnown_A	519203803	519085709	0	0
RvalidKnown_A	519203803	519085709	0	0
WreadyKnown_A	519203803	519085709	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519203803	2231913	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	2231913	0	0
T1	402816	1357	0	0
T2	402539	113	0	0
T3	402085	0	0	0
T10	112479	33228	0	0
T13	1703	0	0	0
T15	402638	100	0	0
T16	402335	96	0	0
T17	402061	893	0	0
T18	404206	99	0	0
T19	404505	198	0	0
T34	0	100	0	0
T35	0	107	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	2231913	0	0
T1	402816	1357	0	0
T2	402539	113	0	0
T3	402085	0	0	0
T10	112479	33228	0	0
T13	1703	0	0	0
T15	402638	100	0	0
T16	402335	96	0	0
T17	402061	893	0	0
T18	404206	99	0	0
T19	404505	198	0	0
T34	0	100	0	0
T35	0	107	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T15,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T15,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T15,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519203803	202539	0	0
DepthKnown_A	519203803	519085709	0	0
RvalidKnown_A	519203803	519085709	0	0
WreadyKnown_A	519203803	519085709	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519203803	202539	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	202539	0	0
T2	402539	6	0	0
T3	402085	0	0	0
T10	112479	4305	0	0
T13	1703	0	0	0
T14	401977	0	0	0
T15	402638	2	0	0
T16	402335	1	0	0
T17	402061	0	0	0
T18	404206	0	0	0
T19	404505	7	0	0
T28	0	16	0	0
T54	0	2	0	0
T85	0	7	0	0
T87	0	12	0	0
T88	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	202539	0	0
T2	402539	6	0	0
T3	402085	0	0	0
T10	112479	4305	0	0
T13	1703	0	0	0
T14	401977	0	0	0
T15	402638	2	0	0
T16	402335	1	0	0
T17	402061	0	0	0
T18	404206	0	0	0
T19	404505	7	0	0
T28	0	16	0	0
T54	0	2	0	0
T85	0	7	0	0
T87	0	12	0	0
T88	0	1	0	0

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T55,T56,T57
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T19,T23

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T17,T19,T23

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T17,T19,T23
1	1	0	Not Covered
1	1	1	Covered	T17,T19,T23

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T17,T19,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519203803	60582695	0	0
DepthKnown_A	519203803	519085709	0	0
RvalidKnown_A	519203803	519085709	0	0
WreadyKnown_A	519203803	519085709	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519203803	60582695	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	60582695	0	0
T10	112479	0	0	0
T14	401977	0	0	0
T17	402061	400660	0	0
T18	404206	0	0	0
T19	404505	400483	0	0
T23	403257	401922	0	0
T28	404665	0	0	0
T34	402270	0	0	0
T35	404832	0	0	0
T50	0	400720	0	0
T54	402678	0	0	0
T55	0	2396	0	0
T56	0	4988	0	0
T89	0	400648	0	0
T90	0	401721	0	0
T91	0	400696	0	0
T92	0	400599	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	60582695	0	0
T10	112479	0	0	0
T14	401977	0	0	0
T17	402061	400660	0	0
T18	404206	0	0	0
T19	404505	400483	0	0
T23	403257	401922	0	0
T28	404665	0	0	0
T34	402270	0	0	0
T35	404832	0	0	0
T50	0	400720	0	0
T54	402678	0	0	0
T55	0	2396	0	0
T56	0	4988	0	0
T89	0	400648	0	0
T90	0	401721	0	0
T91	0	400696	0	0
T92	0	400599	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T55,T56,T57
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519203803	383502364	0	0
DepthKnown_A	519203803	519085709	0	0
RvalidKnown_A	519203803	519085709	0	0
WreadyKnown_A	519203803	519085709	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519203803	383502364	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	383502364	0	0
T1	402816	400405	0	0
T2	402539	400908	0	0
T3	402085	400599	0	0
T10	112479	467245	0	0
T13	1703	0	0	0
T15	402638	400684	0	0
T16	402335	400409	0	0
T17	402061	0	0	0
T18	404206	401282	0	0
T19	404505	914	0	0
T34	0	400447	0	0
T35	0	401393	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	383502364	0	0
T1	402816	400405	0	0
T2	402539	400908	0	0
T3	402085	400599	0	0
T10	112479	467245	0	0
T13	1703	0	0	0
T15	402638	400684	0	0
T16	402335	400409	0	0
T17	402061	0	0	0
T18	404206	401282	0	0
T19	404505	914	0	0
T34	0	400447	0	0
T35	0	401393	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T15,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T19,T85,T87
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T15,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T15,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519203803	609396	0	0
DepthKnown_A	519203803	519085709	0	0
RvalidKnown_A	519203803	519085709	0	0
WreadyKnown_A	519203803	519085709	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519203803	609396	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	609396	0	0
T2	402539	6	0	0
T3	402085	0	0	0
T10	112479	7423	0	0
T13	1703	0	0	0
T14	401977	0	0	0
T15	402638	2	0	0
T16	402335	1	0	0
T17	402061	0	0	0
T18	404206	0	0	0
T19	404505	44	0	0
T28	0	16	0	0
T54	0	2	0	0
T85	0	26	0	0
T87	0	12	0	0
T88	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	609396	0	0
T2	402539	6	0	0
T3	402085	0	0	0
T10	112479	7423	0	0
T13	1703	0	0	0
T14	401977	0	0	0
T15	402638	2	0	0
T16	402335	1	0	0
T17	402061	0	0	0
T18	404206	0	0	0
T19	404505	44	0	0
T28	0	16	0	0
T54	0	2	0	0
T85	0	26	0	0
T87	0	12	0	0
T88	0	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T85,T86
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T15,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T19,T85,T87
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T16

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T15,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T15,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T19,T85,T86
1	0	Covered	T2,T15,T16
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T15,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T15,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519203803	363723	0	0
DepthKnown_A	519203803	519085709	0	0
RvalidKnown_A	519203803	519085709	0	0
WreadyKnown_A	519203803	519085709	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519203803	363723	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	363723	0	0
T2	402539	6	0	0
T3	402085	0	0	0
T10	112479	4305	0	0
T13	1703	0	0	0
T14	401977	0	0	0
T15	402638	2	0	0
T16	402335	1	0	0
T17	402061	0	0	0
T18	404206	0	0	0
T19	404505	26	0	0
T28	0	16	0	0
T54	0	2	0	0
T85	0	26	0	0
T87	0	12	0	0
T88	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	519085709	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519203803	363723	0	0
T2	402539	6	0	0
T3	402085	0	0	0
T10	112479	4305	0	0
T13	1703	0	0	0
T14	401977	0	0	0
T15	402638	2	0	0
T16	402335	1	0	0
T17	402061	0	0	0
T18	404206	0	0	0
T19	404505	26	0	0
T28	0	16	0	0
T54	0	2	0	0
T85	0	26	0	0
T87	0	12	0	0
T88	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	520500413	1031330	0	0
DepthKnown_A	520500413	520340983	0	0
RvalidKnown_A	520500413	520340983	0	0
WreadyKnown_A	520500413	520340983	0	0
gen_passthru_fifo.paramCheckPass	1480	1480	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	1031330	0	0
T1	402816	10	0	0
T2	402539	16	0	0
T3	402085	12	0	0
T10	112479	13291	0	0
T13	1703	11	0	0
T15	402638	12	0	0
T16	402335	12	0	0
T17	402061	7	0	0
T18	404206	13	0	0
T19	404505	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1480	1480	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	520500413	1417034	0	0
DepthKnown_A	520500413	520340983	0	0
RvalidKnown_A	520500413	520340983	0	0
WreadyKnown_A	520500413	520340983	0	0
gen_passthru_fifo.paramCheckPass	1480	1480	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	1417034	0	0
T1	402816	10	0	0
T2	402539	16	0	0
T3	402085	12	0	0
T10	112479	11855	0	0
T13	1703	56	0	0
T15	402638	12	0	0
T16	402335	12	0	0
T17	402061	7	0	0
T18	404206	13	0	0
T19	404505	116	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1480	1480	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	520500413	376644	0	0
DepthKnown_A	520500413	520340983	0	0
RvalidKnown_A	520500413	520340983	0	0
WreadyKnown_A	520500413	520340983	0	0
gen_passthru_fifo.paramCheckPass	1480	1480	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	376644	0	0
T2	402539	6	0	0
T3	402085	0	0	0
T10	112479	7423	0	0
T13	1703	0	0	0
T14	401977	0	0	0
T15	402638	2	0	0
T16	402335	1	0	0
T17	402061	0	0	0
T18	404206	0	0	0
T19	404505	12	0	0
T28	0	16	0	0
T54	0	2	0	0
T85	0	7	0	0
T87	0	12	0	0
T88	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1480	1480	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	520500413	670471	0	0
DepthKnown_A	520500413	520340983	0	0
RvalidKnown_A	520500413	520340983	0	0
WreadyKnown_A	520500413	520340983	0	0
gen_passthru_fifo.paramCheckPass	1480	1480	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	670471	0	0
T2	402539	6	0	0
T3	402085	0	0	0
T10	112479	7423	0	0
T13	1703	0	0	0
T14	401977	0	0	0
T15	402638	2	0	0
T16	402335	1	0	0
T17	402061	0	0	0
T18	404206	0	0	0
T19	404505	44	0	0
T28	0	16	0	0
T54	0	2	0	0
T85	0	26	0	0
T87	0	12	0	0
T88	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1480	1480	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	520500413	588400	0	0
DepthKnown_A	520500413	520340983	0	0
RvalidKnown_A	520500413	520340983	0	0
WreadyKnown_A	520500413	520340983	0	0
gen_passthru_fifo.paramCheckPass	1480	1480	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	588400	0	0
T1	402816	10	0	0
T2	402539	10	0	0
T3	402085	12	0	0
T10	112479	4432	0	0
T13	1703	11	0	0
T15	402638	10	0	0
T16	402335	11	0	0
T17	402061	7	0	0
T18	404206	13	0	0
T19	404505	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1480	1480	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	520500413	746563	0	0
DepthKnown_A	520500413	520340983	0	0
RvalidKnown_A	520500413	520340983	0	0
WreadyKnown_A	520500413	520340983	0	0
gen_passthru_fifo.paramCheckPass	1480	1480	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	746563	0	0
T1	402816	10	0	0
T2	402539	10	0	0
T3	402085	12	0	0
T10	112479	4432	0	0
T13	1703	56	0	0
T15	402638	10	0	0
T16	402335	11	0	0
T17	402061	7	0	0
T18	404206	13	0	0
T19	404505	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520500413	520340983	0	0
T1	402816	402756	0	0
T2	402539	402471	0	0
T3	402085	401925	0	0
T10	112479	112473	0	0
T13	1703	1588	0	0
T15	402638	402559	0	0
T16	402335	402273	0	0
T17	402061	401969	0	0
T18	404206	404155	0	0
T19	404505	404412	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1480	1480	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0