Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	278562	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	489887	1		T1	4		T2	6		T3	7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	487426	1		T1	2		T2	4		T3	3
values[0x0]	139899	1		T1	4		T2	5		T3	2
values[0x1]	141124	1		T1	2		T2	2		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	211202	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	557247	1		T1	5		T2	11		T3	8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2949	1		T34	1		T51	5		T13	45
valid_sources[0x01]	2640	1		T51	3		T13	38		T21	7
valid_sources[0x02]	2540	1		T51	2		T13	45		T52	6
valid_sources[0x03]	2532	1		T3	1		T51	3		T13	39
valid_sources[0x04]	2809	1		T51	5		T13	43		T116	3
valid_sources[0x05]	2804	1		T51	3		T40	1		T13	41
valid_sources[0x06]	2416	1		T13	48		T49	1		T52	3
valid_sources[0x07]	3012	1		T51	3		T13	39		T288	1
valid_sources[0x08]	2568	1		T51	4		T13	40		T52	3
valid_sources[0x09]	2434	1		T51	5		T13	44		T289	9
valid_sources[0x0a]	2389	1		T51	7		T13	38		T214	4
valid_sources[0x0b]	2784	1		T51	1		T13	45		T48	1
valid_sources[0x0c]	2591	1		T51	2		T13	48		T42	1
valid_sources[0x0d]	2375	1		T51	3		T13	37		T8	1
valid_sources[0x0e]	2374	1		T19	2		T51	3		T13	48
valid_sources[0x0f]	3633	1		T33	1		T51	2		T38	1
valid_sources[0x10]	3406	1		T2	1		T51	8		T13	42
valid_sources[0x11]	2684	1		T51	2		T13	44		T290	1
valid_sources[0x12]	2731	1		T51	4		T13	47		T8	2
valid_sources[0x13]	3223	1		T34	1		T19	1		T51	6
valid_sources[0x14]	2687	1		T51	8		T13	40		T290	1
valid_sources[0x15]	2557	1		T3	1		T13	44		T52	1
valid_sources[0x16]	2446	1		T51	9		T13	53		T52	2
valid_sources[0x17]	2979	1		T33	1		T51	6		T13	36
valid_sources[0x18]	2590	1		T51	3		T13	51		T143	1
valid_sources[0x19]	2724	1		T51	5		T13	49		T216	3
valid_sources[0x1a]	3874	1		T51	3		T13	34		T125	1
valid_sources[0x1b]	3168	1		T51	2		T39	2		T13	44
valid_sources[0x1c]	3530	1		T51	3		T13	25		T52	2
valid_sources[0x1d]	2549	1		T51	4		T38	2		T13	33
valid_sources[0x1e]	2500	1		T51	2		T39	5		T13	44
valid_sources[0x1f]	2771	1		T51	4		T13	40		T52	1
valid_sources[0x20]	6853	1		T19	1		T51	2		T13	35
valid_sources[0x21]	2861	1		T51	3		T13	46		T52	4
valid_sources[0x22]	2376	1		T51	2		T87	1		T13	37
valid_sources[0x23]	2832	1		T51	3		T13	36		T52	5
valid_sources[0x24]	6088	1		T51	3		T13	55		T116	1
valid_sources[0x25]	2513	1		T51	8		T13	32		T52	2
valid_sources[0x26]	2918	1		T51	1		T13	29		T264	1
valid_sources[0x27]	4008	1		T12	1		T51	3		T13	50
valid_sources[0x28]	2685	1		T19	1		T51	2		T13	45
valid_sources[0x29]	2874	1		T19	1		T51	4		T13	58
valid_sources[0x2a]	2751	1		T51	3		T13	29		T52	3
valid_sources[0x2b]	2833	1		T33	1		T51	5		T13	57
valid_sources[0x2c]	3035	1		T51	2		T40	1		T13	40
valid_sources[0x2d]	2704	1		T51	6		T13	52		T52	4
valid_sources[0x2e]	2483	1		T51	1		T38	2		T13	40
valid_sources[0x2f]	2523	1		T19	2		T51	1		T13	47
valid_sources[0x30]	2459	1		T34	1		T51	5		T13	45
valid_sources[0x31]	3440	1		T51	3		T13	42		T84	1
valid_sources[0x32]	2807	1		T51	3		T13	35		T52	1
valid_sources[0x33]	2897	1		T51	2		T13	35		T264	1
valid_sources[0x34]	2657	1		T51	2		T13	39		T263	7
valid_sources[0x35]	2691	1		T51	2		T13	52		T45	1
valid_sources[0x36]	2534	1		T51	4		T13	49		T82	2
valid_sources[0x37]	2749	1		T19	1		T51	7		T13	49
valid_sources[0x38]	2802	1		T51	5		T13	45		T52	2
valid_sources[0x39]	3106	1		T18	1		T51	4		T13	32
valid_sources[0x3a]	2390	1		T51	3		T13	51		T48	1
valid_sources[0x3b]	3348	1		T2	1		T40	1		T13	58
valid_sources[0x3c]	2566	1		T51	3		T13	45		T45	1
valid_sources[0x3d]	2761	1		T51	5		T13	52		T84	1
valid_sources[0x3e]	2714	1		T51	4		T38	2		T13	43
valid_sources[0x3f]	2456	1		T51	5		T13	42		T290	1
valid_sources[0x40]	3327	1		T51	6		T13	45		T27	1
valid_sources[0x41]	2470	1		T2	1		T3	1		T51	2
valid_sources[0x42]	2678	1		T19	1		T51	5		T13	43
valid_sources[0x43]	3140	1		T51	8		T13	42		T291	1
valid_sources[0x44]	5759	1		T51	5		T13	37		T119	2
valid_sources[0x45]	6040	1		T51	1		T13	55		T292	3
valid_sources[0x46]	3628	1		T19	1		T51	1		T13	42
valid_sources[0x47]	3986	1		T10	10		T19	1		T51	2
valid_sources[0x48]	3826	1		T2	1		T19	1		T51	3
valid_sources[0x49]	2588	1		T51	9		T13	43		T52	5
valid_sources[0x4a]	2557	1		T51	2		T13	37		T82	1
valid_sources[0x4b]	2608	1		T19	1		T51	3		T13	35
valid_sources[0x4c]	2748	1		T19	1		T51	3		T13	43
valid_sources[0x4d]	2690	1		T33	1		T51	5		T13	48
valid_sources[0x4e]	2849	1		T13	58		T52	3		T293	1
valid_sources[0x4f]	2491	1		T51	6		T13	31		T160	3
valid_sources[0x50]	2787	1		T51	5		T13	53		T48	1
valid_sources[0x51]	2746	1		T19	1		T51	7		T13	38
valid_sources[0x52]	2634	1		T51	3		T13	40		T52	1
valid_sources[0x53]	2714	1		T51	1		T13	42		T52	1
valid_sources[0x54]	2811	1		T3	1		T33	1		T51	5
valid_sources[0x55]	2476	1		T51	2		T13	45		T52	1
valid_sources[0x56]	3147	1		T19	1		T51	6		T13	39
valid_sources[0x57]	2675	1		T51	3		T13	36		T49	1
valid_sources[0x58]	3252	1		T51	4		T13	51		T263	1
valid_sources[0x59]	2830	1		T2	1		T51	2		T13	47
valid_sources[0x5a]	2815	1		T3	1		T51	8		T13	52
valid_sources[0x5b]	2437	1		T37	14		T51	3		T13	41
valid_sources[0x5c]	3968	1		T51	1		T13	38		T52	1
valid_sources[0x5d]	2691	1		T19	1		T51	3		T39	1
valid_sources[0x5e]	2531	1		T87	1		T13	38		T52	3
valid_sources[0x5f]	2796	1		T12	1		T51	6		T13	45
valid_sources[0x60]	2545	1		T19	1		T51	3		T13	48
valid_sources[0x61]	3944	1		T51	4		T39	1		T13	52
valid_sources[0x62]	2746	1		T16	1		T51	6		T38	3
valid_sources[0x63]	3508	1		T19	1		T51	1		T13	38
valid_sources[0x64]	2517	1		T51	12		T13	37		T45	1
valid_sources[0x65]	2466	1		T51	5		T13	51		T8	2
valid_sources[0x66]	3077	1		T51	3		T87	2		T13	50
valid_sources[0x67]	2692	1		T51	4		T13	52		T83	4
valid_sources[0x68]	2667	1		T19	2		T51	2		T13	48
valid_sources[0x69]	3127	1		T2	1		T51	8		T32	10
valid_sources[0x6a]	2471	1		T51	5		T13	44		T52	3
valid_sources[0x6b]	2485	1		T51	4		T13	49		T52	3
valid_sources[0x6c]	2590	1		T11	10		T51	1		T38	2
valid_sources[0x6d]	2118	1		T51	5		T13	42		T137	3
valid_sources[0x6e]	2564	1		T51	8		T13	44		T29	1
valid_sources[0x6f]	2523	1		T51	4		T13	47		T83	2
valid_sources[0x70]	2962	1		T51	4		T13	46		T52	1
valid_sources[0x71]	2602	1		T51	5		T13	49		T204	12
valid_sources[0x72]	3141	1		T19	1		T51	1		T13	45
valid_sources[0x73]	3937	1		T19	1		T51	1		T87	1
valid_sources[0x74]	2837	1		T34	1		T51	3		T13	49
valid_sources[0x75]	2956	1		T51	3		T13	35		T52	1
valid_sources[0x76]	4198	1		T16	2		T19	1		T51	7
valid_sources[0x77]	4009	1		T51	2		T13	49		T52	1
valid_sources[0x78]	2590	1		T51	2		T13	39		T294	1
valid_sources[0x79]	3602	1		T51	1		T13	34		T119	1
valid_sources[0x7a]	2744	1		T16	1		T51	2		T13	43
valid_sources[0x7b]	2614	1		T19	1		T51	5		T13	39
valid_sources[0x7c]	2928	1		T51	2		T13	55		T48	2
valid_sources[0x7d]	2813	1		T51	3		T13	52		T216	1
valid_sources[0x7e]	2445	1		T36	16		T51	4		T13	44
valid_sources[0x7f]	2494	1		T51	2		T13	25		T52	5
valid_sources[0x80]	2742	1		T13	45		T293	1		T295	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

260571

1

T1

1

T2

1

T3

2

values[0x0]

all_enables

biggest_size

118564

1

T1

2

T2

5

T3

1

values[0x1]

all_enables

biggest_size

110752

1

T1

1

T3

4

T12

2