Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	292959	1		T1	4		T2	5		T3	3
full_word	490832	1		T1	4		T2	6		T3	7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	783481	1		T1	8		T2	11		T3	10
auto[TlIntgErrCmd]	132	1		T55	7		T56	11		T209	2
auto[TlIntgErrData]	84	1		T55	9		T56	2		T209	2
auto[TlIntgErrBoth]	94	1		T55	4		T56	7		T209	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	489296	1		T1	2		T2	4		T3	3
auto[1]	294495	1		T1	6		T2	7		T3	7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	228409	1		T1	1		T2	3		T3	1
auto[TlIntgErrNone]	partial	auto[1]	64263	1		T1	3		T2	2		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	260747	1		T1	1		T2	1		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	230062	1		T1	3		T2	5		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	58	1		T55	4		T56	5		T209	1
auto[TlIntgErrCmd]	partial	auto[1]	66	1		T55	3		T56	6		T209	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T232	1		T280	1		T282	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T283	1		T284	2		T285	1
auto[TlIntgErrData]	partial	auto[0]	32	1		T55	4		T56	1		T209	1
auto[TlIntgErrData]	partial	auto[1]	44	1		T55	4		T56	1		T209	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T55	1		T208	1		T286	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T232	1		T284	1		T287	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1		T55	3		T56	2		T209	2
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T56	4		T209	4		T232	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T56	1		T287	2		T282	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T55	1		T232	1		T235	1