Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.68	92.59	67.16	91.97		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	521465834	11521	0	0
ep_in_enable_rd_A	521465834	5773	0	0
ep_out_enable_rd_A	521465834	5778	0	0
in_iso_rd_A	521465834	4938	0	0
intr_enable_rd_A	521465834	7944	0	0
out_iso_rd_A	521465834	5218	0	0
phy_config_rd_A	521465834	3323	0	0
phy_pins_drive_rd_A	521465834	4533	0	0
rxenable_setup_rd_A	521465834	5508	0	0
set_nak_out_rd_A	521465834	5678	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	11521	0	0
T55	40545	5	0	0
T56	16873	5	0	0
T57	9707	819	0	0
T205	10217	726	0	0
T206	5328	9	0	0
T209	19574	3	0	0
T210	5596	469	0	0
T232	30317	4	0	0
T233	4645	8	0	0
T235	22268	2	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	5773	0	0
T91	2463	49	0	0
T92	4516	40	0	0
T205	10217	2	0	0
T209	19574	299	0	0
T232	30317	435	0	0
T233	4645	45	0	0
T235	22268	123	0	0
T250	17320	214	0	0
T253	8666	45	0	0
T255	3451	41	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	5778	0	0
T91	2463	1	0	0
T92	4516	1	0	0
T209	19574	322	0	0
T232	30317	359	0	0
T233	4645	37	0	0
T235	22268	93	0	0
T250	17320	189	0	0
T253	8666	32	0	0
T255	3451	29	0	0
T267	6688	73	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	4938	0	0
T91	2463	73	0	0
T92	4516	2	0	0
T209	19574	241	0	0
T232	30317	530	0	0
T233	4645	7	0	0
T235	22268	100	0	0
T250	17320	183	0	0
T253	8666	77	0	0
T255	3451	23	0	0
T267	6688	105	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	7944	0	0
T67	1982	31	0	0
T68	1511	5	0	0
T91	2463	81	0	0
T92	4516	13	0	0
T209	19574	326	0	0
T232	30317	891	0	0
T233	4645	38	0	0
T235	22268	208	0	0
T250	17320	177	0	0
T268	1509	16	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	5218	0	0
T91	2463	8	0	0
T92	4516	45	0	0
T209	19574	209	0	0
T232	30317	475	0	0
T233	4645	10	0	0
T235	22268	97	0	0
T250	17320	171	0	0
T253	8666	37	0	0
T255	3451	9	0	0
T267	6688	110	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	3323	0	0
T91	2463	7	0	0
T92	4516	16	0	0
T205	10217	4	0	0
T209	19574	115	0	0
T232	30317	296	0	0
T233	4645	9	0	0
T235	22268	40	0	0
T250	17320	173	0	0
T253	8666	61	0	0
T255	3451	18	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	4533	0	0
T91	2463	3	0	0
T92	4516	32	0	0
T209	19574	187	0	0
T232	30317	390	0	0
T233	4645	4	0	0
T235	22268	122	0	0
T250	17320	156	0	0
T253	8666	52	0	0
T255	3451	37	0	0
T267	6688	17	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	5508	0	0
T91	2463	52	0	0
T92	4516	24	0	0
T209	19574	253	0	0
T232	30317	535	0	0
T233	4645	11	0	0
T235	22268	92	0	0
T250	17320	173	0	0
T253	8666	58	0	0
T255	3451	42	0	0
T267	6688	66	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	5678	0	0
T91	2463	60	0	0
T92	4516	9	0	0
T209	19574	195	0	0
T232	30317	408	0	0
T233	4645	67	0	0
T235	22268	154	0	0
T250	17320	187	0	0
T253	8666	43	0	0
T255	3451	69	0	0
T267	6688	62	0	0