Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.91	100.00	67.63			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_rxfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.usbdev_avsetupfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.usbdev_avoutfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo	92.19	100.00	68.75			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47	95.12	77.78			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.68	92.59	67.16	91.97		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	86.51	92.59	90.00			76.92

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.68	92.59	67.16	91.97		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.68	92.59	67.16	91.97		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.62	100.00

tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	LINE
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.75	75.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T82,T83
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T36,T19

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T16,T36,T19

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T13,T20,T82
1	1	0	Not Covered
1	1	1	Covered	T16,T36,T19

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T36,T19

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T36,T19

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T20,T82,T83
1	0	Covered	T16,T36,T19
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T16,T36,T19
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
91.07	64.29

tb.dut.usbdev_avsetupfifo

SCORE	COND
91.07	64.29

tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T51,T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T11

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.usbdev_rxfifo

SCORE	COND
92.19	68.75

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T36,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T11,T16,T18

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T36,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T36,T19

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T16,T36,T19

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T16,T36,T19

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T16,T36,T19
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T10
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T36,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T16,T36,T19

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T16,T36,T19
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
90.62	100.00

tb.dut.usbdev_rxfifo

SCORE	BRANCH
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	BRANCH
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T10,T11

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	453106075	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	447607250	0	0
gen_passthru_fifo.paramCheckPass	8868	8868	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	453106075	0	0
T1	2007310	401019	0	0
T2	9065	122	0	0
T3	2035830	402525	0	0
T7	12780	114	0	0
T10	2011815	400492	0	0
T11	2017165	400488	0	0
T12	16045	44	0	0
T13	0	28377	0	0
T16	4026230	400779	0	0
T17	4060090	402434	0	0
T18	4047680	400946	0	0
T19	2430552	89	0	0
T20	0	226	0	0
T32	406404	0	0	0
T33	2014915	401949	0	0
T34	2017780	402104	0	0
T36	2013115	401295	0	0
T37	2026970	0	0	0
T38	2422824	0	0	0
T39	402290	0	0	0
T40	403754	0	0	0
T48	0	25	0	0
T49	0	10	0	0
T50	405753	0	0	0
T51	55008	0	0	0
T82	0	156	0	0
T83	0	236	0	0
T84	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4817544	4816488	0	0
T2	21756	19464	0	0
T3	4885992	4884816	0	0
T7	30672	28896	0	0
T10	4828356	4827528	0	0
T11	4841196	4840080	0	0
T12	38508	36576	0	0
T16	4831476	4830828	0	0
T17	4872108	4871424	0	0
T18	4857216	4856532	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4817544	4816488	0	0
T2	21756	19464	0	0
T3	4885992	4884816	0	0
T7	30672	28896	0	0
T10	4828356	4827528	0	0
T11	4841196	4840080	0	0
T12	38508	36576	0	0
T16	4831476	4830828	0	0
T17	4872108	4871424	0	0
T18	4857216	4856532	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4817544	4816488	0	0
T2	21756	19464	0	0
T3	4885992	4884816	0	0
T7	30672	28896	0	0
T10	4828356	4827528	0	0
T11	4841196	4840080	0	0
T12	38508	36576	0	0
T16	4831476	4830828	0	0
T17	4872108	4871424	0	0
T18	4857216	4856532	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	447607250	0	0
T1	401462	400987	0	0
T2	1813	0	0	0
T3	407166	402485	0	0
T7	2556	0	0	0
T10	402363	400452	0	0
T11	403433	400448	0	0
T12	3209	0	0	0
T13	0	14795	0	0
T16	1610492	400731	0	0
T17	1624036	402394	0	0
T18	1619072	400774	0	0
T19	1620368	400715	0	0
T20	0	400545	0	0
T21	0	400797	0	0
T32	406404	0	0	0
T33	1208949	401949	0	0
T34	1210668	402104	0	0
T36	1207869	401283	0	0
T37	1216182	0	0	0
T38	1615216	0	0	0
T39	402290	0	0	0
T40	403754	0	0	0
T48	0	15	0	0
T49	0	6	0	0
T50	405753	0	0	0
T51	36672	7081	0	0
T52	0	1598	0	0
T82	0	100	0	0
T83	0	152	0	0
T84	0	6	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	8868	8868	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T7	6	6	0	0
T10	6	6	0	0
T11	6	6	0	0
T12	6	6	0	0
T16	6	6	0	0
T17	6	6	0	0
T18	6	6	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T11,T16,T18

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T10,T11

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519890750	2300778	0	0
DepthKnown_A	519890750	519773330	0	0
RvalidKnown_A	519890750	519773330	0	0
WreadyKnown_A	519890750	519773330	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519890750	2300778	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	2300778	0	0
T3	407166	3488	0	0
T7	2556	0	0	0
T10	402363	1365	0	0
T11	403433	100	0	0
T12	3209	0	0	0
T16	402623	114	0	0
T17	406009	3242	0	0
T18	404768	100	0	0
T19	0	196	0	0
T33	402983	0	0	0
T34	403556	0	0	0
T36	0	100	0	0
T37	0	2464	0	0
T38	0	1916	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	2300778	0	0
T3	407166	3488	0	0
T7	2556	0	0	0
T10	402363	1365	0	0
T11	403433	100	0	0
T12	3209	0	0	0
T16	402623	114	0	0
T17	406009	3242	0	0
T18	404768	100	0	0
T19	0	196	0	0
T33	402983	0	0	0
T34	403556	0	0	0
T36	0	100	0	0
T37	0	2464	0	0
T38	0	1916	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T36,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T36,T19

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T16,T36,T19

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T16,T36,T19

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T16,T36,T19
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T16,T36,T19

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T16,T36,T19
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519890750	209124	0	0
DepthKnown_A	519890750	519773330	0	0
RvalidKnown_A	519890750	519773330	0	0
WreadyKnown_A	519890750	519773330	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519890750	209124	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	209124	0	0
T13	0	4002	0	0
T16	402623	2	0	0
T17	406009	0	0	0
T18	404768	0	0	0
T19	405092	16	0	0
T20	0	16	0	0
T33	402983	0	0	0
T34	403556	0	0	0
T36	402623	6	0	0
T37	405394	0	0	0
T38	403804	0	0	0
T48	0	5	0	0
T49	0	2	0	0
T51	9168	0	0	0
T82	0	12	0	0
T83	0	16	0	0
T84	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	209124	0	0
T13	0	4002	0	0
T16	402623	2	0	0
T17	406009	0	0	0
T18	404768	0	0	0
T19	405092	16	0	0
T20	0	16	0	0
T33	402983	0	0	0
T34	403556	0	0	0
T36	402623	6	0	0
T37	405394	0	0	0
T38	403804	0	0	0
T48	0	5	0	0
T49	0	2	0	0
T51	9168	0	0	0
T82	0	12	0	0
T83	0	16	0	0
T84	0	2	0	0

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T51,T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T19,T51,T20

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T19,T51,T20

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T19,T51,T20
1	1	0	Not Covered
1	1	1	Covered	T19,T20,T21

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T19,T51,T20
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519890750	60598724	0	0
DepthKnown_A	519890750	519773330	0	0
RvalidKnown_A	519890750	519773330	0	0
WreadyKnown_A	519890750	519773330	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519890750	60598724	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	60598724	0	0
T13	109737	0	0	0
T19	405092	400664	0	0
T20	0	400403	0	0
T21	0	400797	0	0
T29	403376	0	0	0
T32	406404	0	0	0
T38	403804	0	0	0
T39	402290	0	0	0
T40	403754	0	0	0
T46	0	402354	0	0
T50	405753	0	0	0
T51	9168	7081	0	0
T52	0	1598	0	0
T53	0	11036	0	0
T54	0	401942	0	0
T85	0	400508	0	0
T86	0	400681	0	0
T87	406243	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	60598724	0	0
T13	109737	0	0	0
T19	405092	400664	0	0
T20	0	400403	0	0
T21	0	400797	0	0
T29	403376	0	0	0
T32	406404	0	0	0
T38	403804	0	0	0
T39	402290	0	0	0
T40	403754	0	0	0
T46	0	402354	0	0
T50	405753	0	0	0
T51	9168	7081	0	0
T52	0	1598	0	0
T53	0	11036	0	0
T54	0	401942	0	0
T85	0	400508	0	0
T86	0	400681	0	0
T87	406243	0	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T51,T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T11

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519890750	383257885	0	0
DepthKnown_A	519890750	519773330	0	0
RvalidKnown_A	519890750	519773330	0	0
WreadyKnown_A	519890750	519773330	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519890750	383257885	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	383257885	0	0
T1	401462	400987	0	0
T2	1813	0	0	0
T3	407166	402485	0	0
T7	2556	0	0	0
T10	402363	400452	0	0
T11	403433	400448	0	0
T12	3209	0	0	0
T16	402623	400725	0	0
T17	406009	402394	0	0
T18	404768	400774	0	0
T33	0	401949	0	0
T34	0	402104	0	0
T36	0	401265	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	383257885	0	0
T1	401462	400987	0	0
T2	1813	0	0	0
T3	407166	402485	0	0
T7	2556	0	0	0
T10	402363	400452	0	0
T11	403433	400448	0	0
T12	3209	0	0	0
T16	402623	400725	0	0
T17	406009	402394	0	0
T18	404768	400774	0	0
T33	0	401949	0	0
T34	0	402104	0	0
T36	0	401265	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T36,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T36,T19

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T16,T36,T19

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T13,T20,T82
1	1	0	Not Covered
1	1	1	Covered	T16,T36,T19

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T16,T36,T19
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T16,T36,T19

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T16,T36,T19
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519890750	776453	0	0
DepthKnown_A	519890750	519773330	0	0
RvalidKnown_A	519890750	519773330	0	0
WreadyKnown_A	519890750	519773330	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519890750	776453	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	776453	0	0
T13	0	6791	0	0
T16	402623	2	0	0
T17	406009	0	0	0
T18	404768	0	0	0
T19	405092	19	0	0
T20	0	65	0	0
T33	402983	0	0	0
T34	403556	0	0	0
T36	402623	6	0	0
T37	405394	0	0	0
T38	403804	0	0	0
T48	0	5	0	0
T49	0	2	0	0
T51	9168	0	0	0
T82	0	44	0	0
T83	0	68	0	0
T84	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	776453	0	0
T13	0	6791	0	0
T16	402623	2	0	0
T17	406009	0	0	0
T18	404768	0	0	0
T19	405092	19	0	0
T20	0	65	0	0
T33	402983	0	0	0
T34	403556	0	0	0
T36	402623	6	0	0
T37	405394	0	0	0
T38	403804	0	0	0
T48	0	5	0	0
T49	0	2	0	0
T51	9168	0	0	0
T82	0	44	0	0
T83	0	68	0	0
T84	0	2	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T82,T83
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T36,T19

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T16,T36,T19

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T13,T20,T82
1	1	0	Not Covered
1	1	1	Covered	T16,T36,T19

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T36,T19

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T36,T19

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T20,T82,T83
1	0	Covered	T16,T36,T19
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T16,T36,T19
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T36,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T16,T36,T19

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T16,T36,T19
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	519890750	464286	0	0
DepthKnown_A	519890750	519773330	0	0
RvalidKnown_A	519890750	519773330	0	0
WreadyKnown_A	519890750	519773330	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	519890750	464286	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	464286	0	0
T13	0	4002	0	0
T16	402623	2	0	0
T17	406009	0	0	0
T18	404768	0	0	0
T19	405092	16	0	0
T20	0	61	0	0
T33	402983	0	0	0
T34	403556	0	0	0
T36	402623	6	0	0
T37	405394	0	0	0
T38	403804	0	0	0
T48	0	5	0	0
T49	0	2	0	0
T51	9168	0	0	0
T82	0	44	0	0
T83	0	68	0	0
T84	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	519773330	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	519890750	464286	0	0
T13	0	4002	0	0
T16	402623	2	0	0
T17	406009	0	0	0
T18	404768	0	0	0
T19	405092	16	0	0
T20	0	61	0	0
T33	402983	0	0	0
T34	403556	0	0	0
T36	402623	6	0	0
T37	405394	0	0	0
T38	403804	0	0	0
T48	0	5	0	0
T49	0	2	0	0
T51	9168	0	0	0
T82	0	44	0	0
T83	0	68	0	0
T84	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521465834	1002581	0	0
DepthKnown_A	521465834	521294396	0	0
RvalidKnown_A	521465834	521294396	0	0
WreadyKnown_A	521465834	521294396	0	0
gen_passthru_fifo.paramCheckPass	1478	1478	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	1002581	0	0
T1	401462	8	0	0
T2	1813	11	0	0
T3	407166	10	0	0
T7	2556	11	0	0
T10	402363	10	0	0
T11	403433	10	0	0
T12	3209	11	0	0
T16	402623	12	0	0
T17	406009	10	0	0
T18	404768	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1478	1478	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521465834	1784032	0	0
DepthKnown_A	521465834	521294396	0	0
RvalidKnown_A	521465834	521294396	0	0
WreadyKnown_A	521465834	521294396	0	0
gen_passthru_fifo.paramCheckPass	1478	1478	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	1784032	0	0
T1	401462	8	0	0
T2	1813	50	0	0
T3	407166	10	0	0
T7	2556	46	0	0
T10	402363	10	0	0
T11	403433	10	0	0
T12	3209	11	0	0
T16	402623	12	0	0
T17	406009	10	0	0
T18	404768	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1478	1478	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521465834	386879	0	0
DepthKnown_A	521465834	521294396	0	0
RvalidKnown_A	521465834	521294396	0	0
WreadyKnown_A	521465834	521294396	0	0
gen_passthru_fifo.paramCheckPass	1478	1478	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	386879	0	0
T13	0	6791	0	0
T16	402623	2	0	0
T17	406009	0	0	0
T18	404768	0	0	0
T19	405092	19	0	0
T20	0	19	0	0
T33	402983	0	0	0
T34	403556	0	0	0
T36	402623	6	0	0
T37	405394	0	0	0
T38	403804	0	0	0
T48	0	5	0	0
T49	0	2	0	0
T51	9168	0	0	0
T82	0	12	0	0
T83	0	16	0	0
T84	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1478	1478	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521465834	829635	0	0
DepthKnown_A	521465834	521294396	0	0
RvalidKnown_A	521465834	521294396	0	0
WreadyKnown_A	521465834	521294396	0	0
gen_passthru_fifo.paramCheckPass	1478	1478	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	829635	0	0
T13	0	6791	0	0
T16	402623	2	0	0
T17	406009	0	0	0
T18	404768	0	0	0
T19	405092	19	0	0
T20	0	65	0	0
T33	402983	0	0	0
T34	403556	0	0	0
T36	402623	6	0	0
T37	405394	0	0	0
T38	403804	0	0	0
T48	0	5	0	0
T49	0	2	0	0
T51	9168	0	0	0
T82	0	44	0	0
T83	0	68	0	0
T84	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1478	1478	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521465834	541301	0	0
DepthKnown_A	521465834	521294396	0	0
RvalidKnown_A	521465834	521294396	0	0
WreadyKnown_A	521465834	521294396	0	0
gen_passthru_fifo.paramCheckPass	1478	1478	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	541301	0	0
T1	401462	8	0	0
T2	1813	11	0	0
T3	407166	10	0	0
T7	2556	11	0	0
T10	402363	10	0	0
T11	403433	10	0	0
T12	3209	11	0	0
T16	402623	10	0	0
T17	406009	10	0	0
T18	404768	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1478	1478	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	521465834	954397	0	0
DepthKnown_A	521465834	521294396	0	0
RvalidKnown_A	521465834	521294396	0	0
WreadyKnown_A	521465834	521294396	0	0
gen_passthru_fifo.paramCheckPass	1478	1478	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	954397	0	0
T1	401462	8	0	0
T2	1813	50	0	0
T3	407166	10	0	0
T7	2556	46	0	0
T10	402363	10	0	0
T11	403433	10	0	0
T12	3209	11	0	0
T16	402623	10	0	0
T17	406009	10	0	0
T18	404768	71	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	521465834	521294396	0	0
T1	401462	401374	0	0
T2	1813	1622	0	0
T3	407166	407068	0	0
T7	2556	2408	0	0
T10	402363	402294	0	0
T11	403433	403340	0	0
T12	3209	3048	0	0
T16	402623	402569	0	0
T17	406009	405952	0	0
T18	404768	404711	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1478	1478	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0