Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	271830	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	501460	1		T2	6		T3	4		T4	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	488666	1		T2	5		T3	2		T4	3
values[0x0]	141981	1		T2	4		T3	6		T4	3
values[0x1]	142643	1		T2	5		T4	3		T10	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	206428	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	566862	1		T2	8		T3	5		T4	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2351	1		T2	1		T12	2		T49	16
valid_sources[0x01]	2334	1		T12	4		T50	4		T312	9
valid_sources[0x02]	2194	1		T12	4		T49	1		T87	13
valid_sources[0x03]	2226	1		T12	3		T22	8		T44	1
valid_sources[0x04]	2684	1		T49	2		T50	1		T313	2
valid_sources[0x05]	2309	1		T12	4		T30	2		T50	12
valid_sources[0x06]	2549	1		T12	5		T282	1		T35	1
valid_sources[0x07]	2590	1		T12	2		T282	1		T84	19
valid_sources[0x08]	2600	1		T49	13		T91	1		T313	3
valid_sources[0x09]	2976	1		T12	2		T49	5		T197	1
valid_sources[0x0a]	1963	1		T12	1		T91	1		T44	1
valid_sources[0x0b]	2636	1		T314	1		T50	8		T313	2
valid_sources[0x0c]	3992	1		T2	1		T12	304		T49	12
valid_sources[0x0d]	2597	1		T49	1		T50	3		T243	3
valid_sources[0x0e]	2600	1		T12	1		T49	15		T44	2
valid_sources[0x0f]	5795	1		T12	4		T49	2		T50	6
valid_sources[0x10]	3751	1		T12	3		T49	7		T138	1
valid_sources[0x11]	2763	1		T80	1		T283	1		T139	1
valid_sources[0x12]	2574	1		T12	2		T8	8		T91	1
valid_sources[0x13]	3114	1		T12	3		T30	1		T315	1
valid_sources[0x14]	3456	1		T12	4		T49	8		T313	3
valid_sources[0x15]	2828	1		T2	1		T12	2		T50	7
valid_sources[0x16]	2231	1		T134	2		T6	7		T154	4
valid_sources[0x17]	2776	1		T12	3		T49	14		T160	3
valid_sources[0x18]	2634	1		T12	4		T88	5		T82	1
valid_sources[0x19]	3189	1		T28	1		T12	33		T50	8
valid_sources[0x1a]	2844	1		T12	7		T283	1		T87	12
valid_sources[0x1b]	2799	1		T5	1		T12	116		T282	1
valid_sources[0x1c]	2869	1		T12	181		T49	2		T50	5
valid_sources[0x1d]	2774	1		T12	1		T49	17		T44	2
valid_sources[0x1e]	2460	1		T12	4		T283	1		T49	4
valid_sources[0x1f]	2398	1		T28	1		T49	2		T316	1
valid_sources[0x20]	2872	1		T12	1		T49	2		T227	3
valid_sources[0x21]	2479	1		T21	39		T49	11		T50	8
valid_sources[0x22]	3607	1		T37	1		T317	1		T12	1
valid_sources[0x23]	2948	1		T37	4		T12	3		T50	9
valid_sources[0x24]	2401	1		T12	5		T49	9		T127	2
valid_sources[0x25]	2708	1		T318	1		T313	2		T13	31
valid_sources[0x26]	2694	1		T12	5		T49	8		T50	19
valid_sources[0x27]	3583	1		T12	5		T319	1		T50	10
valid_sources[0x28]	2324	1		T50	4		T313	3		T13	41
valid_sources[0x29]	5553	1		T12	283		T39	10		T50	1
valid_sources[0x2a]	2715	1		T5	1		T12	4		T49	1
valid_sources[0x2b]	2298	1		T12	2		T49	1		T91	1
valid_sources[0x2c]	3351	1		T4	5		T28	1		T80	1
valid_sources[0x2d]	2288	1		T5	1		T12	1		T313	1
valid_sources[0x2e]	2255	1		T37	1		T12	7		T50	4
valid_sources[0x2f]	6264	1		T12	126		T49	7		T207	1
valid_sources[0x30]	2536	1		T37	1		T12	1		T82	1
valid_sources[0x31]	3656	1		T12	3		T320	1		T313	6
valid_sources[0x32]	2386	1		T12	1		T27	1		T316	1
valid_sources[0x33]	4081	1		T133	4		T12	2		T48	1250
valid_sources[0x34]	2926	1		T12	1		T316	1		T313	2
valid_sources[0x35]	2767	1		T12	5		T30	1		T49	9
valid_sources[0x36]	2291	1		T12	3		T44	1		T50	7
valid_sources[0x37]	2702	1		T12	72		T50	5		T313	2
valid_sources[0x38]	2645	1		T20	1		T12	2		T49	1
valid_sources[0x39]	2623	1		T32	4		T12	5		T281	3
valid_sources[0x3a]	2407	1		T12	2		T229	4		T49	3
valid_sources[0x3b]	2806	1		T78	13		T12	2		T321	1
valid_sources[0x3c]	2281	1		T28	1		T12	4		T35	1
valid_sources[0x3d]	2435	1		T11	1		T282	1		T49	2
valid_sources[0x3e]	2536	1		T3	8		T313	4		T322	1
valid_sources[0x3f]	2633	1		T2	1		T12	2		T91	1
valid_sources[0x40]	2835	1		T12	54		T49	18		T50	2
valid_sources[0x41]	3125	1		T20	1		T12	455		T49	7
valid_sources[0x42]	2501	1		T20	1		T314	1		T12	2
valid_sources[0x43]	3380	1		T12	4		T49	2		T50	5
valid_sources[0x44]	2666	1		T12	3		T29	1		T282	1
valid_sources[0x45]	2480	1		T12	2		T44	2		T313	4
valid_sources[0x46]	2522	1		T5	1		T20	1		T80	2
valid_sources[0x47]	2122	1		T37	1		T229	1		T25	1
valid_sources[0x48]	2451	1		T12	2		T25	1		T138	1
valid_sources[0x49]	2526	1		T12	2		T35	1		T85	1
valid_sources[0x4a]	2573	1		T134	2		T12	2		T283	1
valid_sources[0x4b]	2264	1		T11	1		T12	4		T91	1
valid_sources[0x4c]	2421	1		T19	4		T32	1		T12	5
valid_sources[0x4d]	2221	1		T50	2		T87	2		T313	5
valid_sources[0x4e]	2510	1		T11	1		T12	1		T323	12
valid_sources[0x4f]	2513	1		T12	155		T29	1		T282	2
valid_sources[0x50]	3148	1		T18	10		T49	2		T85	2
valid_sources[0x51]	2458	1		T12	2		T29	2		T27	1
valid_sources[0x52]	2357	1		T12	3		T49	15		T207	1
valid_sources[0x53]	2324	1		T12	6		T49	3		T190	7
valid_sources[0x54]	2891	1		T79	1		T12	1		T324	9
valid_sources[0x55]	2355	1		T11	1		T12	4		T47	2
valid_sources[0x56]	2315	1		T28	1		T80	1		T12	2
valid_sources[0x57]	2510	1		T4	4		T37	3		T12	3
valid_sources[0x58]	2320	1		T12	4		T49	1		T318	1
valid_sources[0x59]	2607	1		T133	5		T12	8		T225	9
valid_sources[0x5a]	2263	1		T79	4		T314	1		T12	2
valid_sources[0x5b]	5958	1		T11	1		T12	3417		T9	8
valid_sources[0x5c]	3807	1		T17	17		T12	1346		T281	6
valid_sources[0x5d]	2682	1		T33	8		T12	2		T229	1
valid_sources[0x5e]	3044	1		T12	4		T49	18		T325	2
valid_sources[0x5f]	2512	1		T10	13		T49	8		T313	6
valid_sources[0x60]	2634	1		T12	2		T282	1		T49	20
valid_sources[0x61]	2657	1		T12	2		T47	5		T50	3
valid_sources[0x62]	3436	1		T37	1		T12	2		T82	1
valid_sources[0x63]	3113	1		T12	3		T49	5		T50	5
valid_sources[0x64]	3156	1		T2	1		T28	1		T12	2
valid_sources[0x65]	3475	1		T49	3		T50	1		T313	6
valid_sources[0x66]	5788	1		T314	1		T80	1		T12	128
valid_sources[0x67]	2874	1		T12	2		T31	9		T49	3
valid_sources[0x68]	3262	1		T5	1		T12	285		T49	8
valid_sources[0x69]	2405	1		T25	1		T27	1		T325	1
valid_sources[0x6a]	3049	1		T12	206		T49	14		T87	1
valid_sources[0x6b]	2551	1		T12	2		T49	4		T313	2
valid_sources[0x6c]	2277	1		T12	1		T50	6		T313	2
valid_sources[0x6d]	2356	1		T12	3		T38	10		T49	5
valid_sources[0x6e]	2925	1		T47	1		T49	3		T50	1
valid_sources[0x6f]	3065	1		T12	5		T49	20		T160	3
valid_sources[0x70]	2162	1		T80	1		T12	2		T49	4
valid_sources[0x71]	3101	1		T12	3		T50	4		T313	2
valid_sources[0x72]	2556	1		T12	2		T27	1		T23	8
valid_sources[0x73]	2422	1		T134	1		T49	9		T50	4
valid_sources[0x74]	5206	1		T49	12		T91	2		T313	2
valid_sources[0x75]	2776	1		T2	2		T12	2		T49	2
valid_sources[0x76]	2490	1		T12	8		T35	1		T50	4
valid_sources[0x77]	2868	1		T12	3		T30	1		T49	3
valid_sources[0x78]	2337	1		T12	2		T326	8		T87	10
valid_sources[0x79]	6232	1		T12	1		T207	1		T50	3
valid_sources[0x7a]	2481	1		T12	5		T49	2		T50	6
valid_sources[0x7b]	2431	1		T12	3		T49	9		T91	1
valid_sources[0x7c]	3866	1		T49	9		T44	1		T313	1
valid_sources[0x7d]	2131	1		T12	5		T316	1		T139	1
valid_sources[0x7e]	2656	1		T46	19		T12	273		T327	1
valid_sources[0x7f]	2552	1		T81	22		T12	2		T30	1
valid_sources[0x80]	3631	1		T28	1		T35	1		T49	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

266446

1

T2

2

T10

5

T11

2

values[0x0]

all_enables

biggest_size

121259

1

T2

3

T3

4

T4

3

values[0x1]

all_enables

biggest_size

113755

1

T2

1

T10

2

T11

2