Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	285601	1		T2	8		T3	4		T4	6
full_word	502487	1		T2	6		T3	4		T4	3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	787788	1		T2	14		T3	8		T4	9
auto[TlIntgErrCmd]	86	1		T52	7		T211	9		T215	5
auto[TlIntgErrData]	107	1		T52	7		T211	7		T215	3
auto[TlIntgErrBoth]	107	1		T52	6		T211	4		T215	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	490571	1		T2	5		T3	2		T4	3
auto[1]	297517	1		T2	9		T3	6		T4	6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	223803	1		T2	3		T3	2		T4	3
auto[TlIntgErrNone]	partial	auto[1]	61517	1		T2	5		T3	2		T4	3
auto[TlIntgErrNone]	full_word	auto[0]	266637	1		T2	2		T10	5		T11	2
auto[TlIntgErrNone]	full_word	auto[1]	235831	1		T2	4		T3	4		T4	3
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T52	5		T211	1		T215	2
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T52	2		T211	7		T215	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T211	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T214	1		T303	1		T304	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T52	2		T211	3		T215	3
auto[TlIntgErrData]	partial	auto[1]	52	1		T52	5		T211	4		T213	3
auto[TlIntgErrData]	full_word	auto[0]	3	1		T303	2		T305	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1		T306	1		T307	1		T302	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T52	4		T215	1		T213	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T52	2		T211	3		T215	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T211	1		T308	1		T309	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T309	1		T310	1		T311	1