Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.95	92.59	67.16	93.35		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	523818771	10687	0	0
ep_in_enable_rd_A	523818771	3006	0	0
ep_out_enable_rd_A	523818771	2447	0	0
in_iso_rd_A	523818771	2515	0	0
intr_enable_rd_A	523818771	3675	0	0
out_iso_rd_A	523818771	2536	0	0
phy_config_rd_A	523818771	2010	0	0
phy_pins_drive_rd_A	523818771	2220	0	0
rxenable_setup_rd_A	523818771	2474	0	0
set_nak_out_rd_A	523818771	2356	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	10687	0	0
T51	3476	19	0	0
T52	26172	8	0	0
T53	10859	639	0	0
T210	8315	469	0	0
T211	26932	4	0	0
T215	15552	6	0	0
T216	4522	265	0	0
T242	3604	9	0	0
T249	4601	11	0	0
T250	4150	14	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	3006	0	0
T59	50173	239	0	0
T98	21995	71	0	0
T212	8999	29	0	0
T246	3343	6	0	0
T251	7742	54	0	0
T280	2091	2	0	0
T286	20368	30	0	0
T287	104774	692	0	0
T288	34443	562	0	0
T289	3965	14	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	2447	0	0
T59	50173	193	0	0
T98	21995	30	0	0
T212	8999	11	0	0
T251	7742	99	0	0
T268	119363	434	0	0
T280	2091	8	0	0
T286	20368	56	0	0
T287	104774	545	0	0
T288	34443	421	0	0
T289	3965	20	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	2515	0	0
T59	50173	224	0	0
T98	21995	43	0	0
T212	8999	9	0	0
T246	3343	11	0	0
T251	7742	67	0	0
T268	119363	445	0	0
T280	2091	38	0	0
T286	20368	65	0	0
T287	104774	438	0	0
T288	34443	521	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	3675	0	0
T59	50173	215	0	0
T98	21995	67	0	0
T246	3343	7	0	0
T251	7742	112	0	0
T280	2091	5	0	0
T286	20368	47	0	0
T290	1541	26	0	0
T291	2077	21	0	0
T292	3092	17	0	0
T293	3140	13	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	2536	0	0
T59	50173	235	0	0
T98	21995	28	0	0
T212	8999	22	0	0
T246	3343	12	0	0
T251	7742	76	0	0
T280	2091	7	0	0
T286	20368	77	0	0
T287	104774	544	0	0
T288	34443	352	0	0
T289	3965	11	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	2010	0	0
T59	50173	208	0	0
T98	21995	38	0	0
T212	8999	19	0	0
T246	3343	3	0	0
T251	7742	25	0	0
T268	119363	512	0	0
T280	2091	8	0	0
T286	20368	49	0	0
T287	104774	327	0	0
T288	34443	232	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	2220	0	0
T59	50173	214	0	0
T98	21995	42	0	0
T212	8999	28	0	0
T246	3343	9	0	0
T251	7742	12	0	0
T280	2091	3	0	0
T286	20368	60	0	0
T287	104774	380	0	0
T288	34443	316	0	0
T289	3965	10	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	2474	0	0
T59	50173	248	0	0
T98	21995	57	0	0
T212	8999	12	0	0
T246	3343	8	0	0
T251	7742	66	0	0
T280	2091	4	0	0
T286	20368	66	0	0
T287	104774	362	0	0
T288	34443	521	0	0
T289	3965	15	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	2356	0	0
T59	50173	203	0	0
T98	21995	70	0	0
T212	8999	27	0	0
T246	3343	9	0	0
T251	7742	31	0	0
T268	119363	434	0	0
T280	2091	4	0	0
T286	20368	19	0	0
T287	104774	432	0	0
T288	34443	279	0	0