Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.91	100.00	67.63			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_rxfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.usbdev_avsetupfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.usbdev_avoutfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo	92.19	100.00	68.75			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47	95.12	77.78			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.95	92.59	67.16	93.35		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	86.51	92.59	90.00			76.92

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.95	92.59	67.16	93.35		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.95	92.59	67.16	93.35		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	98.55	78.63			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.62	100.00

tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	LINE
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.75	75.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T76,T77,T21
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T10,T17,T46

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T17,T46

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T10,T78,T76
1	1	0	Not Covered
1	1	1	Covered	T10,T17,T46

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T10,T17,T46

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T10,T17,T46

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T76,T77,T21
1	0	Covered	T10,T17,T46
1	1	Covered	T2,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T10,T17,T46
1	Covered	T2,T3,T4

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
91.07	64.29

tb.dut.usbdev_avsetupfifo

SCORE	COND
91.07	64.29

tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T49,T50
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T11

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.usbdev_rxfifo

SCORE	COND
92.19	68.75

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T17,T46
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T17

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T10,T11
1	Covered	T2,T3,T4

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T17,T46
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T10,T17,T46

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T17,T46

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T17,T46

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T10,T17,T46
1	Covered	T2,T3,T4

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avsetupfifo

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T2,T3,T4

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T17,T46
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T10,T17,T46

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T17,T46
0	Covered	T2,T3,T4

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
90.62	100.00

tb.dut.usbdev_rxfifo

SCORE	BRANCH
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	BRANCH
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T10,T11

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T11
0	Covered	T2,T3,T4

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	454804649	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	449408987	0	0
gen_passthru_fifo.paramCheckPass	8886	8886	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	454804649	0	0
T2	2015550	400535	0	0
T3	2007740	401252	0	0
T4	2007795	36	0	0
T5	4013190	58	0	0
T8	402099	0	0	0
T9	401512	0	0	0
T10	4018070	400626	0	0
T11	4056420	401975	0	0
T12	0	26218	0	0
T15	2008835	0	0	0
T16	2016050	401840	0	0
T17	4023800	400978	0	0
T18	4082230	402401	0	0
T19	4050400	401490	0	0
T20	4028710	400264	0	0
T21	405092	0	0	0
T30	405746	0	0	0
T32	2035800	401835	0	0
T46	0	40	0	0
T48	13011	7755	0	0
T76	0	34	0	0
T77	0	13	0	0
T78	0	10	0	0
T79	0	10	0	0
T80	0	30	0	0
T81	0	55	0	0
T82	404563	0	0	0
T83	402485	0	0	0
T84	402988	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T2	4837320	4836480	0	0
T3	4818576	4817472	0	0
T4	4818708	4816956	0	0
T5	4815828	4814628	0	0
T10	4821684	4820892	0	0
T11	4867704	4866672	0	0
T17	4828560	4827648	0	0
T18	4898676	4897704	0	0
T19	4860480	4859760	0	0
T20	4834452	4833648	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T2	4837320	4836480	0	0
T3	4818576	4817472	0	0
T4	4818708	4816956	0	0
T5	4815828	4814628	0	0
T10	4821684	4820892	0	0
T11	4867704	4866672	0	0
T17	4828560	4827648	0	0
T18	4898676	4897704	0	0
T19	4860480	4859760	0	0
T20	4834452	4833648	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T2	4837320	4836480	0	0
T3	4818576	4817472	0	0
T4	4818708	4816956	0	0
T5	4815828	4814628	0	0
T10	4821684	4820892	0	0
T11	4867704	4866672	0	0
T17	4828560	4827648	0	0
T18	4898676	4897704	0	0
T19	4860480	4859760	0	0
T20	4834452	4833648	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	449408987	0	0
T2	403110	400479	0	0
T3	401548	401170	0	0
T4	401559	0	0	0
T5	1605276	0	0	0
T8	402099	0	0	0
T9	401512	0	0	0
T10	1607228	400574	0	0
T11	1622568	401915	0	0
T12	0	13698	0	0
T15	1205301	0	0	0
T16	1209630	401840	0	0
T17	1609520	400910	0	0
T18	1632892	402287	0	0
T19	1620160	401434	0	0
T20	1611484	400152	0	0
T21	405092	400632	0	0
T25	0	400423	0	0
T30	405746	0	0	0
T32	1221480	401835	0	0
T46	0	24	0	0
T48	13011	7755	0	0
T76	0	22	0	0
T77	0	8	0	0
T78	0	6	0	0
T79	0	6	0	0
T80	0	18	0	0
T81	0	33	0	0
T82	404563	0	0	0
T83	402485	0	0	0
T84	402988	0	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886	8886	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T10	6	6	0	0
T11	6	6	0	0
T17	6	6	0	0
T18	6	6	0	0
T19	6	6	0	0
T20	6	6	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T17

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T10,T11
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T10,T11

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T11
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522241227	2360560	0	0
DepthKnown_A	522241227	522122836	0	0
RvalidKnown_A	522241227	522122836	0	0
WreadyKnown_A	522241227	522122836	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	522241227	2360560	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	2360560	0	0
T2	403110	1418	0	0
T3	401548	0	0	0
T4	401559	0	0	0
T5	401319	0	0	0
T10	401807	96	0	0
T11	405642	108	0	0
T17	402380	81	0	0
T18	408223	3466	0	0
T19	405040	2407	0	0
T20	402871	117	0	0
T37	0	98	0	0
T46	0	81	0	0
T79	0	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	2360560	0	0
T2	403110	1418	0	0
T3	401548	0	0	0
T4	401559	0	0	0
T5	401319	0	0	0
T10	401807	96	0	0
T11	405642	108	0	0
T17	402380	81	0	0
T18	408223	3466	0	0
T19	405040	2407	0	0
T20	402871	117	0	0
T37	0	98	0	0
T46	0	81	0	0
T79	0	81	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T17,T46
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T10,T17,T46

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T17,T46

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T17,T46

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T10,T17,T46
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T10,T17,T46

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T17,T46
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522241227	216259	0	0
DepthKnown_A	522241227	522122836	0	0
RvalidKnown_A	522241227	522122836	0	0
WreadyKnown_A	522241227	522122836	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	522241227	216259	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	216259	0	0
T5	401319	0	0	0
T10	401807	2	0	0
T11	405642	0	0	0
T12	0	3719	0	0
T15	401767	0	0	0
T16	403210	0	0	0
T17	402380	6	0	0
T18	408223	0	0	0
T19	405040	0	0	0
T20	402871	0	0	0
T32	407160	0	0	0
T46	0	8	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	6	0	0
T81	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	216259	0	0
T5	401319	0	0	0
T10	401807	2	0	0
T11	405642	0	0	0
T12	0	3719	0	0
T15	401767	0	0	0
T16	403210	0	0	0
T17	402380	6	0	0
T18	408223	0	0	0
T19	405040	0	0	0
T20	402871	0	0	0
T32	407160	0	0	0
T46	0	8	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	6	0	0
T81	0	11	0	0

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T49,T50
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T48,T21,T25

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T48,T21,T25

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T48,T21,T25
1	1	0	Not Covered
1	1	1	Covered	T21,T25,T26

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T48,T21,T25
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522241227	60584920	0	0
DepthKnown_A	522241227	522122836	0	0
RvalidKnown_A	522241227	522122836	0	0
WreadyKnown_A	522241227	522122836	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	522241227	60584920	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	60584920	0	0
T8	402099	0	0	0
T9	401512	0	0	0
T21	405092	400632	0	0
T22	402307	0	0	0
T25	0	400423	0	0
T26	0	401144	0	0
T30	405746	0	0	0
T38	406334	0	0	0
T44	0	400551	0	0
T48	13011	7755	0	0
T49	0	8181	0	0
T50	0	2234	0	0
T82	404563	0	0	0
T83	402485	0	0	0
T84	402988	0	0	0
T85	0	402008	0	0
T86	0	400652	0	0
T87	0	2107	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	60584920	0	0
T8	402099	0	0	0
T9	401512	0	0	0
T21	405092	400632	0	0
T22	402307	0	0	0
T25	0	400423	0	0
T26	0	401144	0	0
T30	405746	0	0	0
T38	406334	0	0	0
T44	0	400551	0	0
T48	13011	7755	0	0
T49	0	8181	0	0
T50	0	2234	0	0
T82	404563	0	0	0
T83	402485	0	0	0
T84	402988	0	0	0
T85	0	402008	0	0
T86	0	400652	0	0
T87	0	2107	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T49,T50
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T11

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522241227	385080317	0	0
DepthKnown_A	522241227	522122836	0	0
RvalidKnown_A	522241227	522122836	0	0
WreadyKnown_A	522241227	522122836	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	522241227	385080317	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	385080317	0	0
T2	403110	400479	0	0
T3	401548	401170	0	0
T4	401559	0	0	0
T5	401319	0	0	0
T10	401807	400568	0	0
T11	405642	401915	0	0
T16	0	401840	0	0
T17	402380	400892	0	0
T18	408223	402287	0	0
T19	405040	401434	0	0
T20	402871	400152	0	0
T32	0	401835	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	385080317	0	0
T2	403110	400479	0	0
T3	401548	401170	0	0
T4	401559	0	0	0
T5	401319	0	0	0
T10	401807	400568	0	0
T11	405642	401915	0	0
T16	0	401840	0	0
T17	402380	400892	0	0
T18	408223	402287	0	0
T19	405040	401434	0	0
T20	402871	400152	0	0
T32	0	401835	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T17,T46
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T10,T17,T46

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T17,T46

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T10,T78,T76
1	1	0	Not Covered
1	1	1	Covered	T10,T17,T46

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T10,T17,T46
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T10,T17,T46

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T17,T46
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522241227	732698	0	0
DepthKnown_A	522241227	522122836	0	0
RvalidKnown_A	522241227	522122836	0	0
WreadyKnown_A	522241227	522122836	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	522241227	732698	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	732698	0	0
T5	401319	0	0	0
T10	401807	2	0	0
T11	405642	0	0	0
T12	0	6260	0	0
T15	401767	0	0	0
T16	403210	0	0	0
T17	402380	6	0	0
T18	408223	0	0	0
T19	405040	0	0	0
T20	402871	0	0	0
T32	407160	0	0	0
T46	0	8	0	0
T76	0	10	0	0
T77	0	3	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	6	0	0
T81	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	732698	0	0
T5	401319	0	0	0
T10	401807	2	0	0
T11	405642	0	0	0
T12	0	6260	0	0
T15	401767	0	0	0
T16	403210	0	0	0
T17	402380	6	0	0
T18	408223	0	0	0
T19	405040	0	0	0
T20	402871	0	0	0
T32	407160	0	0	0
T46	0	8	0	0
T76	0	10	0	0
T77	0	3	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	6	0	0
T81	0	11	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T76,T77,T21
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T10,T17,T46

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T17,T46

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T10,T78,T76
1	1	0	Not Covered
1	1	1	Covered	T10,T17,T46

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T10,T17,T46

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T10,T17,T46

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T76,T77,T21
1	0	Covered	T10,T17,T46
1	1	Covered	T2,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T10,T17,T46
1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T17,T46
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T10,T17,T46

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T17,T46
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522241227	434233	0	0
DepthKnown_A	522241227	522122836	0	0
RvalidKnown_A	522241227	522122836	0	0
WreadyKnown_A	522241227	522122836	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	522241227	434233	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	434233	0	0
T5	401319	0	0	0
T10	401807	2	0	0
T11	405642	0	0	0
T12	0	3719	0	0
T15	401767	0	0	0
T16	403210	0	0	0
T17	402380	6	0	0
T18	408223	0	0	0
T19	405040	0	0	0
T20	402871	0	0	0
T32	407160	0	0	0
T46	0	8	0	0
T76	0	10	0	0
T77	0	3	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	6	0	0
T81	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	522122836	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	522241227	434233	0	0
T5	401319	0	0	0
T10	401807	2	0	0
T11	405642	0	0	0
T12	0	3719	0	0
T15	401767	0	0	0
T16	403210	0	0	0
T17	402380	6	0	0
T18	408223	0	0	0
T19	405040	0	0	0
T20	402871	0	0	0
T32	407160	0	0	0
T46	0	8	0	0
T76	0	10	0	0
T77	0	3	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	6	0	0
T81	0	11	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	523818771	1098790	0	0
DepthKnown_A	523818771	523657483	0	0
RvalidKnown_A	523818771	523657483	0	0
WreadyKnown_A	523818771	523657483	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	1098790	0	0
T2	403110	14	0	0
T3	401548	8	0	0
T4	401559	9	0	0
T5	401319	7	0	0
T10	401807	13	0	0
T11	405642	15	0	0
T17	402380	17	0	0
T18	408223	10	0	0
T19	405040	14	0	0
T20	402871	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	523818771	1630787	0	0
DepthKnown_A	523818771	523657483	0	0
RvalidKnown_A	523818771	523657483	0	0
WreadyKnown_A	523818771	523657483	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	1630787	0	0
T2	403110	14	0	0
T3	401548	33	0	0
T4	401559	9	0	0
T5	401319	22	0	0
T10	401807	13	0	0
T11	405642	15	0	0
T17	402380	17	0	0
T18	408223	47	0	0
T19	405040	14	0	0
T20	402871	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	523818771	401451	0	0
DepthKnown_A	523818771	523657483	0	0
RvalidKnown_A	523818771	523657483	0	0
WreadyKnown_A	523818771	523657483	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	401451	0	0
T5	401319	0	0	0
T10	401807	2	0	0
T11	405642	0	0	0
T12	0	6260	0	0
T15	401767	0	0	0
T16	403210	0	0	0
T17	402380	6	0	0
T18	408223	0	0	0
T19	405040	0	0	0
T20	402871	0	0	0
T32	407160	0	0	0
T46	0	8	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	6	0	0
T81	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	523818771	809481	0	0
DepthKnown_A	523818771	523657483	0	0
RvalidKnown_A	523818771	523657483	0	0
WreadyKnown_A	523818771	523657483	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	809481	0	0
T5	401319	0	0	0
T10	401807	2	0	0
T11	405642	0	0	0
T12	0	6260	0	0
T15	401767	0	0	0
T16	403210	0	0	0
T17	402380	6	0	0
T18	408223	0	0	0
T19	405040	0	0	0
T20	402871	0	0	0
T32	407160	0	0	0
T46	0	8	0	0
T76	0	10	0	0
T77	0	3	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	6	0	0
T81	0	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	523818771	633847	0	0
DepthKnown_A	523818771	523657483	0	0
RvalidKnown_A	523818771	523657483	0	0
WreadyKnown_A	523818771	523657483	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	633847	0	0
T2	403110	14	0	0
T3	401548	8	0	0
T4	401559	9	0	0
T5	401319	7	0	0
T10	401807	11	0	0
T11	405642	15	0	0
T17	402380	11	0	0
T18	408223	10	0	0
T19	405040	14	0	0
T20	402871	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	523818771	821306	0	0
DepthKnown_A	523818771	523657483	0	0
RvalidKnown_A	523818771	523657483	0	0
WreadyKnown_A	523818771	523657483	0	0
gen_passthru_fifo.paramCheckPass	1481	1481	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	821306	0	0
T2	403110	14	0	0
T3	401548	33	0	0
T4	401559	9	0	0
T5	401319	22	0	0
T10	401807	11	0	0
T11	405642	15	0	0
T17	402380	11	0	0
T18	408223	47	0	0
T19	405040	14	0	0
T20	402871	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523818771	523657483	0	0
T2	403110	403040	0	0
T3	401548	401456	0	0
T4	401559	401413	0	0
T5	401319	401219	0	0
T10	401807	401741	0	0
T11	405642	405556	0	0
T17	402380	402304	0	0
T18	408223	408142	0	0
T19	405040	404980	0	0
T20	402871	402804	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1481	1481	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0